Theoretical and Experimental Substractions of Device Temperature Determination Utilizing I-V Characterization Applied on AlGaN/GaN HEMT

Abstract

A differential analysis of electrical attributes, including the temperature profile and trapping phenomena is introduced using a device analytical spatial electrical model. The resultant current difference caused by the applied voltage variation is divided into isothermal and thermal sections, corresponding to the instantaneous time- or temperature-dependent change. The average temperature relevance is explained in the theoretical section with respect to the thermal profile and major parameters of the device at the operating point. An ambient temperature variation method has been used to determine device average temperature under quasi-static state and pulse operation, was compared with respect to the threshold voltage shift of a high-electron-mobility transistor (HEMT). The experimental sections presents theoretical subtractions of average channel temperature determination including trapping phenomena adapted for the AlGaN/GaN HEMT. The theoretical results found using the analytical model, allow for the consolidation of specific methodologies for further research to determine the device temperature based on spatially distributed and averaged parameters.

1. Introduction

The commercial wireless market requires more demanding microwave operation with higher requirements in terms of self-heating, high operating voltage and inherent processes and their impact on the device reliability in consumer electronics [1,2,3]. The presence of two-dimensional electron gas (2DEG) in a gallium nitride (GaN) based structure presents the potential to fabricate high electron mobility transistors (HEMTs) with Schottky diodes employed as excellent devices for application in the microwave and power conversion field. The suppression of the critical temperature increase, caused by high power density along the device active area, requires the utilization of high thermal conductance substrates e.g., silicon carbide (SiC) [4]. Since the devices are microscopic in size, the conventional methods lack the accuracy to estimate the device operating temperature.

Numerous experimental methods were developed to determine the temperature inside and nearby active device area such as Raman spectroscopy or interferometric mapping [5,6,7]. Additionally, various methods utilizing external heating, or a low-power operating regime were employed, taking advantage of specific electro-thermal device properties. However, these methods, that are widely applied to determine average temperature of HEMT operating in the saturation regime, suffer from a lack of accuracy due to the marginalization of the drain current increase caused by, e.g., gate length modulation or leakage effects [8,9,10]. Moreover, the current comparison at the defined operating point to the peak current under short-pulsed operation at various ambient temperatures [11] in these devices does not account for time dependent isothermal phenomena caused processes such as by charge trapping.

Although device thermal simulations, based on non-linear equations, resolve thermal processes inside the structure [12], the combined integral and differential analysis of the resultant current and the separation of the isothermal and thermal sections are emphasized in this work. The complex theoretical considerations, utilizing thermal profile variation, were simplified and adapted for the practical purposes to acquire the average HEMT channel temperature. The theoretical and experimental results obtained are present the potential to improve and consolidate the already utilized methodologies described empirically for specific devices.

2. Theory

2.1. Electrical Model

The presented model is possible to be applied to an n-port device with applied voltage V_n considering resultant current I at one port and neglecting the other port current. Devices meeting these requirements are e.g., Schottky diode, ungated or gated transmission line model (TLM) structure such as field-effect transistor (FET) when neglecting the gate current.

The resultant current change dI (∆I) consists of an isothermal section dI_E (∆I_E) induced by applied voltage change dV_n (∆V_n) and isothermal trapped charge variation dQ_TE(X) (∆Q_TE(X)) and thermal section dI_T (∆I_T) assigned to spatial temperature change dT(X) (∆T(X)) and the thermal trapped charge variation dQ_TT(X) (∆Q_TT(X)):

$$dI=d{I}_E+d{I}_T$$

(1)

The current change is defined for the time interval dt (∆t) considering the device area consisting of spatial elements dX (∆X) and thermal profile T(X). The resultant trapped charge dQ_T (X) (∆Q_T (X)) is defined in a similar way, as follows:

$$d{Q}_T\left(X\right)=d{Q}_{TE}\left(X\right)+d{Q}_{TT}\left(X\right)$$

(2)

In general, dI_E is related to dV_n and dQ_TE(X) by time invariant coefficients k_Vn and k_Q(X), respectively, whereas dI_T is related to dT(X) and dQ_TT(X) by time invariant coefficients k_T(X) and k_Q(X), respectively:

$$d{I}_E=k_{Vn}d{V}_n+\underset{X}{\overset{}{{\displaystyle \iiint }}}{k}_Q\left(X\right)d{Q}_{TE}\left(X\right)dX$$

(3)

$$d{I}_T=\underset{X}{\overset{}{{\displaystyle \iiint }}}\left[k_T\left(X\right)+k_Q\left(X\right)k_{TT}\left(X\right)\right]dT\left(X\right)dX$$

(4)

In (4) $k_{TT}\left(X\right)=d{Q}_{TT}\left(X\right)/dT\left(X\right)$ is time and state dependent variable. The coefficients k_Q(X), k_T(X), k_TT(X) and k_Vn at the operating point defined by V_n, I and T(X) at time t can be obtained using an analytical solution or advanced simulation software calibrated by experimental results. Although the majority of commercially utilized simulation software allows for self-heating to be switched off/on [12] or DC measurements to be realized in a pulse or quasi-static state [13], it is impossible to turn self-heating on separately to obtain T(X) and I at a predefined operating point and to subsequently turn it off for ∆t and ∆V_n to separate ΔI_T and ΔI_E.

It is recommended that the device current response of a stepping and rectangular pulse source is differentiated into time elements Δt to find the particular ΔI_E and ΔI_T as shown in Figure 1a,b, respectively. The small parasitic capacitance, typical for GaN-based devices, and a short switching time of the stepping source in comparison with thermal and trapping time constants make it possible for ∆I_T to be obtained as the difference between I acquired at t₁+Δt^′ and at t₁+Δt in the case of a negligible ΔQ_TE(X). To reach an equilibrium state during quasi-static stepping, the voltage source measurements shown in Figure 1a, Δt is utilized much higher than the thermal and trapping time constants. For the pulse voltage source measurements initialized at time t₀ depicted in Figure 1b, the temperature T(X) ≈ T₀ is found along the active device area at $t\approx t_1$, that it is zero ΔV_n at $t>t_1$ and a negligible ΔQ_TE(X) results in ΔI_T ≈ ΔI. Otherwise, ΔQ_TE(X) is required to be incorporated into ΔI_E as illustrated below.

2.2. Average Temperature Definition

To avoid thermal gradient calculations, the average temperature contribution dT_A in the active device area X_A is defined by the substitution of $k_T^I\left(X\right)=k_T\left(X\right)+k_Q\left(X\right)k_{TT}\left(X\right)$ and the spatially independent thermal coefficient k_T related to the operating point:

$$d{I}_T=k_T\left(T_A,V_n, t\right)d{T}_A=\underset{X_A}{\overset{}{{\displaystyle \iiint }}}{k}_T^I\left(X\right)dT\left(X\right)dX$$

(5)

To eliminate the $k_T^I\left(X\right)$ spatial determination, the approximation, demonstrated by an infinite thermal conductance for which the power density of X_A does not perform a function, is usually utilized to calculate average temperature T_A with trapping centers thermally excited by the same dT_A. Therefore the $k_T={{\displaystyle \iiint }}_{X_A}{k}_T^I\left(X\right)dX$ as T_A, V_n and t dependent are used in the following way:

$$d{I}_T=k_T\left(T_A,V_n, t\right)d{T}_A=\left[\underset{X_A}{\overset{}{{\displaystyle \iiint }}}{k}_T^I\left(X\right)dX\right]d{T}_A$$

(6)

The deviation between (5) and (6) leads to a discrepancy in T_A determination, especially for different heat flux distributions caused by power dissipation, ambient temperature and time variation. For a spatially independent k_T(X), k_Q(X) or k_TT(X) in X_A, (5) and (6) appear identical, resulting in $k_T=k_T^I\left(X\right)X_A$ and subsequently dT_A as the thermodynamic average temperature contribution in X_A:

$$d{T}_A=X_A^{-1}\underset{X_A}{\overset{}{{\displaystyle \iiint }}}dT\left(X\right)dX$$

(7)

2.3. Ambient Temperature Variation

The average temperature determination method depicted in Figure 2a is based on the resultant current I comparison with an isothermal device current I_E at time t₁ after the measurement initialization at time t₀, where the maximum I and I_E should be reached at time t₀’. The trapping effects must be included in I_E as illustrated below. In spite of the zero thermal contribution ${{\displaystyle \iiint }}_X{k}_T^I\left(X\right)d{T}_E\left(X\right)dX$ to I_E, the variation of the isothermal temperature profile T_E(X), together with a spatially dependent $k_T^I\left(X\right)$, results in a thermodynamic average temperature deviation from the initial temperature at t₀, caused by the difference between (5) and (6). Therefore, this method is found to be sufficient for devices with a relatively small active area or negligible spatial $k_T^I\left(X\right)$ variation.

Two identical measurements at distinct ambient temperatures, such that T₀₁ ≈ T₀ and T₀₂ ≈ T₀ + ΔT^* with a small temperature difference ΔT* result in the current I₁ and I₂, temperature profiles T₁(X) and T₂(X), as depicted in Figure 2b, and exhibit the temperature profile difference $\Delta T^{*}\left(X\right)=T_2\left(X,t_1\right)-T_1\left(X,t_1\right)\approx T_2\left(X,t_1+\Delta t\right)-T_1\left(X,t_1+\Delta t\right)$, $\Delta T\left(X\right)=T_1\left(X,t_1+\Delta t\right)-T_1\left(X,t_1\right)$ and the differential current $\Delta I=I_1\left(t_1+\Delta t\right)-I_1\left(t_1\right)$, $\Delta I^{*}=I_2\left(t_1\right)-I_1\left(t_1\right)\approx I_2\left(t_1+\Delta t\right)-I_1\left(t_1+\Delta t\right)$. The assumption of a low Δt means that the following formula is applicable for quasi-static and pulsed operations:

$$\Delta I^{*}=\underset{X}{\overset{}{{\displaystyle \iiint }}}{k}_T^I\left(X\right)\Delta T^{*}\left(X\right)dX$$

(8)

The substitution of $\Delta T^{*}\left(X\right)=\Delta T\left(X\right)-\Delta T_E\left(X\right)$ and $\Delta T_E\left(X\right)=T_1\left(X,t_1+\Delta t\right)-T_2\left(X,t_1\right)$ in (8), utilized for the dI_T comparison with $\Delta I_T={{\displaystyle \iiint }}_X^{}{k}_T^I\left(X\right)\Delta T\left(X\right)dX$ based on the comparison of difference and differential substitution $d{I}_T/\Delta I_T=dT\left(X\right)/\Delta T\left(X\right)$, results in:

$$\frac{d{I}_T}{\Delta I^{*}}=\frac{{{\displaystyle \iiint }}_X^{}{k}_T^I\left(X\right)dT\left(X\right)dX}{{{\displaystyle \iiint }}_X^{}{k}_T^I\left(X\right)\Delta T^{*}\left(X\right)dX}$$

(9)

As a result, a T_A definition utilizing (6) and substitution X ≈ X_A, dI_T and ΔI^* caused by ΔV_n and ΔT₀ leading to dT_A and ∆T_A^*, respectively, leads (9) to the following relationship:

$$d{I}_T/\Delta I^{*}=d{T}_A/\Delta T_A^{*}$$

(10)

However, despite the zero I_E thermal current, a non-zero ∆T_E(X) variation results in a discrepancy between the definition of dT_A and ∆T_A* by (7) and the definition utilizing infinite thermal conductance of the device active area, on the other side. Nevertheless, the T_A determination methods utilizing (10) are found to be sufficient for devices with a negligible spatial $k_T^I\left(X\right)$ variation or a relatively small active area.

Already known ∆T_A^* and ΔI_E time dependence allows to obtain T_A as the sum of dT_A calculated in (10) in the quasi-static or pulsed operating regime. Temperature dependent thermal resistance and thermal capacity result in a ∆T_A* deviation from ΔT₀. Quasi-static state methods, utilizing the T₀ variation, allows for the calculation of dT_A and ∆T_A* [9,14].

2.4. Trapping Effects Approximation in FET

We further consider the T_A determination of the FET-neglecting parasitic gate, and its entire electric capacitance. Even a relative carrier velocity v change, and pinch-off area formation are thought to have no impact on channel potential distribution along the channel [15,16].

The threshold voltage V_TH shift is related to the time and temperature variation of energy barrier height, free charge concentration along the conductive channel as well as charge trapping, resulting in the additional virtual gate electrode. The gate voltage V_GS, drain voltage V_DS and ambient temperature T₀ variation causes dT_A, with a direct impact on the v and V_TH change. These variations result from the isothermal section dV_THN, caused by an immediate band energy diagram and free charge concentration change. The isothermal section dV_THE, is a result of the trapping phenomena during the defined time and the thermal section dV_THT originates from thermal carrier and trap center density change.

A widely utilized FET approximation [15] in the case of stepping V_DS and/or V_GS at a defined T₀ is as follows:

$$dI=g_{M0}\left(d{V}_{GS}-d{V}_{THE}-d{V}_{THT}\right)+g_{D0}d{V}_{DS}+d{I}_{TV}$$

(11)

It is possible to acquire the isothermal transconductance g_M0 and output conductance g_D0 via immediate isothermal V_DS and V_GS responses, including $d{V}_{THN}/d{V}_{DS}$ and $d{V}_{THN}/d{V}_{GS}$. The term dI_TV represents the thermal change caused by dV_DS, dV_GS and dT₀ and has a major impact on v, excluding dV_TH. A substitution of $d{I}_0=g_{M0}d{V}_{GS}+g_{D0}d{V}_{DS}$ and $dI=d{I}_E+d{I}_T$, as applied in (11), results in:

$$d{I}_E=d{I}_0-g_{M0}d{V}_{THE}$$

(12)

$$d{I}_T=dI-d{I}_E=d{I}_{TV}-g_{M0}d{V}_{THT}$$

(13)

A common way to obtain V_TH is pulsed and/or quasi-static transfer I-V characteristics utilization at defined T₀ and V_DS assuming V_TH independent on V_GS as well as an approximation of isothermal and measured I-V characteristics pointing on the same V_TH shift at T₀ in the operating range. Trapping phenomena and voltage drop in the source-to-gate and drain-to-source area have a partial influence on the V_TH determination especially for low applied V_DS or non-linear V_TH vs. V_DS dependence. The following ways of trapping effects incorporation in T_A calculation coming out of V_TH determination from transfer I-V characteristics are explained.

In the case of the quasi-static state operation V_TH shift, resulting in $\left(d{V}_{THE}+d{V}_{THN}\right)/d{V}_{DS}$ caused by T₀ and V_DS variation, can be simply obtained from quasi-static I-V characteristics. Transfer I-V characteristics, measured by short-pulsed V_GS and V_DS offering trap influence separation, allow to get $d{V}_{THN}/d{V}_{DS}$ obtained from negative V_TH shift caused by roll-off effect in short-channel FET [15,17]. Subsequently, the ratio $d{V}_{THE}/d{V}_{DS}$ dependent on V_DS and T₀ is acquired and utilized in (12), whereby dI₀ is acquired at the beginning of V_DS and/or V_GS step, a measured transconductance $g_M\gg \left|g_M-g_{M0}\right|$ is supposed. For a significant $g_{M}d{V}_{THE}/d{V}_{DS}$ temperature variation in comparison with $d{I}_T/d{V}_{DS}$ an iteration process is required for T_A determination.

For V_DS and/or V_GS pulse responses, depicted in Figure 1b, the pulsed transfer I-V characteristics are measured utilizing V_GS and/or V_DS quiescent biasing and/or voltage pulses. At T₀ and the defined time t₁ after the increase of constant amplitude V_DS and the sweeping amplitude V_GS, drain currents are acquired to extract the V_TH as t₁ and T₀ functions. At the time interval ∆t, during the pulse, $\Delta V_{THE}=V_{TH}\left(T_A, t_1+\Delta t\right)-V_{TH}\left(T_A, t_1\right)$ gives the opportunity to utilize $\mathsf{\Delta }{I}_E=-g_{M0}\Delta V_{THE}$ for both a small Δt and ΔV_THE corresponding to the virtual gate electrode potential shift, neglecting the g_M0 time variation. The maximum resultant current I_E and V_TH, obtained immediately after V_GS and/or V_DS rising edges at t₀, provides the opportunity to plot the I_E time dependence at T₀, depicted in Figure 2a:

$$I_E\left(t_1\right)=I_E\left(t_0^{\prime }\right)-g_{M0}\left[V_{TH}\left(t_1\right)-V_{TH}\left(t_0^{\prime }\right)\right]$$

(14)

In the considerations above a thermal gradient along the active device area that effects the trap spatial localization is truncated. Isothermal trapping phenomena and a voltage drop in the source-to-gate and the drain-to-source area having a partial influence on V_TH shift are neglected as well. Despite this, an appropriate analytical approximation of the I-V characteristics provides an opportunity to predict the trapping phenomena in particular devices. An advantage of the T₀ variation method during the device operation is that the calibration of for $d{I}_{TV}/d{T}_A$ vs. T_A, V_DS and V_GS with an additional trapping phenomena analysis is not required.

2.5. Short Time Response Current Utilization

Many of the experimental methods that are widely utilized for the T_A acquisition of FET in a saturation regime are based on a zero isothermal drain current change $d{I}_E/d{V}_{DS}$ at constant V_GS. The requirement of zero dI_E in (12) is satisfied for a gate length modulation or a leakage current increase compensated by the trapping phenomena in the saturation regime, resulting in $d{I}_E\ll d{I}_T$. Long-channel FET excluding V_DS such as V_GS dependent charge trapping variation meets this condition therefore the methods to acquire T_A in quasi-static operation coming out from temperature calibration of major electrical parameters [8,16] or ambient temperature variation [9,18] require standard DC measuring equipment. The dI_E prediction at various ambient temperatures, using an analytical model or simulation software also makes such methods applicable for short-channel FET [17,18].

In general, the resultant current acquisition after a short period after the voltage step/pulse is required, to obtain the dI₀. The method depicted in Figure 2a is simply applicable for devices exhibiting relatively short time responses t₀’–t₀, operating in the quasi-static and dynamic state as well providing the opportunity to obtain an isothermal trapping effects approximation. However a switching time of ~10⁻⁸ s is required for full load turning-on, which makes the experimental setup more expensive.

3. Experimental

3.1. Structure Design and Experimental Setup

The investigated Al_0.25Ga_0.75N/GaN HEMT structure, including 14 nm Al_0.25Ga_0.75N/1.5 nm AlN/1700 nm GaN/75 nm thermal boundary resistance layer (TBR) heterostructure was grown by MOVPE on a 70 μm thick 4H-SiC substrate, containing the backside Au contact, which was soldered to 1 mm thick CuMo leadframe using a 60 μm thick AuSn solder. The top ohmic drain/source and gate contacts were created via standard Au-based metallization. A gated transmission line model (GTLM) HEMT with a width of w ≈ 100 μm, a gate with a length of d_G ≈ 0.15 μm, asource to gate gap of length d_GS ≈ 0.75 μm and the drain to gate gap of length d_GS ≈ 1.5 μm was investigated [14]. The device is placed in an open package located on the Al thermal chuck and maintainedat a constant temperature.

A semiconductor parameter analyzer Agilent 4155C and controlled thermal chuck were utilized to acquire the output characteristics at zero gate-source voltage V_GS and the drain-source voltage V_DS varied from 0 V up to 20 V. The chuck temperature was set in the range of 25–185 °C to demonstrate methods based on ambient temperature and threshold voltage variation. The device trapping level was reset via white LED illumination for one minute between quasi-static measurements. The 3D model incorporating device geometry, layout and thicknesses of individual layers was created using the 3D thermal FEM simulations performed by Synopsys TCAD Sentaurus [12]. The material thermal conductivity and capacity values were obtained from the previous work and calibrated utilizing the measurements provided [19,20]. The constant ambient temperature boundary condition was set to the structure backside, assuming an ideal heat transfer between leadframe and heatsink. The structure’s self-heating is simulated by three thermal contacts placed along 2DEG, between the drain and source, representing heat contribution from the drain to the source access region, under the gate electrode and the pinch-off region located at the drain side gate edge [19].

3.2. Average Channel Temperature Determination

The drain-source current I_DS dependence on drain-source voltage V_DS for gate-source voltage V_GS = 0 V at varying ambient temperature T₀ in the range of 25–105 °C was acquired during the V_DS step, for a period of period ~1 s using the quasi-static operation as depicted in Figure 3. The maximum I_DS obtained at the beginning of the extended V_DS step ∆V_DS ≈ 2 V, and subtracted by I_DS value, that were acquired under quasi-static operation from the previous V_DS step, results in dI₀. Quasi-static and pulsed transfer I-V characteristics show soft g_M and a g_M0 decrease with rising V_DS and T₀ as illustrated in Figure 4. In particular, the V_TH and V_THT were obtained from square rooted transfer I-V characteristics resulting in constant $d{V}_{THE}/d{V}_{DS}$ for a defined T_A. Therefore $d{V}_{THE}/d{V}_{DS}\approx \left(d{V}_{TH}-d{V}_{THN}\right)/d{V}_{DS}$ is approximately $d{V}_{THE}/d{V}_{DS}\approx k_{THE}\left(T_A-T_{00}\right)+k_{TH00}$, T₀₀ ≈ 25 °C, $k_{THE}\approx 8.8·{10}^{-6}{\mathrm{K}}^{-1}$ and $k_{TH00}\approx 1.97·{10}^{-3}$ for T_A (°C) in the saturation area. However, T_A above T₀ ≈ 105 °C was reached, which results in $g_{M}d{V}_{THE}/d{V}_{DS}$ being linearly approximated, exhibiting variations of ~ 8·10⁻⁸°V/K in the range of 25–225 °C, corresponding to ~10% of $d{I}_T/d{V}_{DS}$. Interpolated thermal and isothermal parts of $d{I}_{DS}/d{V}_{DS}$ vs. V_DS at T₀ ≈ 25 °C are depicted in Figure 5. Moreover, the dissipated power contribution $d{P}^{*}=V_{DS}\Delta I^{*}$, caused by dT₀ for low V_DS negligible in comparison with $dP=V_{DS}d{I}_{DS}+I_{DS}d{V}_{DS}$ caused by dV_DS, results in the simplified formula for differential thermal resistance R_A0(T₀) calculation [14] utilizing (12):

$$R_{A0}=\left(d{T}_0^{*}/dP\right)\left(dI-d{I}_0+g_{M}d{V}_{THE}\right)/\Delta I^{*}$$

(15)

The linear approximation $T_A-T_0\approx R_{A0}P$, utilized in the first $g_{M}d{V}_{THE}$ iteration step in (15), leads to a formula resulting in R_A0(T₀) plot at different T₀ and V_DS as shown in Figure 6:

$$R_{A0}=\frac{d{I}_{DS}-d{I}_0+g_M\left[k_{THE}\left(T_0-T_{00}\right)+k_{TH00}\right]d{V}_{DS}}{\left(\Delta I^{*}dP/d{T}_0^{*}\right)-\left(g_M{k}_{THE}{V}_{DS}{I}_{DS}d{V}_{DS}\right)}$$

(16)

Increasing V_DS results in different R_A0 values at a defined T_0, which is partially caused by spatially distributed electrical parameters of the active device area such as the $g_{M}d{V}_{THE}/d{V}_{DS}$ variation. The approximation $R_{A0}\approx k_{RA}\left(T_0-T_{00}\right)+R_{00}$, T₀₀ ≈ 25 °C, $k_{RA}\approx 0.2{ \mathrm{W}}^{-1}$, $R_{00}\approx 57.0 \mathrm{K}/\mathrm{W}$ at the defined T₀ was utilized to calculate T_A in a recurrent way [14] as illustrated in Figure 7. In [8] the major contribution of the thermal I_DS section is assigned to the serial source area resistance increase, caused by self-heating in a saturation regime for AlGaN/GaN HEMT. The simulated average channel temperature of the source to the gate area is in acceptable agreement in comparison to the calculated T_A.

For the T_A investigation of HEMT in the pulse operation, V_GS and V_DS bias was set to zero, superimposed by a V_DS = 20 V pulse of length ~1 s. In the case of non-zero biasing, the initial condition of zero power dissipation is required to be satisfied. The period of ~5 s between voltage pulses was found sufficient because of the absence of the automated white LED illumination during the pulse breaks. The resultant current I_DS acquired at T₀ and delay t₁ after the rising edge of constant amplitude V_DS = 20 V and V_GS amplitude sweeping from −4 V to −2 V at defined points, allowed us to plot the transfer I-V characteristics and to subsequently obtain the V_TH dependent on t₁ in the logarithmic scale in the range of 10⁻⁷–1 s, where the T₀ step is set linearly in the range of 25–185 °C. Experimentally acquired I_DS in the range of 20–100 ns and 25–185 °C for pulsed V_DS = 20 V and zero V_GS are depicted in Figure 8. Setting the V_GS =−0.5 V allows us to obtain the supposed g_M0 constant at the defined T₀ due to a small deviation under isothermal conditions.

Although in the theoretical section the maximum I_DS obtained at t₀ ≈ 60–90 ns is suggested as the initial resultant current I_DS0 at T₀, simulation results exhibit higher T_A than T₀ by 30–50 °C at t₀ which is caused by the rapid device self-heating. The real parasitic capacitance time constant and carrier transit time of the investigated device and measurement setup are the causes of this discrepancy. Linear extrapolation of I_DS rising edge for t < t₀ resulting in a linear dissipated power P increase, provides an opportunity to estimate I_DS0 from $d{I}_T/k_T=d{T}_A~P$ utilizing the dI_T sum as the quadratic time dependence. This approximation is found to be sufficient, although further V_DS and I_DS time dependence investigations for t < t₀ are recommended. The trapping time constants of at least one order higher than ~10⁻⁷ s allow the calculation of the isothermal time dependence utilizing (14).

The intersection of the measured I_DS time dependence and I_E at defined T₀ allows T_A determination as depicted in Figure 7 and Figure 8. The difference between the T_A obtained by the quasi-static and the pulsed measurements at t₁~ 1 s can be explained by the partially compensated I_DS during the rising time for the voltage pulse ΔV_DS ≈ 20 V and the uncompensated I_DS during the rising time at the voltage step ΔV_DS ≈ 2 V, which were utilized in the quasi-static measurements. The difference of ~20 °C (13%) between simulated and experimental T_A values is assigned to the different heat-flux distributions, resulting in the deviation between (5) and (6), as well as in the electric parameters from the source to the gate area, influencing dI_T and I_E approximation.

4. Conclusions

The average temperature significance was underlined in the theoretical section to avoid spatially distributed device parameters acquisition. The particular methods, based on an ambient temperature variation for a device under a quasi-static state and a device under pulse operation, were compared by taking the trapping process into account as a result of the FET threshold voltage shift that neglects electric capacitance. In the experimental section, the theoretical subtractions were adapted for the AlGaN/GaN HEMT channel temperature determination. The calculations were a result of the isothermal and thermal current sections separation, by taking into account the threshold voltage shift caused by trapped and free carrier concentration, the band diagram variation in operating temperatures and the applied voltage. The calculated and simulated average channel temperature ~160 °C of the source to the gate area for power dissipation ~2 W exhibits a difference of ~20 °C (13%). The considerations applied in the analytical model offer methodological consolidation for use in further research.