Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms
Round 1
Reviewer 1 Report
Virtual platform is meaningful for MPSoC design. This paper presents a method to synchronize a third-party emulator(QEMU) and the HW simulator with less overhead. It seems the authors' most important contribution only resides in obtaining the SW notions of time from the host vCPUs, which has been discussed in some works[1]. Thus, this work seems not novel to me. Besides, some details should be reconsidered to improve the paper.
1) the model in Equation 1 should not ignore the role of instruction types and the execution time of the RISC instructions is not most in one cycle as described in Line298. The I/D Cache miss rate can be acquired easily by the emulator, which may improve the model precision.
2) more result comparison between setup #2 (or some related works without the proposed scheme)and #3 is required.
3) in Line91 "In [12] and [11]", and in Line143 "[31]", the reference should mark in the order in which they appeared.
[1]. Ozgur Kilic, Spoorti Doddamani, and et al. Overcoming Virtualization Overheads for Large-vCPU Virtual Machines. 2018 IEEE 26th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS).
Author Response
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Author Response File: 
Author Response.pdf
Reviewer 2 Report
The paper suggests the mechanism for external synchronization of QEMU in a parallel, which adds no computational load and enables Parallelized-QEMU in HW/SW co-simulation Virtual Platform.
The problem is thoroughly analyzed and clearly stated. The results seem convincing and promising. On the downside, the paper is quite difficult to follow. To make this submission attractive for a wider audience, I would suggest:
- Decrease the number of acronyms. Besides, they need to be used only after the introduction. For example, the interpretation of HW/SW is first given in the Introduction, while the acronyms are used in the Abstract and so on.
- The main contribution should be clearly stated, step-by-step, in a short and conclusive form. Maybe, it would make sense, first, to present the contribution, then, to reasoning about the solution.
Author Response
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Author Response File: Author Response.pdf
Reviewer 3 Report
This paper studies how to speed up the co-simulation to verify how the multi-core CPUs work. They used QEMU simulator in the context of co-simulation of HW and SW. Previously, QEMU was studied only in the context of SW. The results seem nice and this reviewer believes they that are of interest to Electronics journal community. Therefore, this paper can be accepted with a minor revision on english. There are may long sentences providing potentially disconnected information. It would be nice to break those sentences and provide a coherent exposure on the discussion.
Author Response
Please see the attachment.
Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
This article has been greatly improved.
Although there are slight differences in individual views, the authors have explained their points in detail. Thus all my concerns have been addressed.
I recommend accepting in present form.
