Area Optimization Techniques for High-Density Spin-Orbit Torque MRAMs

Abstract

This paper presents area optimization techniques for high-density spin-orbit torque magnetic random-access memories (SOT-MRAMs). Although SOT-MRAM has many desirable features of nonvolatility, high reliability and low write energy, it poses challenges to high-density memory implementation because of the use of two access transistors per cell. We first analyze the layout of the conventional SOT-MRAM bit-cell that includes two vertical metal lines, a bit-line and a source-line, limiting the horizontal dimension. We further propose two design techniques to reduce the horizontal dimension by decreasing the number of metal lines per cell without any performance overhead. Based on the fact that adjacent columns in a bit-interleaved array are not simultaneously accessed, the proposed techniques share a single source-line between two consecutive bit-cells in the same row. The simulation result shows that proposed techniques can achieve a bit-cell area reduction of 10–25% compared to the conventional SOT-MRAM. The comparison of our proposed designs with the standard spin-transfer torque MRAM shows 45% lower write energy, 84% lower read energy, and 2.3 × higher read-disturb margin.

1. Introduction

Spin-transfer torque magnetic random-access memory (STT-MRAM) has attracted significant attention for future CPU caches and embedded memories due to its promising attributes of nonvolatility, high integration density and compatibility with CMOS processes [1,2,3]. The storage element of STT-MRAM is a magnetic tunnel junction (MTJ) comprising two ferromagnetic layers separated by an oxide layer, e.g., MgO, as shown in Figure 1a. The magnetization of one ferromagnetic layer, the pinned layer (PL), is fixed, whereas that of the other ferromagnetic layer, the free layer (FL), is changeable by passing an electrical current. The FL magnetization is bistable, either parallel (P state) or anti-parallel (AP state) with respect to the PL magnetization. As the P state has a lower resistance than the resistance in the AP state, a read operation can be performed by passing a small read current via the MTJ and then sensing the voltage difference to determine a binary state. Since MTJ is nonvolatile, STT-MRAM can lower the total power dissipation by eliminating leakage power. Additionally, STT-MRAM using a single access transistor is capable of >2 × higher integration density in comparison with conventional static RAMs (SRAMs) [4,5,6].

Despite its desirable attributes, STT-MRAM poses two reliability concerns. First, the read current path is identical to the write current path, as in Figure 1b, leading to a tradeoff between the read stability and write ability [7,8]. For example, the larger the access transistor width for a reliable write operation, the more likely an inadvertent bit flip is to occur during a read operation, as shown in Figure 1c. Second, for a high-speed write operation, the large electrical current needs to be applied, exerting a high stress condition on the tunnel junction [9,10]. Recently, spin-orbit torque MRAM (SOT-MRAM) was proposed as another on-chip memory solution with the enhanced reliability [11,12]. As a three-terminal structure of SOT-MRAM decouples a read path from a write path, the read stability and the write-ability can be independently optimized. Moreover, a write mechanism of SOT-MRAM does not require a high stress condition on the tunnel junction by using spin injection from a heavy metal [10,13]. Additionally, for low-power high-speed write operations, SOT-MRAM is a more promising option than STT-MRAM due to its high spin current injection efficiency [11,12,13].

However, the main drawback of SOT-MRAM is that each memory cell requires two access transistors, resulting in a lower integration density compared to STT-MRAM. This motivates a need for improving the cell area of SOT-MRAM, especially for high-density memory applications. In this paper, we first identify that the SOT-MRAM cell layout includes two vertical metal lines, the bit-line (BL) and source-line (SL), which typically limit the horizontal dimension. We further propose two design techniques, namely, flipped SOT-MRAM (F-SOT-MRAM) and rotated SOT-MRAM (R-SOT-MRAM), both of which reduce the horizontal dimension by decreasing the number of metal lines per cell. Based on the fact that adjacent columns in a bit-interleaved array are not simultaneously accessed due to column selection [14,15,16], the proposed techniques share a single SL between two consecutive cells in the same row without any performance overhead. Our simulation result shows that the proposed designs can improve the memory cell area by 10–25% in comparison to the conventional SOT-MRAM at the same specification of 10 ns switching time, 15% write margin, and >40% read-disturb margin.

The rest of this paper is organized as follows. Section 2 reviews the basic principles of SOT-MRAM, and Section 3 presents the proposed techniques for improving cell area. Section 4 discusses the simulation results, and Section 5 concludes the paper.

2. SOT-MRAM Fundamentals

A three-terminal SOT device is composed of MTJ and heavy metal (HM), as shown in Figure 2a. For a write operation, a charge current is passed through HM in direct contact with FL. In the bottom figure in Figure 2a, FL magnetization is initially aligned along +y direction. If a charge current is applied in −x direction, the spin-orbit coupling in HM deflects −y and +y directed spins to the top and bottom surfaces of HM, respectively. Note that the accumulated spins on the top surface exert STT, causing FL magnetization to be switched to the −y direction. The spin current injection efficiency, defined as the ratio of the injected spin current (I_S) and the charge current (I_C), can exceed 100%, since a single electron passing through the HM transfers multiple units of angular momentum [12,17,18]. More importantly, this switching mechanism of the SOT device enhances the reliability of MTJ, because its oxide layer is not stressed by high voltage drop [13]. For a read operation, BL is connected to a current source, SL is set to G_ND, and the word-line of the read access transistor is asserted high.

This biasing condition passes a small current from a terminal T₁ to the terminal T₃ of the SOT device, enabling the comparison of the cell voltage (V_READ) with respect to the reference voltage (V_REF) using a sense amplifier.Note from Figure 2b that the read and write paths are decoupled; hence, each memory operation can be independently optimized without disturbing the other.

The SOT-MRAM cell, however, requires two access transistors, RFET for a read operation and WFET for a write operation, resulting in a larger bit-cell area compared to STT-MRAM. Consider memory cell layouts in Figure 3, where λ is half the minimum feature size. The minimum metal spacing and the minimum metal width are assumed to be 3λ [19,20] in this paper. Other design parameters are shown in Figure 3a. In general, word-lines, RWL (for a read) and WWL (for a write), run horizontally across the memory array, whereas BL and SL run orthogonally to word-lines. W_RFET (W_WFET) is the width of RFET (WFET). If both RFET and WFET are smaller than 9λ as in Figure 3b, i.e., if max(W_RFET, W_WFET) < 9λ, the horizontal dimension is limited by the metal pitch as follows.

$$2W_{M2M}+2W_M=12\lambda$$

(1)

Otherwise, as shown in Figure 3c, the horizontal dimension is determined by the larger W_RFET and W_WFET as follows.

$$max\left(W_{RFET},W_{WFET}\right)+W_{A2A}=max\left(W_{RFET},W_{WFET}\right)+3\mathsf{\lambda }$$

(2)

The vertical dimension of SOT-MRAM is

$$W_C+4W_{G2C}+2W_G+2W_C+2W_{C2A}+W_{A2A}=23\mathsf{\lambda }$$

(3)

which is due to the two-transistor requirement, twice the vertical dimension of standard STT-MRAM, shown in Figure 3d.

3. Proposed SOT-MRAM Designs

3.1. Basic Idea

In a conventional memory array containing multiple words per row, the bit-interleaving is a commonly used technique [14,15,16] (1) to reduce the risk of multi-bit errors by a radiation event and (2) to achieve a higher array density via BL multiplexing. As technology shrinks, the single radiation event due to alpha particle or neutron strikes can cause a multi-bit upset (MBU) [21]. In such case, the bit-interleaving can avoid a multi-bit error by spreading MBU over multiple different words so that each word involves at most one bit of error that can be corrected by a simple error correction code [15]. In the case of SOT-MRAM, although the magnetic storage element is immune to radiation-induced soft error, the use of bit-interleaving is still preferred, since its access transistors can suffer from MBUs [22]. In addition, the bit-interleaving is an effective means to share peripheral circuitries, thereby reducing the area of memory array [16]. Figure 4 shows an illustrative example of distance-2 bit-interleaving architecture, where two adjacent BLs, BL[k] and BL[k + 1], with k being an odd number, are multiplexed to share the sense amplifier and the write driver.

In the aforementioned bit-interleaving architecture, we observe that two adjacent bit-cells are not simultaneously accessed. This provides an opportunity for bit-cell area improvement by sharing a vertical metal line between two consecutive cells. In this work, we employed a single SL for two cells and applied the appropriate biasing conditions so that the shared SL could be used for the cell selected for access without disturbing the other cell. The following subsection describes the details of the proposed bit-cell structure, which can be applied to an array with any distance-n bit-interleaving, where n is the even number.

3.2. Proposed Bit-Cell Structures

We first discuss memory cell arrangements suitable for the sharing of a single SL between two adjacent cells in the same row. Consider the pair of cells in Figure 5a, where four vertical metal tracks lie in the order of BL[k], SL[k], BL[k + 1], and SL[k + 1]. In this conventional arrangement, combining two SLs into a single one can be complicated because BL[k + 1] is sandwiched between SL[k] and SL[k + 1]. To facilitate the combining of SLs, we propose to flip or rotate a cell in the even column such that SL[k + 1] precedes BL[k + 1]. The first proposed structure, termed the flipped SOT-MRAM (F-SOT-MRAM), flips an even-column cell in the horizontal direction and combines two SLs into a single one, as shown in Figure 5b. The F-SOT-MRAM can obviously improve the bit-cell area because the number of metal lines required for a pair of cells decreases from four to three. Specifically, if both RFET and WFET are sized smaller than 6λ, i.e., if max(W_RFET, W_WFET) < 6λ, its horizontal dimension is

$$1.5W_{M2M}+1.5W_M=9\mathsf{\lambda }$$

(4)

If W_RFET is >6λ or W_WFET is >6λ, the horizontal dimension is

$$max(W_{RFET,}{W}_{WFET})+W_{A2A}=max(W_{RFET,}{W}_{WFET})+3\mathsf{\lambda }$$

(5)

Shown in Figure 6a are bit-cell areas with respect to a range of max(W_RFET, W_WFET) for the conventional SOT-MRAM and F-SOT-MRAM. Note that the bit-cell area can be metal pitch limited (MPL) or transistor width limited (TWL) [19]. In the MPL region, F-SOT-MRAM can improve the bit-cell area by 25% compared to the conventional SOT-MRAM. If max(W_RFET, W_WFET) is >6λ, the bit-cell area saving diminishes as F-SOT-MRAM is in the TWL region.

The second proposed structure, namely, the rotated SOT-MRAM (R-SOT-MRAM), rotates an even-column cell by 180 degrees and combines SLs, as shown in Figure 5c. Note that the RFET of the odd-column cell and WFET of the even-column cell are connected to the same word-line, termed WL_A. Similarly, the WFET of the odd-column cell and RFET of the even-column cell are connected to WL_B. Under such configuration, the horizontal dimension of R-SOT-MRAM in the TWL region is determined by the mean of W_RFET and W_WFET, i.e.,

$$0.5\left(W_{RFET}+W_{WFET}\right)+W_{A2A}=0.5\left(W_{RFET}+W_{WFET}\right)+3\mathsf{\lambda }$$

(6)

This is unlike F-SOT-MRAM, in which the horizontal dimension is independent of the smaller transistor width. Hence, R-SOT-MRAM can optimize the bit-cell area further if two access transistors are different in size. Figure 6b shows the bit-cell area of R-SOT-MRAM in comparison to F-SOT-MRAM when the absolute difference between W_WFET and W_RFET is λ, 2λ, and 3λ.

The biasing conditions of the proposed SOT-MRAMs are shown in Figure 7. Since a single SL is shared between two adjacent cells, a pair of cells needs an appropriate biasing so that access to one cell for memory operation does not disturb the other cell connected to the same SL. For example, to write a value of 0 into an odd-column cell in Figure 7a, BL[k] is set to G_ND, SL is set to V_WRITE, and WWL is asserted such that the current flows from SL to BL[k]. In this case, F-SOT-MRAM applies V_WRITE to BL[k + 1] to prevent the even-column cell from being unintentionally overwritten. In addition, R-SOT-MRAM needs to consider that the 180° rotation of the even-column cell alters the position of word-lines. Note from Figure 7b that WL_A is used for a read operation of the odd-column cell or for a write operation of the even-column cell. Similarly, WL_B is used for a write operation of the odd-column cell or for a read operation of the even-column cell.

4. Results

4.1. Simulation Framework

To evaluate our proposed memory bit-cells in comparison to conventional STT-MRAM and SOT-MRAM, we utilized a simulation framework [23] that consists of three components:

(1)

Landau–Lifshitz–Gilbert (LLG) equation solver to model the magnetization dynamics of the spintronic device [24,25,26];

(2)

Non-Equilibrium Green’s Function (NEGF) formalism to obtain the voltage-dependent resistance of MTJ [27];

(3)

SPICE simulator to model the memory bit-cell circuit.

The LLG equation solver determines the critical current for the 10 ns switching time based on the parameters in

Table 1. Parameters of storage devices.

Device Parameters	STT Device	SOT Device
Gilbert damping, α	0.007	0.0122
Saturation magnetization, MS	1100 × 103 A/m	1100 × 103 A/m
Dimension of FL (WFL × LFL × tFL)	120 nm × 40 nm × 2.5 nm 1	120 nm × 40 nm × 2.5 nm 2
Dimension of HM (WHM × LHM × tHM)	-	120 nm × 80 nm × 2.7 nm
HM resistivity	-	200 µΩ·cm
Spin Hall angle, θSH	-	0.3
Spin flip length, λsf	-	1.40 nm
MgO thickness, tMgO	1.05 nm	1.30 nm
Critical current for 10 ns switching time	206 µA	121 µA

^1,2 MTJ free layer has an elliptical shape.

. In the case of the SOT device, the spin current injection efficiency, the ratio of I_S to I_C, can be calculated as [18,28]:

$$\frac{I_S}{I_C}=\frac{A_{MTJ}}{A_{HM}}·{\theta }_{SH}\left(1-\mathrm{sech}\left(\frac{t_{HM}}{{\lambda }_{sf}}\right)\right)$$

(7)

where A_MTJ is the cross-sectional area of the MTJ (xy-plane), A_HM the cross-sectional area of the HM (yz-plane), t_HM the thickness of HM, λ_sf a spin flip length, and θ_SH a spin Hall angle that is assumed to be 0.3 in our work [11]. Since A_HM (=W_HM × t_HM) is designed to be smaller than A_MTJ (=π/4 × W_FL × L_FL), the resultant spin current injection efficiency, 272.39%, is higher than 100%.

The resistance of HM was estimated from the experimental resistivity in [11], whereas the voltage-dependent resistance of MTJ was obtained by using the NEGF formalism [10]. The resistance function of spintronic devices was coupled with a commercial 45 nm transistor model to form the complete memory cell structure. Transient SPICE circuit simulations were performed to evaluate the energy of bit-cells at the target switching time.

4.2. Simulation Results

We evaluated four different memory bit-cells with each being designed at the same condition of 10 ns switching time; 2 ns sensing time; 15% write margin; defined as (I_W-I_C)/I_C; and >40% read-disturb margin, defined as (I_C-I_R)/I_C, in an array comprising 256 rows and 512 columns [29,30,31]. See

Table 2. Comparison of different bit-cells.

	STT-MRAM	Conventional SOT-MRAM	F-SOT-MRAM	R-SOT-MRAM
Transistor width (nm)	430	155 (WWFET) 85 (WRFET)	155 (WWFET) 85 (WRFET)	155 (WWFET) 85 (WRFET)
Bit-cell area (µm2)	0.0880	0.1104	0.0989	0.0828
Write energy per bit (fJ)	2737.3	1504.0	1508.4	1508.4
Read energy per bit (fJ)	267.4	42.3	42.3	42.3
Read-disturb margin (%)	41	93	93	93

for simulation results. In the case of STT-MRAM in which the read and write current paths are identical, its access transistor needs to be sized to ensure both read and write operations. In our analysis, the transistor was sized at 430 nm, which was determined by a write operation rather than by a read operation. In the case of SOT-MRAM, the write operation at the same condition can be achieved by using the smaller transistor at 155 nm width thanks to the high spin current injection efficiency.

Nevertheless, since the conventional SOT-MRAM requires an additional transistor for a read, its bit-cell area (0.1104 µm²) is still 25% larger than that of STT-MRAM (0.0880 µm²).

In order to improve the bit-cell area, the proposed F-SOT-MRAM and R-SOT-MRAM share an SL between two adjacent bit-cells in the same row. As a result, the F-SOT-MRAM achieves a 10% reduction in bit-cell area compared to the conventional SOT-MRAM. As mentioned earlier, the R-SOT-MRAM has the potential to achieve a higher area saving if W_RFET is different from W_WFET. In our analysis, the R-SOT-MRAM took advantage of this potential and achieved a 25% reduction, resulting in the smallest bit-cell area among four different memory cells in Table 2.

Note that the proposed designs maintain the inherent advantages of SOT-MRAM. Due to the spin current injection efficiency of 272.39%, F-SOT-MRAM and R-SOT-MRAM achieve 45% lower write energy compared to STT-MRAM. Additionally, unlike STT-MRAM, in which the oxide thickness (t_MgO) is determined by the tradeoff between read stability and write-ability, two proposed designs can optimize t_MgO for a read operation only. In our work, t_MgO for F-SOT-MRAM and R-SOT-MRAM was 1.30 nm, as opposed to 1.05 nm for STT-MRAM, as in Table 1. The thicker t_MgO translates into the higher MTJ resistance, in turn, the smaller current required to develop the identical BL voltage during a read operation. Table 2 shows that F-SOT-MRAM and R-SOT-MRAM achieved 84% lower read energy and 2.3 × higher read-disturb margin in comparison to STT-MRAM.

5. Conclusions

We discussed area optimization techniques for high-density SOT-MRAMs. Based on the fact that adjacent columns in a bit-interleaved array are not simultaneously accessed, we proposed two design techniques to share a single source-line between two consecutive bit-cells in the same row. The proposed techniques reduce the horizontal dimension by decreasing the number of metal lines per cell while retaining the advantages of SOT-MRAM, such as high reliability and low write energy. The simulation result shows that the proposed techniques achieved a bit-cell area reduction of 10–25% without any performance overhead. Compared to STT-MRAM, our proposed designs achieved 45% lower write energy, 84% lower read energy, and 2.3 × higher read-disturb margin.