Parallel Computation of CRC-Code on an FPGA Platform for High Data Throughput
Abstract
:1. Introduction
2. CRC Background
3. CRC Computational Process
3.1. Serial CRC Generation Process
Algorithm 1. Bitwise CRC. |
1: Input: Byte Array Data |
2: Crc = 0XFFFFFFFF |
3: While index < size of data do |
4: CRC = CRC XOR data[index] |
5: for j = 0; j < 8; j++ do |
6: CRC = (CRC >> 1) XOR -(CRC AND 1) AND G(x) |
7: end for |
8: index + 1 |
9: end while |
10: Return CRC XOR 0XFFFFFFFF |
3.2. The Sarwate’s Algorithm and Slicing by an N Algorithm
Algorithm 2. Sarwate Algorithm. |
1: Input: Byte Array Data |
2: Crc = 0XFFFFFFFF |
3: While index < size of data do |
4: CRC = (CRC >> 8) XOR TABLE[(CRC AND 0xFF) XOR data[index]] |
5: index + 1 |
6: end while |
7: Return CRC XOR 0XFFFFFFFF |
Algorithm 3. Slicing by 4 Algorithm. |
1: Input: Byte Array Data |
2: Crc = 0XFFFFFFFF |
3: While index < size of data do |
4: CRC = CRC XOR data[index:index+3] |
5: XOR TABLE1[(CRC AND 0xFF)] |
6: XOR TABLE2[((CRC >> 8) AND 0xFF)] |
7: XOR TABLE3[((CRC >> 16) AND 0xFF)] |
8: XOR TABLE4[((CRC >> 24) AND 0xFF)] |
9: index + 4 |
10: end while |
11: Return CRC XOR 0XFFFFFFFF |
3.3. Matrix Transformation
3.4. Hybrid Method
4. FPGA Implementation
5. Experimental Results
6. Conclusions and Future Work
Author Contributions
Funding
Conflicts of Interest
References
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Name | Number of Bits | Number of Channels | Total | Comment |
---|---|---|---|---|
Thermopile Data + Time Stamp Thermistor data on thermopile Hot Target Temperature | 32 | 8 | 256 | Science Data |
16 | 8 | 128 | Science Data | |
12 | 1 | 12 | Thermal data | |
Fan-out board Temperature Vessel Temperature | 12 | 1 | 12 | Thermal data |
12 | 1 | 12 | Thermal data | |
Windows Temperature Cold Target Temperature LED status Motor Position | 12 | 1 | 12 | Thermal data |
12 | 1 | 12 | Thermal data | |
1 | 1 | 1 | Auxiliary data, 1 bit for ON/OFF | |
3 | 1 | 3 | Auxiliary data, 3 bits for 7 positions | |
Survival Heater Status Thermopile Data + Time Stamp | 1 | 1 | 1 | Auxiliary data, 1 bit for ON/OFF |
32 | 8 | 256 | Science Data |
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Tran, D.; Aslam, S.; Gorius, N.; Nehmetallah, G. Parallel Computation of CRC-Code on an FPGA Platform for High Data Throughput. Electronics 2021, 10, 866. https://doi.org/10.3390/electronics10070866
Tran D, Aslam S, Gorius N, Nehmetallah G. Parallel Computation of CRC-Code on an FPGA Platform for High Data Throughput. Electronics. 2021; 10(7):866. https://doi.org/10.3390/electronics10070866
Chicago/Turabian StyleTran, Dat, Shahid Aslam, Nicolas Gorius, and George Nehmetallah. 2021. "Parallel Computation of CRC-Code on an FPGA Platform for High Data Throughput" Electronics 10, no. 7: 866. https://doi.org/10.3390/electronics10070866