Applying FPGA Control with ADC-Free Sampling to Multi-Output Forward Converter

Abstract

In this paper, a forward converter with multiple outputs is employed to build up a circuit system with full-digital control without any analog-to-digital (ADC) converter adopted. In this circuit, all the output voltages can be regulated by individual feedback control loops. As transient load variations due to the main output happens, the secondary outputs are affected quite slightly. Furthermore, the output voltage with the largest output current adopts not only the voltage mode control but also the interleaved control and current sharing control. Therefore, if this circuit system adopts full-digital control, the number of ADCs employed is relatively large, and the corresponding cost is expensive. Accordingly, the sampling of multiple output voltages and two-phase currents without any ADCs is used herein. Moreover, a nonlinear control strategy is proposed and applied to the traditional proportional-integral-derivative (PID) controller to accelerate the load transient response. In addition, the field programmable gate array (FPGA) is used as a control kernel.

1. Introduction

The more the functions in an electronic product, the more the voltage types required [1,2]. For example, in digital circuits that require different operating voltages according to different chips, multiple output positive voltage DC–DC converters are required [3,4]. In IGBT or SiC, drive circuits usually require multiple sets of multi-channel isolated power supplies with positive and negative outputs [5]. Accordingly, a DC–DC converter with good performance of multiple outputs is indispensable. Concerning the control of such a converter, it usually focuses on regulating the minimum output voltage with the maximum output current [6]. In the literature [7], the parasitic and leakage inductances lead to degrading the performance of the forward converter. In the literatures [8,9], cross regulation is discussed. As one or more output voltages are under load variations, the steady-state and dynamic cross regulations that exist between output voltages will occur.

The literatures [3,10] discuss the control of multi-output converters, but they both only take single output feedback control. From these studies, it can be found that regulation improvements based on such a method is limited. Therefore, if each output voltage is desired to be high-accuracy output voltage, then, in general, the coupled inductor and magnetic amplifier can be applied to achieve highly stabilized output voltages. If the uncontrolled output terminal adopts the coupled inductor [10,11], then the turns ratio of the coupled inductor should be equal to the turns ratio of the transformer. If not, there will be a large circulating current between the two output voltage terminals. In addition, if the output diodes have a slight difference in forward voltage between them, then the corresponding design will be complicated and unpredictable. If the uncontrolled output voltage terminal adopts the magnetic amplifier, then the circuit system control will be difficult due to the nonlinear behavior of the magnetic amplifier [12,13].

The literatures [14,15] adopt the secondary side post regulators (SSPRs) to regulate individual output voltages. In this paper, the forward converter with multiple outputs taking the SSPR technique along with synchronous rectification (SR) will be presented. There are three circuits in the proposed converter: one is an SR forward converter; another is an SR buck converter; the other is a two-phase Interleaved SR buck converter. Furthermore, the output voltage terminal with the maximum output current will adopt the interleaved control technique. In addition, the comparator sampling technique [16] will be applied to this converter to realize full digital control, and the voltage mode control is used herein to stabilize each output voltage at the desired value. Accordingly, the main novelty elements and advantages are as follows: (1) fast load transient response; (2) good current sharing; (3) good load regulation; (4) good line regulation; and (5) excellent cross regulation. In the following, Section 2 presents the system configuration; Section 3 explains the SSPR technique; Section 4 explains the two-phase interleaved control strategy; Section 5 introduces the ADC-free sampling technique; Section 6 introduces the nonlinear control strategy; Section 7 presents the experimental results; Section 8 makes comparisons; and Section 9 makes conclusions.

2. System Configuration

Figure 1, Figure 2 and Figure 3 show the proposed circuit system configuration. The main power stage is built up by an SR forward converter, as shown in Figure 1. At the same time, the SR buck converter, shown in Figure 2, is connected between point A and the ground, as shown in Figure 1, whereas an SR two-phase interleaved buck converter, shown in Figure 3, is connected between point A and the ground, as shown in Figure 1. The output voltage of the main output is signified by v_o1, the output voltage of the first secondary output is indicated by v_o2, and the output voltage of the second secondary output is denoted by v_o3. Each output voltage is controlled at a desired value based on sampling without ADC. As for the current sharing between two phases, it is achieved also based on sampling without ADC.

The main output is constructed by an SR forward converter with an LC snubber built up by two diodes D_s1 and D_s2, one inductor L_s, and one capacitor C_s. As for this converter, it is established by one transformer with two windings N₁ and N₂ and magnetizing inductance, one main switch S₁ with one body diode D_p1, two SR switches S₂ and S₃ with individual body diodes D_p2 and D_p3, one output inductor L_o1, one output capacitor C_o1, and one output resistor R₁. Regarding the corresponding symbols for currents and voltages, V_i is the input voltage, i_Ds1 is the current flowing through D_s1, i_Ls is the current flowing through L_s or D_s2, i_Cs is the current flowing through C_s, i_S1 is the current flowing through S₁, i_S2 is the current flowing through S₂, i_S3 is the current flowing through S₃, i_Lo1 is the current flowing through L_o1, v_Lo1 is the voltage across L_o1, v_Cs is the voltage across C_s, and v_o1 is the voltage across R₁.

The first secondary output is constructed by the SR buck converter. As for this converter, it is established by one main switch S₄ with one body diode D_p4, one SR switch S₅ with one body diode D_p5, one output inductor L_o2, one output capacitor C_o2, and one output resistor R₂. Regarding the corresponding symbols for currents and voltages, i_S4 is the current flowing through S₄, i_S5 is the current flowing through S₅, i_Lo2 is the current flowing through L_o2, v_Lo2 is the voltage across L_o2, and v_o2 is the voltage across R₂.

The second secondary output is constructed by the two-phase interleaved SR buck converter. As for this converter, it is established by two main switches S₆ and S₈ with individual body diodes D_p6 and D_p8, two SR switches S₇ and S₉ with individual body diodes D_p7 and D_p9, two output inductors L_o3 and L_o4, one output capacitor C_o3, and one output resistor R₃. Regarding the corresponding symbols for currents and voltages, i_S6, i_S7, i_S8 and i_S9 are the currents flowing through S₆, S₇, S₈ and S₉, respectively, i_Lo3 and i_Lo4 are the currents flowing through L_o3 and L_o4, respectively, v_Lo3 and v_Lo4 are the voltages across L_o3 and L_o4, respectively, and v_o3 is the voltage across R₃.

3. SSPR Technique

The SSPR technique can be classified into trailing-edge modulation and leading-edge modulation. Concerning the former, the main switches for the main output and the first secondary output are switched on with the same turn-on moment, as shown in Figure 4, resulting in reducing the peak current flowing through the main switch of the main output. Regarding the latter, the main switches for the main output and the first secondary output are both switched off with the same turn-off moment, as shown in Figure 5, leading to being widely used in peak current mode control. This is because the former has an error in trigger due to having two peak values. However, in this paper, only the voltage control is utilized. Consequently, such a problem never happens, and hence the former is employed to reduce the peak current in the main switch of the main output, as well as to adjust easily the duty cycle for the main switch of the first secondary output.

4. Two-Phase Interleaved Control Strategy

In the three output voltages, the interleaved control strategy is applied to the output voltage with the maximum output current. As for the SSPR technique, it is applied to multiple outputs; all the main switches should be switched on within the turn-on time of the main output. By doing so, the energy can be transferred from the input to the load. If the switching period of the second secondary output is the same as that of the main output, the second phase cannot transfer energy, as shown in Figure 6. Accordingly, the switching period of the second secondary output should be double that of the main output, as shown in Figure 7.

5. ADC-Free Sampling Technique

5.1. Comparator Sampling

The ADC-free sampling technique based on the comparator is used as a method for sampling the output voltages of the proposed multi-output forward converter. There are two counters and one sampling block in the FPGA. One is a fixed period counter PWM_CNT, and the other is a counter CNT cooperated with a sampling block to count. The digital output voltage feedback information, named the value of CNT, is generated by comparing the output feedback voltage v_o-sense and the reference voltage V_ref through a comparator and a counter CNT. The reference voltage V_ref will be set as the average value of the output feedback voltage, and then a signal VFB with a high or low level will be obtained. Afterwards, this digital signal is sent to the FPGA, and cooperated with a sampling block, which is pre-written by using the very high-speed hardware description language (VHDL). The sampling block gets started within the preset range of the PWM_CNT count value as the basis for starting and stopping the counting of CNT; CNT counts within one period and its value is the digital output voltage feedback information. The sampling block action is shown in Figure 8. First, supposing that the equivalent series resistance (ESR) of the output capacitor of the converter is large enough, the output voltage waveform is the DC output voltage plus the approximately linear triangular wave ripple. PWM_CNT starts the sampling block at t₀ and disables the sampling block at t₃. At the beginning of a switching cycle t₀, PWM_CNT starts counting from zero and the sampling block starts. During the time interval between t₀ and t₁, the output feedback voltage is smaller than V_ref. The output signal of the comparator is one (that is, VFB = 1), and CNT does not count. At t₁, the output feedback voltage is greater than the reference voltage, hence the comparator output changes from high level to low level (that is, VFB changes from one to zero), thereby making CNT start counting from zero. When the comparator output changes again (that is, when VFB changes from zero to one) at t₂, CNT stops counting, the sampling block is disabled, and the value of CNT is the digital output voltage feedback information.

Here the sampling clock is the same as the FPGA clock. If the sampling clock is defined as f_sm, then the value of CNT is

$$\mathit{CNT}=f_{sm}(t_2-t_1)$$

(1)

Rewrite (1) as

$$\mathit{CNT}=f_{sm}\left[(t_a-t_1)+(t_2-t_a)\right]$$

(2)

From the geometrical relationship, it can be seen that the instantaneous values of the signal v_o-sense to be sampled at t₁ and t₂ are

$$v_{o-sense}(t_1)=\frac{v_{o-ripple}}{\left(\frac{T_s}{2}\right)}(t_a-t_1)$$

(3)

$$v_{o-sense}(t_2)=\frac{v_{o-ripple}}{\left(\frac{T_s}{2}\right)}(t_2-t_a)$$

(4)

Substituting Equation (3) and Equation (4) into Equation (2) yields

$$\mathit{CNT}=f_{sm}\frac{T_s}{2}\frac{\left[v_{o-sense}\left(t_1\right)+v_{o-sense}\left(t_2\right)\right]}{v_{o-ripple}}$$

(5)

Equation (5) describes a linear mapping transformation from the analog value to the digital value. Therefore, the resolution of the digital feedback value is as follows:

$$\mathrm{Resolution}=\left(t_3-t_0\right)f_{sm}$$

(6)

In the following, based on Figure 9, Figure 10, Figure 11 and Figure 12, three cases and the corresponding control loop will be given. Under a constant switching frequency, since the FPGA clock is 100 MHz and the system switching frequency is 200 KHz, the PWM_CNT counting cycle is set to 500CLK, so when the sampling block is enabled, it can be seen from Equation (1) that there are three cases for the value of CNT. The first case is that the average value of the output feedback voltage v_o-sense is equal to the value of V_ref, so the comparator output will get a signal VFB with the high-level time interval equal to the low-level time interval. At this time, the value of CNT will be equal to 250CLK, so the output voltage error v_o-error obtained by subtracting the value of REG from the reference value of 250 is zero, implying that the duty cycle of PWM remains fixed, as shown in Figure 9. It is noted that REG is the register for the value of CNT. The second case is that the average value of v_o-sense is less than the value of V_ref, and the comparator output will get a digital signal VFB with the high-level time interval larger than the low-level time interval. At this time, the value of CNT will be less than 250CLK. Therefore, the digital reference value 250 minus REG will produce a positive error value, so the PWM duty cycle must be increased to boost up the output voltage, as shown in Figure 10. The third case is that the average value of v_o-sense is greater than the value of V_ref, and the comparator output will get a digital signal VFB with the high-level time interval smaller than the low-level time interval. At this time, the value of CNT will be more than 250CLK. Therefore, the digital reference value of 250 minus REG will produce a negative error value, so the PWM duty cycle must be decreased to reduce the output voltage, as shown in Figure 11.

For the control loop shown in Figure 12, when the sampling block is disabled within the remaining time of PWM_CNT, that is, before the end of a cycle, the value of REG is subtracted from the digital reference value of 250 to obtain output voltage error v_o-error, and this error is sent to the digital proportional-integral-derivative (PID) controller for calculation. Eventually, the controller outputs a control force v_f, and this control force is added to a digital value of 250, leading to generating the corresponding duty cycle; this duty cycle will be limited to the prescribed range and then will be used in the next cycle.

5.2. Triangular Wave Injection Method

The previous discussion of the ADC-free sampling technology is to consider that the output capacitor of the DC–DC converter has an equivalent series resistance (ESR), so its output voltage waveform possesses the DC voltage and triangular ripple. However, since the solid organic semiconductor capacitor (OSCON) or the multilayer ceramic capacitor (MLCC) can be used as the output voltage capacitor, the output voltage ripple will become smaller, and the linearity of the output voltage ripple waveform is degraded, as shown in Figure 13.

Therefore, this section will introduce a triangular wave injection method to improve the problem that the voltage cannot be accurately controlled due to the decrease in the linearity of the output voltage ripple. The solution is to inject a triangular wave into the output feedback voltage to improve the output voltage ripple due to poor linearity, as shown in Figure 14; hence, a modified triangular waveform will be obtained, which is combined with the previously-discussed comparator sampling method to obtain precise output voltage control, as shown in Figure 15.

In the following, the accuracy after injection can be expressed as follows. From Equation (7), it can be seen that there is a relationship between the sampling accuracy and peak-to-peak value of the triangular wave injected output voltage, called ${\tilde{v}}_{op}$. Therefore, ${\tilde{v}}_{op}$ is large. Although the original poor linearity of the output voltage ripple can be modified into a better linearity of the triangular waveform, according to Equation (7), the cost of the injection method is at the expense of sampling accuracy.

$$\mathrm{Accuracy}=\frac{{\tilde{v}}_{op}}{\mathrm{Resolution}}$$

(7)

5.3. Interleaved Current Sampling Method

In this paper, an interleaved ADC-free sampling strategy is proposed. Firstly, it is assumed that the inductor current ripple is small enough and the amplitude of the injected triangular wave is large enough. In Figure 16, the currents ${\tilde{i}}_{s1}$ and ${\tilde{i}}_{s2}$, generated by individual current sensing devices with the same gain K, are added to individual triangular waves and then compared with the same prescribed current reference I_ref to obtain high- or low-level signals (IFB1 and IFB2). Afterwards, these two signals are sent to the FPGA, which has four counters. There are two synchronous counters, PWM_ICNT1 and PWM_ICNT2, with the same period and two counters, ICNT1 and ICNT2, in the sampling block. Accordingly, the value of ICNT1 minus the value of ICNT2 can be obtained, and then this result is sent to the current sharing controller. Therefore, the corresponding control force v_f1 will be obtained. The sampling operation principle in the sampling block is the same as mentioned in Section 5.1, so it will not be redescribed herein. The next duty cycle of PWM1 can be determined by the present values v_f1 and v_f2 based on v_f2 minus v_f1 plus DUTY_CYCLE, and then passed through a prescribed limiter, called Limiter1, whereas the next duty cycle of PWM2 can be determined by the prescribed values v_f1 and v_f2 based on v_f2 plus v_f1 plus DUTY_CYCLE, and then passed through a prescribed limiter, called Limiter2, with a phase shift of 180 degrees from PWM1. In Figure 17, PWM_ICNT1 counts between t₀ and t₂, whereas PWM_ICNT2 counts between t₁ and t₃; ICNT1 counts between t_a and t₁, whereas ICNT2 counts between t_b and t₂. Additionally, PWM_ICNT2 will start to count when PWM_ICNT1 counts to half of the cycle. ICNT1 and ICNT2 will get different or identical count values, which can be regarded as feedback information of the two-phase currents at the same point.

6. Nonlinear Control Strategy

The nonlinear control strategy is explained in detail as follows. For the upload mode to be considered, as shown in Figure 18, when the value of REG is equal to the value of MIN_CNT, the program chooses to disable the PID controller and fix the duty cycle at a certain value higher than the steady-state duty cycle. However, in order to prevent the transformer of the forward converter from being saturated, the time required for resetting the magnetic flux of the transformer must be considered. Here, the duty cycle d_m for the main output is set to 0.62 to make the output feedback voltage ripple rapidly climb to approach the reference voltage. For the normal mode to be considered, when the value of REG is between the value of MIN_CNT and the value of MAX_CNT, that is, when the reference voltage is within the output feedback voltage ripple, the open loop control is disabled and the PID controller is restored to reduce the steady-state error. For the download mode to be considered, when the value of REG is equal to the value of MAX_CNT, it means that the output voltage is too high. The program chooses to disable the PID controller and reduce the duty cycle to a value lower than the steady-state duty cycle. As discussed in Section 5, the duty cycle d_m for the main output must be larger than the duty cycles for the other two secondary outputs. If not, two secondary outputs will not be supplied with electricity. So, the value of d_m will be set to be greater than the maximum value of the steady-state duty cycle of the two secondary outputs, such as d_a.

7. Experimental Results

Prior to this section,

Table 1. Main output specifications.

System Parameters	Specifications
Operating Mode	CCM
Input Voltage (Vi)	$36 \mathrm{V}\pm 10\%$
Output Voltage (Vo1)	12 V
Rated Output Current (Io1)	10 A
Rated Output Power (Po1)	120 W
Turns Ratio (n = N2/N1)	5/6
Inductor Current Slew Rate (SRLo1)	2 A/μs
Switching Frequency (fs1)	200 kHz
Output Voltage Ripple (Δvo1,max)	=<100 mV

,

Table 2. First secondary output specifications.

System Parameters	Specifications
Operating Mode	CCM
Input Voltage (Vi)	$36 \mathrm{V}\pm 10\%$
Output Voltage (Vo2)	5 V
Rated Output Current (Io2)	8 A
Rated Output Power (Po2)	120 W
Inductor Current Slew Rate (SRLo2)	2 A/μs
Switching Frequency (fs2)	200 kHz
Output Voltage Ripple (Δvo2,max)	=<100 mV

and

Table 3. Second secondary output specifications.

System Parameters	Specifications
Operating Mode	CCM
Input Voltage (Vi)	$36 \mathrm{V}\pm 10\%$
Output Voltage (Vo3)	3.3 V
Rated Output Current (Io3)	12 A
Rated Output Power (Po3)	40 W
Inductor Current Slew Rate (SRLo3)	2 A/μs
Switching Frequency (fs3)	200 kHz
Output Voltage Ripple (Δvo3,max)	=<100 m

display the specifications for the main output, the first secondary output, and the second secondary output.

7.1. Current Sharing Waveforms

The waveforms shown in Figure 19 are two-phase inductor currents of the second secondary output at the rated load and in the steady state. The inductor current waveforms shown in Figure 20 and Figure 21 are load transient responses from the rated/light load to light/rated load for the second secondary output. Therefore, it can be found that from this figure, the proposed two-phase interleaved current sampling method, together with the current sharing control, can make the output current evenly distributed among two phases. As the load changes, the two inductor currents will follow each other. It is noted that variations in each inductor current due to a step load change from the light/rated load to rated/light load belong to a large-signal response. Accordingly, each current-sharing controller with only the proportional gain k_p used to make the corresponding inductor current during the download transient period only has one undershoot. Therefore, the value of k_p is tuned to be 0.4. Afterwards, this value of k_p is applied to the upload transient response, causing each inductor current to have an overshoot and ring.

7.2. Dynamic Cross Regulation Performance

Figure 22 and Figure 23 show that the main output is varied from a light/rated load to rated/light load, respectively, on the condition that the first and second secondary outputs are at a light load, whereas Figure 24 and Figure 25 show that the main output is varied from a light/rated load to rated/light load, respectively, on the condition that the first and second secondary outputs are at a rated load. The results of the dynamic cross regulation are tabulated in

Table 4. Results for dynamic cross regulation.

Item	Figure	22	23	24	15
1	Peak Overshoot or Undershoot	vo1: 156.52 mV vo2: 17.39 mV vo3: 52.17 mV	vo1: 104.35 mV vo2: 17.39 mV vo3: 26.09 mV	vo1: 130.43 mV vo2: 52.19 mV vo3: 34.78 mV	vo1: 104.35 mV vo2: 34.78 mV vo3: 52.17 mV
2	Percentage of Output Voltage for Item 1	1.31% of Vo1 0.35% of Vo2 1.58% of Vo3	0.87% of Vo1 0.35% of Vo2 0.79% of Vo3	1.09% of Vo1 1.04% of Vo2 1.06% of Vo3	0.87% of Vo1 0.70% of Vo2 1.58% of Vo3
3	Setting Time	vo1: 40 µs vo2: 60 µs vo3: 80 µs	vo1: 40 µs vo2: 60 µs vo3: 80 µs	vo1: 40 µs vo2: 40 µs vo3: 80 µs	vo1: 40 µs vo2: 40 µs vo3: 80 µs

, including the peak overshoot voltage, peak undershoot voltage, peak overshoot voltage percentage, peak undershoot voltage percentage, and setting time. From Table 4, it can be seen that each response has its peak overshoot and undershoot voltage percentages within 1.6%, which are smaller than 5% from industrial applications.

7.3. Overall Efficiency and Prototype Photo

Figure 26 shows the overall efficiency, where each point of the efficiency cure is plotted at the same load current percentage for three outputs. From this figure, it can be seen that the efficiency can be up to 91% and the efficiency at the rated load is 86%. In addition, Figure 27 displays the photo of the experimental setup.

7.4. Current Sharing Error Percentage

Figure 28 shows the current sharing error percentage, which is obtained based on the following equation:

$$\mathrm{Current}\mathrm{Sharing}\mathrm{Error}\%=\left|\frac{I_{o3}-I_{o4}}{I_{o3}+I_{o4}}\right|\times 100\%$$

(8)

Therefore, the corresponding maximum value of the current sharing error percentage, displayed in Figure 28, is 3.8%, which is smaller than the 5% from industrial applications.

7.5. Load Regulation

Figure 29 shows the load regulation of the main output on the condition that the first and second secondary outputs are at the rated load. Figure 30 shows the load regulation of the first secondary output on the condition that the main and second secondary outputs are at the rated load. Figure 31 shows the load regulation of the second secondary output on the condition that the main and first secondary outputs are at the rated load. After that, the load regulation percentage equation is defined as:

$$\mathrm{Load}\mathrm{Regulation}\%=\left|\frac{V_o(\mathrm{Rated}\mathrm{Load})-V_o(\mathrm{Light}\mathrm{Load})}{V_o(\mathrm{Half}\mathrm{Load})}\right|\times 100\%$$

(9)

Therefore, the corresponding values of the load regulation percentages for Figure 29, Figure 30 and Figure 31 are 0.17%, 0.60% and 0.91%, respectively, which are all smaller than the 1% from industrial applications.

7.6. Line Regulation

Figure 32 shows the line regulation of the main output on the condition that the first and second secondary outputs are at the rated load. Figure 33 shows the line regulation of the first secondary output on the condition that the main and second secondary outputs are at the rated load. Figure 34 shows the line regulation of the second secondary output on the condition that the main and first secondary outputs are at the rated load. Afterwards, the line regulation percentage equation is defined to be the following:

$$\begin{gathered} \mathrm{Line}\mathrm{Regulation}\%= \\ \left|\frac{V_o(\mathrm{High}\mathrm{Input}\mathrm{Voltage})-V_o(\mathrm{Low}\mathrm{Input}\mathrm{Voltage})}{V_o(\mathrm{Rated}\mathrm{Input}\mathrm{Voltage})}\right|\times 100\% \end{gathered}$$

(10)

Therefore, the corresponding values of the line regulation percentages for Figure 32, Figure 33 and Figure 34 are 0.17%, 0.60% and 0.91%, respectively, which are all smaller than the 1% from industrial applications.

8. Comparisons

Table 5. Comparisons between the proposed circuit and the existing circuits.

Item	Proposed	[5]	[10]	[13]	[14]
Output Number	3	6	6	4	2
Feedback Number	3	1	1	4	2
Converter Type	Forward +SSPRs	Flyback	Push-pull + Coupled Inductor	Resonant Converter +Magnetic Amplifier	LLC+SSPRs
Voltages and Powers	12V/120W 5V/8A 3.3V/12A	16V/1.6W −16V/1.6W 16V/1.6W −16V/1.6W 16V/1.6W −16 V/1.6 W	3.4V/17.5W 6.4V/7.2W −6.4V/2.6W 14V/1.3W −14V/1.3W 14V/0.6W 60V/1.8W	3.3V/132W 5V/170W 12V/300W −12V/12W	100V/60W 100V/60W
Number of Passive Components	4 Magnetic Devices 0 Diodes	3 Magnetic Devices 6 Diodes	2 Magnetic Devices 16 Diodes	10 Magnetic Devices 16 Diodes	1 Magnetic Device 4 Diodes
Number of Active Components	7	1	2	10	4
Cross Regulation	Excellent	Poor	Medium	Good	Good
Advantages	High Accuracy Fast Load Transient Response	Single PWM IC and Switch	1 Transformer 1 Inductor	High Accuracy	High Accuracy
Disadvantages	Complex	High cost	Complex	Complex High Cost	Two Outputs with the Same Voltage
Rated-Load Efficiency	86%	NA	NA	85%	90%

shows the comparisons between the proposed circuit and the existing circuits, including output number, feedback number, converter type, voltages and powers, number of passive components, cross regulation, advantages, disadvantages, and rated-load efficiency. From Table 5, it can be seen that the proposed circuit has high accuracy, a fast transient load response and excellent cross regulation.

9. Conclusions

An SR forward converter with a set of three outputs takes the SSPR technology to control the stability of the output voltages. The output with the largest current adopts a two-phase interleaved structure, and the associated switching period is twice that of the main switch of the main output to facilitate the realization of the proposed current sharing strategy. The voltage/current sampling for each output adopts ADC-free sampling technology. In the two-phase current sampling for the second secondary output, the proposed interleaved current sampling method is employed so that the currents in two phases are sampled in the same position. As for the voltage controller to be concerned, a nonlinear control strategy is added to the traditional PID controller so that the main output can accelerate the load transient response when the load changes instantaneously. From the experimental results, as the transient load variations due to the main output happen, the effect of these variations on the secondary outputs is quite small, meaning that the proposed circuit has excellent cross regulation performance. In addition, a low current sharing error percentage, low load regulation percentage and low line regulation percentage are also advantages of the proposed circuit.