Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm
Abstract
:1. Introduction
- It introduces a Genetic Algorithm (GA)-based metascheduler for time-triggered NoC-based architectures.
- It presents a solution to combat the state-space explosion problem in the MSG using a reconvergence of paths algorithm.
- It implements a reconvergence horizon to maintain schedule generation within configured bounds.
- It further evaluates the reconvergence of paths algorithm using different input model sizes and configurations for the reconvergence horizon.
2. Related Work
3. System Model
3.1. Input Models
3.2. Output Model
4. Proposed Approach
4.1. Genetic Algorithm
Algorithm 1: Genetic Algorithm Adaptation for TTNoC Architecture. |
4.2. Metascheduler with Reconvergence of Paths in MSG
Algorithm 2: GA-based Metascheduler with reconvergence of paths in MSG. |
5. Results and Discussions
5.1. Architectures and Applications
5.2. Selection of Genetic Algorithm Parameters
5.3. Evaluation of State Space Reduction
5.4. State-Space Exploration Time
5.5. Sleep Time for Energy Saving
6. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Generation | Population | Computational Time (s) | Makespan |
---|---|---|---|
1000 | 100 | 31 | 444 |
1000 | 100 | 31 | 466 |
1000 | 100 | 32 | 457 |
1000 | 100 | 31 | 459 |
1000 | 100 | 32 | 427 |
1000 | 500 | 160 | 550 |
1000 | 500 | 162 | 508 |
1000 | 500 | 160 | 505 |
1000 | 500 | 160 | 485 |
1000 | 500 | 161 | 476 |
3000 | 100 | 96 | 508 |
3000 | 100 | 94 | 484 |
3000 | 100 | 93 | 493 |
3000 | 100 | 95 | 427 |
3000 | 100 | 93 | 436 |
3000 | 500 | 474 | 458 |
3000 | 500 | 474 | 450 |
3000 | 500 | 473 | 463 |
3000 | 500 | 476 | 544 |
3000 | 500 | 483 | 445 |
5000 | 100 | 158 | 439 |
5000 | 100 | 160 | 443 |
5000 | 100 | 158 | 478 |
5000 | 100 | 159 | 453 |
5000 | 100 | 158 | 449 |
5000 | 200 | 326 | 419 |
5000 | 200 | 322 | 385 |
5000 | 200 | 321 | 387 |
5000 | 200 | 321 | 410 |
5000 | 200 | 325 | 427 |
Setup | Scenario 1 | Scenario 2 | ||
---|---|---|---|---|
PBIL | Proposed | PBIL | Proposed | |
AM Size | 20 | 20 | 35 | 40 |
NoC Architecture | 3 × 3 | 3 × 3 | 3 × 3 | 3 × 3 |
Processors | 9 | 4 | 9 | 4 |
Computational Time | 30 | 8 | 110 | 22 |
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Muoka, P.; Onwuchekwa, D.; Obermaisser, R. Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm. Electronics 2022, 11, 49. https://doi.org/10.3390/electronics11010049
Muoka P, Onwuchekwa D, Obermaisser R. Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm. Electronics. 2022; 11(1):49. https://doi.org/10.3390/electronics11010049
Chicago/Turabian StyleMuoka, Pascal, Daniel Onwuchekwa, and Roman Obermaisser. 2022. "Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm" Electronics 11, no. 1: 49. https://doi.org/10.3390/electronics11010049
APA StyleMuoka, P., Onwuchekwa, D., & Obermaisser, R. (2022). Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm. Electronics, 11(1), 49. https://doi.org/10.3390/electronics11010049