New Heuristic Algorithm for Low Energy Mapping for 2.5-D Integration
Round 1
Reviewer 1 Report
1) Authors have focused on one specific set of 22 chiplets. Can you validate that your proposed algorithm works for other sets of chiplets?
2) It seems that your algorithm depends on the initial state. How can people judge that the final design done through your algorithm is the least energy consumption?
3) Authors need to address the computation cost as well.
4) Your proposed algorithm seems to consider ‘global routing’ which does not consider the physical routability. How did you consider the detail routing in the interposer die?
Author Response
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Author Response File: Author Response.pdf
Reviewer 2 Report
The direction of this work is quite interesting. A heuristic chiplet placement algorithm for 2.5D IC integration on interposer that incorporates the chiplet's size in its computations, is presented in this paper, and its efficiency is evaluated through adequate experimentation.
In order to enhance the clarity of results, the authors should enhance Figure 10(a).
Author Response
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Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
If the authors include more cases (other designs and many chiplets than 22), it would be better. Please do more experiments to validate your algorithm is effective.
Author Response
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Author Response File: Author Response.pdf