A High-Stability Regulation Circuit with Adaptive Linear Pole–Zero Tracking Compensation for USB Type-C Interface

Abstract

We present a high-stability regulation circuit to ensure the safety of a device within a wide range of the back-sink current for a USB Type-C interface application. The proposed adaptive linear pole–zero tracking compensation can linearly compensate for the changes in the back-sink current, thereby adaptively canceling the pole–zero changes caused by the current changes. The simulation results show that the phase margin remains greater than 60°. Meanwhile, the loop bandwidth changes between 45 kHz and 135 kHz, when the current increases from 0 A to 1 A, ensuring excellent loop stability. The high-stability regulation circuit is realized in a standard 180 nm CMOS process with an area of 0.4 mm × 0.6 mm. The chip regulates an output voltage from 4.5 V to 5.5 V with 1 A current capacity and 100 mV maximum dropout voltage with the help of the adaptive linear pole–zero tracking compensation.

1. Introduction

The USB Type-C interface is significantly advantageous over the conventional data transmission interfaces and has been widely used in various portable electronic devices such as notebooks, desktops and smartphones [1]. The current-limiting switch between the Type-C interface and peripherals is employed to prevent overcurrent, short-circuit or even reverse-current, thus effectively protecting the safety of the host and the device.

Figure 1 shows the schematic structure of a typical USB interface protection circuit. Two NMOS switches M_SW1 and M_SW2 are connected in series, and the substrate can be prevented from being turned on when the switch is turned off. In practice, M_SW1 is used for the current limit protection while M_SW2 is employed to protect against the reverse current. The voltage stabilization loop used to control M_SW2 is similar to the LDO structure, but the difference from the traditional LDO is that the dropout voltage of the loop needs to be reduced (<100 mV) to avoid the power loss of the switch itself [2,3,4,5,6,7,8,9,10,11]. Under such a low dropout voltage, the working state of the M_SW2 transistor is approximately in the linear region. It should be noted that according to the protocol requirements of USB3.X, the current flowing through the switch varies from 0 A to several amperes corresponding to the change of the load on the output terminal of the switch, which poses difficulties for the compensation of the loop stability [1].

Due to the large capacitance (microfarad-level) connected to the switch output as the stabilized capacitor for power supply measurement, the output pole appears at a very low frequency when the load current is small. A large capacitance is thus required for conventional Miller compensation, which, however, is unacceptable for a chip application with limited floor space. On the other hand, the traditional equivalent series resistor (ESR) compensation has the problem of zero drift with limited compensation stability [2]. Dynamic pole–zero tracking frequency compensation can compensate the first nondominant pole in multistage op-amps by dynamically generating zeros [3,4]. However, in the conventional pole–zero compensation method, although the tracking MOS transistor works in the saturation region, the zero resistance works in the linear region leading to a continuous change in the impedance, which can further result in a large variation in the relative position of the pole–zero in the full current range. This can have a significant influence on the variation range of the bandwidth, making it unsuitable for the application of a current limiting switch system. In this work, an adaptive linear pole–zero tracking compensation method is proposed by introducing a current detection loop and a constant bandwidth tracking loop. While the loop stability is not affected by the change of the load current, the gain bandwidth of the entire loop is constant at a certain level.

2. Traditional Regulation Circuit with Pole–Zero Tracking Compensation

Figure 2 shows the schematic structure of the circuit design with traditional pole–zero tracking compensation. The regulator loop is composed of a two-stage amplifier, pole–zero tracking voltage generator and output stage.

The pole–zero (PZ) dynamic compensation is realized by the output current sensor, PZ tracking voltage generator, M_RZ and C_C circuits. The current sensor mirrors and tracks the output current and realizes 1/K current scaling by adjusting the mirror ratio of M_SWB and M_SW2. The drain voltages of M_SWB and M_SW2 are equal through the function of OP1, achieving accurate copying of the current, which is subsequently output through the current mirror composed of M_N3 and M_N4. The current of M_P5 is the output of M_P2 and M_P3 current mirrors. As a result, the V_GS voltage of M_P5 is proportional to the output current. In addition, M_RZ and C_C form a zero, and the gate–source voltages of M_RZ and M_P5 are the same, which makes the on-resistance of M_RZ proportional to the output current. When the output current decreases, the output pole (P_o) and the V_GS voltage of M_P5 decrease. With a larger impedance of M_RZ, the frequency of the zero formed by M_RZ and C_C is lowered, realizing the tracking compensation of the output pole. The compensated voltage stabilizing loop has only one dominant pole at the output of EA1, which makes the entire loop stable.

From the above analysis, there exist two dominant poles located at V_OUT and EA1 in the traditional circuit with varying load current. In addition, the P_o at the V_OUT terminal will change with the varying load current. For example, with a small output current, R_L >> R_MSW2 (meanwhile, R_MSW1 << R_MSW2), and the output impedance at the V_OUT terminal is:

$$R_{\mathrm{L}}=\frac{V_{\mathrm{OUT}}}{I_{\mathrm{o}}}$$

(1)

$$P_{\mathrm{o}}=\frac{1}{R_{\mathrm{L}}\times C_{\mathrm{L}}}$$

(2)

The V_GS voltage of M_P5 is calculated as:

$$V_{\mathrm{GSP}5}=\sqrt{\frac{I_{\mathrm{o}}}{K\times \beta \times \raisebox{1ex}{$W_{\mathrm{P}5}$}\!\left/ \!\raisebox{-1ex}{$L_{\mathrm{P}5}$}\right.}}+V_{\mathrm{THP}}$$

(3)

Since the V_GS values of M_RZ and M_P5 are the same, and M_RZ is operating in the linear region, the on-resistance of M_RZ is:

$$\frac{1}{R_{\mathrm{Z}}}=\frac{W_{\mathrm{RZ}}}{L_{\mathrm{RZ}}}\times \sqrt{\frac{\beta \times I_{\mathrm{o}}}{K\times \raisebox{1ex}{$W_{\mathrm{P}5}$}\!\left/ \!\raisebox{-1ex}{$L_{\mathrm{P}5}$}\right.}}$$

(4)

Thus, the zero formed by M_RZ and C_C can be expressed as:

$$Z_C=\frac{1}{R_{\mathrm{Z}}{C}_C}=\frac{W_{\mathrm{RZ}}}{L_{\mathrm{RZ}}}\times \sqrt{\frac{\beta \times V_{\mathrm{OUT}}}{K\times R_{\mathrm{L}}\times \raisebox{1ex}{$W_{\mathrm{P}5}$}\!\left/ \!\raisebox{-1ex}{$L_{\mathrm{P}5}$}\right.}}\times \frac{1}{C_C}$$

(5)

The K in Equations (3)–(5) represents the ratio of sensor current, and W_MP5 and L_MP5 are the channel width and length of the M_P5 transistor. The frequency compensation can be achieved by using Z_C to cancel out P_o. However, due to the different dependence of P_o (Equation (2)) and Z_C (Equation (5)) on R_L, Z_C cannot track the change of P_o well when R_L varies in a large range. This can further result in a large change in bandwidth as well as a deterioration in stability.

3. Proposed Regulation Circuit with Adaptive Linear Pole–Zero Tracking Compensation

To solve the above issue, we propose a regulation circuit with an adaptive linear pole–zero tracking compensation, which is schematically illustrated in Figure 3. The entire circuit includes a two-stage amplifier (AMP STG1 and AMP STG2), buffer stage, output current sensor, adaptive linear PZ tracking voltage generator, output power transistor and load resistor and capacitor. Among these components, the AMP STG1 provides gain and the AMP STG2 provides low output impedance to push the output pole farther from the origin. The output power transistor provides a large current, and the output current sensor can achieve accurate reproduction of the output current. The adaptive linear PZ tracking voltage generator is used to perform the compensation of the output pole making the unity-gain bandwidth (GBW) of the feedback system constant while ensuring stability.

Figure 4 shows the pole−zero distribution of the proposed regulation circuit. There are four poles (P₁~P₃, P_o) and a zero (Z_C) in the circuit illustrated in Figure 3.

The four poles can be expressed as:

$$P_1=\frac{1}{R_{\mathrm{o}1}{C}_{\mathrm{o}1}}$$

(6)

$$P_2=\frac{1}{R_{\mathrm{o}2}{C}_{\mathrm{o}2}}$$

(7)

$$P_3=\frac{1}{R_{\mathrm{o}3}{C}_{\mathrm{o}3}}=\frac{g_{m\mathrm{MSW}}}{C_{\mathrm{o}3}}$$

(8)

$$P_{\mathrm{o}}=\frac{1}{R_{\mathrm{L}}{C}_{\mathrm{L}}}$$

(9)

Figure 5 shows the detailed structure of the adaptive linear pole–zero compensation voltage regulation circuit (M_SW1 and M_SW2 are represented and labeled by M_SW for a better description). The linear pole–zero tracking voltage generator is composed of OP2, M_N5 and R_B. The voltage potential at points A and B are clamped to be equal though OP2, which makes the V_DS voltage of M_N5 equal to the voltage across R_B, V_DSN5 = V_RB. M_N5 can be modulated to work in the linear region through V_RB making V_DSN5 = V_RB = V_drop. The output of OP2 also functions as the gate voltage of both M_RZ and M_N5.

From the circuit shown in Figure 5, M_N5 is in the linear region, and the drain–source current of M_N5 is:

$$I_{\mathrm{DSN}5}=\beta \times \frac{W_{\mathrm{N}5}}{L_{\mathrm{N}5}}\times (V_{\mathrm{GSN}5}-V_{\mathrm{THN}5})\times V_{\mathrm{DSN}5}$$

(10)

There is a fixed 1/K relationship between the drain–source current of M_N5 and the output current due to the current mirror:

$$I_{\mathrm{DSN}5}=\frac{I_{\mathrm{o}}}{K}$$

(11)

From Equations (10) and (11), the V_GS of M_N5 transistor is:

$$V_{\mathrm{GSN}5}=\frac{I_{\mathrm{o}}}{K\times \beta \times V_{\mathrm{DSN}5}\times \raisebox{1ex}{$W_{\mathrm{N}5}$}\!\left/ \!\raisebox{-1ex}{$L_{\mathrm{N}5}$}\right.}+V_{\mathrm{THN}}$$

(12)

Considering the fact that the V_GS values of M_RZ and M_N5 are the same, and both work in the linear region, the on-resistance of M_RZ can be obtained by:

$$R_{\mathrm{Z}}=\frac{1}{K\times \beta \times \raisebox{1ex}{$W_{\mathrm{RZ}}$}\!\left/ \!\raisebox{-1ex}{$L_{\mathrm{RZ}}$}\right.\times (V_{\mathrm{GSRZ}}-V_{\mathrm{THN}})}$$

(13)

$$V_{\mathrm{GSRZ}}=V_{\mathrm{GSN}5}$$

(14)

From Equations (11)–(14), we can obtain:

$$\frac{1}{R_{\mathrm{Z}}}=\frac{I_{\mathrm{o}}\times \raisebox{1ex}{$W_{\mathrm{RZ}}$}\!\left/ \!\raisebox{-1ex}{$L_{\mathrm{RZ}}$}\right.}{\raisebox{1ex}{$W_{\mathrm{N}5}$}\!\left/ \!\raisebox{-1ex}{$L_{\mathrm{N}5}$}\right.}$$

(15)

The corresponding zero can be obtained from Equation (15):

$$Z_C=\frac{1}{R_{\mathrm{Z}}{C}_C}=\frac{I_{\mathrm{o}}\times \raisebox{1ex}{$W_{\mathrm{RZ}}$}\!\left/ \!\raisebox{-1ex}{$L_{\mathrm{RZ}}$}\right.}{\raisebox{1ex}{$W_{\mathrm{N}5}$}\!\left/ \!\raisebox{-1ex}{$L_{\mathrm{N}5}$}\right.}\times \frac{1}{C_C}=\frac{V_{\mathrm{OUT}}\times \raisebox{1ex}{$W_{\mathrm{RZ}}$}\!\left/ \!\raisebox{-1ex}{$L_{\mathrm{RZ}}$}\right.}{R_{\mathrm{L}}\times \raisebox{1ex}{$W_{\mathrm{N}5}$}\!\left/ \!\raisebox{-1ex}{$L_{\mathrm{N}5}$}\right.}\times \frac{1}{C_C}$$

(16)

Compared to the traditional circuit design, in our proposed circuit design, both P_o and Z_C are in a first-order linear relationship to R_L, as indicated by Equations (9) and (16), respectively, realizing the linear tracking and compensation of Z_C with a different loading current.

4. Simulation and Experimental Test Results

The positions of the poles are the outputs of each stage with P₁ as the dominant pole and P_o as the first nondominant pole. P₂ and P₃ are far away from P₁ due to the small equivalent input capacitance and equivalent output impedance, and do not affect the stability of the loop. Then, we can plot the location of the poles of the proposed regulation circuit as shown in Figure 6. From Equations (9) and (16), it can be seen that both Z_C and P_o have a first-order linear proportional relationship with I_O. When the load changes, Z_C can be used to track and compensate for the change of P_o linearly. Thus, we can obtain a high-stability loop in a wide current range.

Figure 7 shows the continuous change of GBW and the phase margin under different load currents. The current changes from 0 A to 1 A, and the GBW changes from 45 kHz to 135 kHz. The phase margin is greater than 60° in the full current range ensuring excellent loop stability.

The proposed high−stability regulation circuit was designed in a 180 nm CMOS process. The chip micrograph is shown in Figure 8, and the die size is 400 × 600 μm².

Figure 9 shows the measured load transient responses when the load changes between 0.2 A and 1 A. From the figure, the output V_O shows undershoot and overshoot voltages of −187.6 mV and 175.4 mV, respectively. The 0.5% settling times are 175 μs and 177 μs, respectively. The test result indicates an enhanced working stability of the entire loop.

Finally, we compared the performance that can be achieved by the currently reported compensation methods of voltage stabilization loops. The comparison is listed in

Table 1. Comparison Table.

	Ref. [6]	Ref. [9]	Ref. [10]	Ref. [11]	This Work
Technology (nm)	180	130	90	180	180
Power MOS	PMOS	PMOS	PMOS	PMOS	PMOS
Output cap. (μF)	4.7	4	1	17	10
Supply voltage (V)	1.6~5.5	>1.15	1	1.5~3.3	4.5~5.5
Quiescent current (μA)	424	50	46	790	100
Output current (A)	1	0.025	0.1	6	2
Dropout voltage (mV)	200	>150	150	110	75
GBW range	-	-	-	26.5~1.48 MHz	45~135 kHz
PM range	35~95°	-	-	14.9–61°	61~80°
Area (mm × mm)	1.4	0.049	0.0041	6.3	0.24

in terms of process, dropout voltage, output capacitor and the maximum output current I_o(max). From the comparison result, it is found that within the full load range, the bandwidth change of the regulation circuit proposed in this paper is the smallest, the stability of the system is better and a smaller drop voltage can be achieved.

5. Conclusions

In summary, an adaptive linear pole–zero tracking compensation was proposed in this paper, by changing the tracking transistor from the traditional saturation region to the triode region for a good linear match to the resistance of the zero-adjusting resistor. The frequency change of the zero and the first nondominant pole was linearly consistent. From the simulation and test results, the bandwidth change range was very small within the full load range, due to the high linearity of the zero and the first nondominant pole with the load change. Further delicate circuit design and engineering will shed more light on this issue towards advanced USB Type-C interface applications.