Error Detection and Correction of Mismatch Errors in M-Channel TIADCs Based on Genetic Algorithm Optimization

Abstract

In order to achieve higher system performance, a digital calibration technique for the sub-channel mismatches of time-interleaved ADCs (TIADCs) is proposed in this paper. The sine-fit-based estimation algorithm is introduced to estimate the channel mismatches and a calibration algorithm is proposed to compensate for the mismatches. Subsequently, the genetic algorithm (GA) is firstly utilized to detect the mismatch errors of the outputs of sub-channels after frequency domain filtering. The detected offset error and gain error are then corrected by performing the calibration algorithm, and the time errors are corrected by fractional delay filters based on Farrow structure. The spurious-free dynamic range (SFDR) is enhanced from 19.69 dB to 108.12 dB, and the signal to noise and distortion ratio (SNDR) is enhanced from 16.02 dB to 97.63 dB. The proposed technique is further validated on the FPGA. Compared with existing calibration techniques, the proposed technique has the advantages of simple algorithm structure, low hardware resource consumption, and high calibration accuracy and can be applied to the calibration of high-resolution (18-bit) TIADCs for low-frequency inputs.

1. Introduction

In view of a single ADC hardly meeting the requirements for both high sampling frequency and high resolution, designers have paid attention to the TIADC technique. This is a multi-channel data-parallel acquisition technique realized by the precise cooperation between each sub-channel [1,2,3]. Figure 1 shows the block diagram of an M-channel TIADC and its timing diagram. TIADCs are composed of M identical sub-ADCs working in parallel modes. Each sub-channel of a TIADC system consists of a sub-ADC with its own sampling and holding (S/H) circuit which is sampled and held at interleaved times. The sampling interval of each sub-channel is ${MT}_s$. Therefore, the overall sampling rate of a TIADC system is M times higher than that of a single chip of ADC. In theory, this system increases the sampling rate of the ADC by a factor of M, and the sampling resolution of ADC is not reduced. A continuous analog input signal x(t) is sequentially sampled and digitized by the sub-ADCs to produce digital streams independently, and the TIADC system will eventually superpose each sub-channel output to produce a discrete digital output signal y[n] as is shown in Figure 1a.

However, due to the existence of different peripheral circuits and temperature variations of different sub-ADCs, the working conditions of each sub-channel cannot keep consistent, which results in channel mismatches. The channel mismatches mainly include the offset mismatch, the gain mismatch and the timing mismatch [4,5,6]. They introduce spurious spectra into the output spectrum, deteriorating the SNDR and SFDR of a TIADC, which severely degrades the performance of a TIADC system [7,8,9,10], especially for the high resolution requirement.

To solve the above limitation, multiple calibration techniques on TIADCs have been proposed. We classify them into two kinds: error detection and error correction. Error detection typically adds an additional auxiliary channel [11] to obtain the mismatch errors and then exploits fast interpolation for real-time calibration. This technique needs an additional channel, which increases the complexity and cost of the calibration system. In Ref. [12], the author used the difference between two adjacent channels as the judgment basis for the timing mismatch. The algorithm does not need complex computation such as multiplication but needs more sampling times to converge. In Refs. [13,14], the blind estimation algorithm was adopted to detect the timing mismatch of the system. The output of each channel can be directly utilized to estimate the sampling time error without a known signal in this algorithm. However, the error estimation performance of the blind estimation algorithm is worse than that of the non-blind estimation algorithm [15]. Error correction mainly includes offset, gain and timing mismatch correction, where the offset and gain mismatch error correction is a relatively simple technique. As a result, many works have been published recently on timing mismatch calibration. In Refs. [12,16], the phase of each clock was fine-tuned by the digital analog mixed method by adjusting the analog delay line. This method is easily affected by voltage, aging and other factors. In Refs. [17,18,19], the timing mismatch can be calibrated with a small number of conversions by the technique based on the split-ADC structure, which is limited to a low-resolution or moderate-resolution TIADC system. In Refs. [20,21], the author used a filter-bank structure to reconstruct the non-uniform sampled signals at the cost of an additional oversampling rate and higher hardware resource consumption. In Ref. [22], the author introduced an extra reference channel and used the correlation results to achieve the calibration, but the reference channel consumed hardware too. In Refs. [23,24], a technique based on the Hadamard transform was used to compensate for the timing mismatch which only required a fixed-coefficient FIR filter, thus simplifying the correction structure. However, only some special channel numbers have Hadamard transforms, which limits the application of this technique.

In this paper, we propose a genetic algorithm (GA)-based error detection and correction technique to optimize M-channel TIADCs. It is mainly divided into two steps: primary course correction and secondary fine correction. The sine-fit-based algorithm is utilized to estimate the existing offset, gain and timing mismatch, and these mismatch errors are roughly corrected with the derived correction algorithm. In the second step, frequency domain filtering is performed to eliminate the white Gaussian noise. Subsequently, the proposed GA technique is used to implement optimization and second detection [25]. Finally, the derived correction algorithm is used to implement the second fine correction for offset and gain mismatch, and a fractional delay filter based on Farrow structure is used to compensate for the remaining timing mismatch. As a result, the accuracy of the overall calibration is very high.

The highlights of this paper are as follows. Firstly, GA optimization is first proposed to detect and calibrate the offset, gain and timing mismatch at the same time. Secondly, no reference channel is added in the technique, which makes for small hardware consumption. Thirdly, the calibration technique can be applied to the calibration of high-resolution (18-bit) TIADCs for low-frequency inputs. The brief is organized as follows. In Section 2, an error detection and correction technique based on GA optimization is proposed. Section 3 simulates and analyzes the performance of the proposed technique. The hardware validation on FPGA is also presented. Finally, the conclusion and future directions are drawn in Section 4.

2. Materials and Methods

2.1. Model of TIADCs’ Mismatch Errors

The channel mismatch error model of a TIADC system is as shown in Figure 2. There are M sub-ADCs, and m is the channel index number. The aggregate sampling period is $T_s$ and the corresponding sampling rate is $f_s$ = 1/$T_s$. The adder $o_m$ is used to represent the offset mismatch error of each channel and the multiplier $g_m$ is used to represent the gain mismatch error of each channel. The delayer $H_m$(${\mathrm{e}}^{\mathrm{jw}}$) is used to equal the clock delay and the timing mismatch error, and the timing mismatch error is $r_m$$T_s$. The sampling time can be expressed as follows.

$$t_n=nM{T}_s+m{T}_s$$

(1)

Assuming the analog input signal is a single-frequency sine wave, its time domain expression is

$$x\left(t\right)=\sin \left(2\pi f_{in}t\right)$$

(2)

where $f_{in}$ is the input signal frequency of the TIADC. Putting the existence of the three mismatch errors in the system into consideration, at the n-th sampling time, the output of the m-th channel can be expressed as follows:

$$x_m\left[n\right]=(1+g_m)\sin \left(2\pi f_{in}(t_n+r_m{T}_s)\right)+o_m$$

(3)

2.2. Sine-Fit-Based Estimation and the First Correction

A sine wave includes four parameters, i.e., frequency, amplitude, phase and DC component [26,27]. The goal of sine fitting is to obtain the best fit values of the above parameters from the uniformly sampled sine wave signal. Here, we apply this method to the TIADC system, in which the error parameters of each channel are obtained by fitting the sampled sequence.

Formula (3) can be transformed as

$$x_m\left[n\right]=A_m\cos \left(2\pi f_{in}{t}_n\right)+B_m\sin \left(2\pi f_{in}{t}_n\right)+C_m$$

(4)

where

$$\left\{\begin{array}{cc}\hfill & A_m=(1+g_m)\sin \left(2\pi f_{in}{r}_m{T}_s\right)\hfill \\ \hfill & B_m=(1+g_m)\cos \left(2\pi f_{in}{r}_m{T}_s\right)\hfill \\ \hfill & C_m=o_m\hfill \end{array}\right.$$

(5)

Assuming that the TIADC’s actual sampled value of the m-th channel at the n-th sampling time is $y_m$[n], the goal is to find a set of $A_m$, $B_m$ and $C_m$ to minimize the squared sum of the differences between $y_m$[n] and $x_m$[n], as shown in Formula (6).

$$\epsilon =\sum _{n=1}^N{(y_m\left[n\right]-x_m\left[n\right])}^2=\sum _{n=1}^N(y_m\left[n\right]-A_m\cos \left(2\pi f_{in}{t}_n\right)-B_m\sin \left(2\pi f_{in}{t}_n\right)-C_m)$$

(6)

Since the frequency of the input signal is known, only three parameters of the sine wave need to be considered. In order to find the best fit values for $A_m$, $B_m$ and $C_m$, the following matrices are established.

$$D=\left[\begin{array}{ccc}\cos \left(2\pi f_{in}{t}_1\right)& \sin \left(2\pi f_{in}{t}_1\right)& 1\\ \cos \left(2\pi f_{in}{t}_2\right)& \sin \left(2\pi f_{in}{t}_2\right)& 1\\ ⋮& ⋮& ⋮\\ \cos \left(2\pi f_{in}{t}_N\right)& \sin \left(2\pi f_{in}{t}_N\right)& 1\end{array}\right]$$

(7)

$$y_m={[y_m\left[1\right]y_m\left[2\right]\cdots y_m\left[N\right]]}^T$$

(8)

$$S_m={\left[A_m{B}_m{C}_m\right]}^T$$

(9)

Then, Formula (6) can be expressed in matrix form as Formula (10).

$$\epsilon ={(y_m-D·S_m)}^T(y_m-D·S_m)$$

(10)

Its least square (LS) solution is [28]:

$${\widehat{S}}_m={(D^T·D)}^{-1}(D^T·y_m)={\left[{\widehat{A}}_m{\widehat{B}}_m{\widehat{C}}_m\right]}^T$$

(11)

Substituting Formula (11) into Formula (5), the estimated results of each sub-channel’s mismatch errors can be calculated as follows:

$$o_m={\widehat{C}}_m$$

(12)

$$g_m=\sqrt{{{\widehat{A}}_m}^2+{{\widehat{B}}_m}^2}-1$$

(13)

$$r_m{T}_s=\frac{\arctan \left(\frac{{\widehat{A}}_m}{{\widehat{B}}_m}\right)}{2\pi f_{in}}$$

(14)

According to the estimated mismatch errors, the correction algorithm can be derived. The parameters obtained in Formulas (12)–(14) are used as the initial parameters to reconstruct the signal to perform the first error correction on the output sampled data of the M-channel TIADCs. The output signals of each sub-channel before correction are given as $x_1$, $x_2$, …, $x_m$, …, $x_M$. We record the error parameters estimated by the sine-fit-based algorithm as $o_m^{{}^{\prime }}$, $g_m^{{}^{\prime }}$ and $r_m^{{}^{\prime }}$.

Since both the offset mismatch and the gain mismatch are independent of the timing mismatch, the subtractors and the multipliers can be used for simple correction.

$$x{\left(n\right)}^{\prime }=x\left(n\right)-o_m^{{}^{\prime }}$$

(15)

$$x{\left(n\right)}^{″}=\frac{x{\left(n\right)}^{\prime }}{1+g_m^{{}^{\prime }}}$$

(16)

Since the sine-fit-based estimation method has very high error estimation accuracy for the offset error and the gain error (Ref. [29]), the timing mismatch error can be calibrated by performing the following process on x(n)${}^{″}$:

$$x{\left(n\right)}^{‴}=\sin \left(2\pi f_{in}(t_n+r_m{T}_s-r_m^{{}^{\prime }}{T}_s)\right)$$

(17)

Expanding Formula (17) gives

$$x{\left(n\right)}^{‴}=\sin \left(2\pi f_{in}(t_n+r_m{T}_s)\right)\cos \left(2\pi f_{in}{r}_m^{{}^{\prime }}{T}_s\right)-\cos \left(2\pi f_{in}(t_n+r_m{T}_s)\right)\sin \left(2\pi f_{in}{r}_m^{{}^{\prime }}{T}_s\right)$$

(18)

Transforming Formula (18) gives

$$x{\left(n\right)}^{‴}=\sin \left(2\pi f_{in}(t_n+r_m{T}_s)\right)\cos \left(2\pi f_{in}{r}_m^{{}^{\prime }}{T}_s\right)-\sqrt{1-{\sin }^2\left(2\pi f_{in}(t_n+r_m{T}_s)\right)}\sin \left(2\pi f_{in}{r}_m^{{}^{\prime }}{T}_s\right)$$

(19)

where $\sin \left(2\pi f_{in}(t_n+r_m{T}_s)\right)$ can be equivalent to the signal x(n)${}^{″}$, which has been obtained from Formula (16). Thus, the timing mismatch error is corrected.

2.3. Frequency Domain Filtering Correction

Due to the inherent noise interference in sub-ADCs, frequency domain filtering correction is performed on the sampled data x(n)${}^{‴}$ after the first correction. The block diagram of frequency domain filtering correction is shown in Figure 3a. The output signals of each channel after the first correction are given as $x_{1,jz}$, $x_{2,jz}$, …, $x_{m,jz}$, …, $x_{M,jz}$. Here, the procedure of frequency domain filtering correction is described as follows: (1) a set of band-pass filters $H_1$(w), $H_2$(w), …, $H_m$(w), …, $H_M$(w) are constructed to filter the noise according to the spectrum peaks of the signals $x_{1,jz}$, $x_{2,jz}$, …, $x_{m,jz}$, …, $x_{M,jz}$; (2) the inverse fast Fourier transform (IFFT) is performed to obtain the filtered time domain signals, which are is recorded as $x_{1,ff}$, $x_{2,ff}$, …, $x_{m,ff}$, …, $x_{M,ff}$.

As is shown in Figure 3, frequency domain filtering correction is mainly used to filter the white noise in the signals after the first correction. It can help reduce the error caused by the white noise in the detection of the later error parameters. Then, the accuracy of the later error parameter estimation and correction can be improved.

The signals corrected by frequency domain filtering will be slightly deformed. However, the LS method cannot be used to estimate the deformed parameters.

2.4. Error Estimation and Correction Based on GA Optimization

Here, the GA optimization algorithm is used to perform the further estimation and correction for the signals $x_{1,ff}$, $x_{2,ff}$, …, $x_{m,ff}$, …, $x_{M,ff}$. The idea of the algorithm is summarized as follows: We take the minimum of errors between the signals to be further corrected and the standard signals as the optimization goal. Meanwhile, the error parameters are optimized in these iterations. Once the optimization is finished, the optimal error parameters can be obtained.

Throughout the optimization, these mismatch errors are determined by the GA and constantly iterated to obtain better parameters. The offset, gain and sampling time errors in each channel of the TIADCs can be detected when the optimization is done, as shown in Figure 3b.

The following steps are mainly involved in GA:

(i). Generation of chromosomes

Since the problem is to determine the offset, gain and sampling time errors, a random population with the number of individuals (P) is created, and three error phenotypes are contained in the individuals. Here, the way of binary coding is used. The advantage of binary coding is simple and can be implemented easily. The coding can be completed by 0 and 1, which makes the operations of the GA convenient. The relationship between the coding parameter u and the coding is as follows:

$$u=u_{min}+\frac{a}{2^l-1}(u_{max}-u_{min})$$

(20)

where u is the parameter of binary coding and $u_{min}$ and $u_{max}$ are the minimum value and maximum value of u, respectively. a represents the encoded value and l represents the coding length.

(ii). Selection

A new binary population is formed by a part of the chromosomes selected from the old binary population randomly. The main selection methods of GA are proportion selection and ranking selection, and the error of the result is relatively large for proportion selection. Hence, the ranking selection is chosen in this paper. The essence of the selection is that the two parent chromosomes are selected according to the fitness of them, and the better the fitness, the bigger the chance to be selected.

(iii). Cross Over

The cross over operation is performed on the selected p chromosomes, and the gene exchange is carried out with a cross over probability. The function of the cross over is to recombine two chromosomes to generate two new ones. The cross over operation is performed among all chromosomes to generate new ones (children). The characteristics of the parent chromosomes are inherited in the new chromosomes, and the new chromosomes have advantages that the parent chromosomes do not have.

(iv). Mutation

The mutation operation is performed on new chromosomes generated by cross over with a mutation probability. Here, the mutation of a gene is realized by the mutation of a chromosome’s bit. One bit is randomly selected in the chromosomes and mutated, i.e., changing 0 to 1 or 1 to 0. The chromosomes obtained by mutation are added to previous chromosomes once again, i.e., parent and child chromosomes.

(v). Fitness function

The fitness function is used to evaluate the fitness of all these chromosomes after mutation. Here, the fitness function is chosen based on the error in sample values and the minimum error between the signal to be further corrected, and according to the principle of the sine fit calibration method, the input standard sine wave signal is taken as the optimization goal.

The fitness function F of an individual i is given as follows:

$$F=mean\left(F_{mi}\right)$$

(21)

$$F_{mi}=mean\left(e_{mi}\left(n\right)\right)$$

(22)

$$e_{mi}\left(n\right)=|x_m\left(n\right)-x_{m,ff}\left(n\right)|$$

(23)

where $x_m$(n) represents the m-th time interleaved ADC’s sampling signal without channel mismatch errors and $x_{m,ff}$(n) represents the m-th channel’s signal obtained by filtering $x_{m,jz}$(n) in the frequency domain. During the calculation, it is more reasonable to calculate the average values for individuals and channels.

(vi). Test

The fitness function F should satisfy the condition F ≤ $F_{min}$, where $F_{min}$ is the minimum value of the fitness function F. If this condition is not satisfied, all the above steps are repeated until it is satisfied. When it is satisfied, the optimal value and its serial number I are output and the three mismatch errors written as $o_m^{{}^{″}}$, $g_m^{{}^{″}}$ and $r_m^{{}^{″}}$$T_s$ will be detected by GA optimization, i.e., $o_m^{{}^{″}}$ = $o_m$(I), $g_m^{{}^{″}}$ = $g_m$(I), $r_m^{{}^{″}}$$T_s$ = $r_m$(I)$T_s$. The diagram for this algorithm is shown in Figure 4a.

2.5. The Second Fine Correction for Offset Error and Gain Error

The second fine correction for the offset error and the gain error is the same as the correction for the offset error and the gain error in Section 2.2. The subtractors and the multipliers can be used for the fine correction. As shown in Formulas (24) and (25),

$$x_{m,ga}\left(n\right)=x_{m,ff}\left(n\right)-o_m^{{}^{″}}$$

(24)

$$x_{m,ga}{\left(n\right)}^{\prime }=\frac{x_{m,ga}\left(n\right)}{1+g_m^{{}^{″}}}$$

(25)

The calibration for the timing mismatch error can be realized by Formula (19). However, its calibration is related to the frequency of the input signal $f_{in}$, which affects the calibration accuracy of the sampling time error. Therefore, a more appropriate algorithm is needed to calibrate the sampling time error accurately.

2.6. Calibration of Farrow Fractional Delay Filters

Now, the only timing mismatch error in the TIADC system is reconsidered and the timing mismatch error of m-th channel is still expressed as $\Delta$$t_m$ = $r_m$$T_s$. Assuming that the Fourier transform of the input signal x(t) is $x^{\beta }$(w), after sampling by TIADC system, the digital spectrum of the sequence can be expressed as

$$X\left(w\right)=\frac{1}{M{T}_s}\sum _{m=0}^{M-1}\sum _{k=-\infty }^{\infty }(X^{\beta }[w-k(\frac{2\pi }{M{T}_s})]·e^{-j(w-k\frac{2\pi }{M{T}_s})r_m}·e^{-jmk\frac{2\pi }{M}})$$

(26)

If x(t) is a complex sinusoidal virtual signal $e^{j{w}_{0}t}$ with an angular frequency of $w_0$($2\pi f_0$), its Fourier transform is

$$X^{\beta }\left(w\right)=2\pi \sigma (w-w_0)$$

(27)

Substituting Formula (27) into Formula (26) gives

$$X\left(w\right)=\frac{1}{M{T}_s}\sum _{m=0}^{M-1}\sum _{k=-\infty }^{\infty }(2\pi \sigma [w-w_0-k(\frac{2\pi }{M{T}_s})]·e^{-j(w-k\frac{2\pi }{M{T}_s})r_m}·e^{-jmk(\frac{2\pi }{M})})$$

(28)

It can be seen from Formula (28) that to recover the uniformly sampled spectra from the non-uniformly-sampled signal, an all-pass filter $e^{-jw{r}_m}$ is needed to correct the sampling time error.

According to Formula (28) and the time shift characteristic of the Fourier transform, the time domain delay $\Delta t_m$ = $r_m$$T_s$ of the signal is equivalent to multiplying the frequency domain value multiplied by $e^{-jw{r}_m}$ when the frequency domain changes. Therefore, an all-pass filter with the ideal frequency response $e^{-jw{r}_m}$ can be used to finish the correction as long as the $\Delta t_m$ of each channel is detected. Since the coefficients of an all-pass filter are infinite, it cannot be implemented in FPGA. In order to implement real-time correction in FPGA, an FIR filter is used here to approximate it. Assuming that an N-order FIR filter is used to approximate $h_d$(n), the transfer function is represented as follows:

$$H_d\left(z\right)=\sum _{n=0}^{N-1}{h}_d\left(n\right)z^{-n}$$

(29)

After GA optimization, we obtain ∣$r_m$∣ < 1, showing that the filter is a fractional delay filter. With the aging of electronic devices and the influence of the environment, the mismatch error between channels is always changing. This increases the difficulty of calculating the coefficients of the fractional delay filters.

An efficient real-time correction algorithm can be implemented by Farrow structure filters. The coefficients of the fractional delay filters can be obtained in advance with this structure. Then, the coefficients of each filter are approximated by polynomials, and the N-order filter is further decomposed into N (P + 1)-order sub-filter banks. Once the filter coefficients are obtained, the timing mismatch error can be calibrated only by changing the delay value in the Farrow structure filter. We can expand $h_d$(n) with respect to $r_m$ by performing the polynomial expansion to obtain

$$h_d\left(n\right)\approx \sum _{k=0}^P{b}_k\left(n\right)r_m^k,n=0,1,\cdots ,N-1,m=0,1,cdots,M-1$$

(30)

The $b_k\left(n\right)$ can be obtained by the Lagrange interpolation algorithm. The formula of the fractional delay filter is expressed in Formula (31). The output of the TIADC system filtered by fractional delay filters can be obtained. The expression of it is shown in Formula (32). Then, Formula (32) is recombined according to similar items of r to obtain the $b_k\left(n\right)$.

$$H_d\left(z\right)\approx \sum _{n=0}^{N-1}\sum _{k=0}^P{b}_k\left(n\right)r_m^k{z}^{-n}=\sum _{k=0}^P[\sum _{n=0}^{N-1}{b}_k\left(n\right)z^{-n}]r_m^k=\sum _{k=0}^P{B}_k\left(z\right)r_m^k$$

(31)

$$h\left(r\right)=\prod _{l=0,l\ne k}^P\left(\frac{r-l}{k-l}\right),\mathbf{0}\le k\le P$$

(32)

$$x_{ccrr}\left(n\right)=\sum _{k=0}^{P}h\left(r\right)x(n-k)=\sum _{k=0}^P\prod _{l=0,l\ne k}^P\left(\frac{r-l}{k-l}\right)x(n-k)$$

(33)

Formula (33) is equivalent to the first P-term of $Z^{-rm}$ expanded by a Taylor series. Therefore, the all-pass filter structure shown in Figure 4b can be obtained.

3. Results

To evaluate the effectiveness of the proposed method, the simulated results of a four-channel TIADC with a sampling frequency of 64 Ms/s are shown (the sampling rate of an 18-bit high-resolution ADC is usually slower than 20 Ms/s). The resolution of the TIADC is 18 bits. The added offset mismatch error is $o_m$ = [$o_1$, $o_2$, $o_3$, $o_4$] = [0.1, 0.2, 0.1, 0.3], the added gain mismatch error is $g_m$ = [$g_1$, $g_2$, $g_3$, $g_4$] = [0.0, 0.4, 0.3, 0.4], and the added timing mismatch error is $r_m$$T_s$ = [10.0, 40.0, 50.0, 40.0]·$T_s$. The input signal for the test is a single-frequency sine wave signal and its frequency is $f_{in}$ = 1 kHz (for example, a speech signal).

3.1. Detection of Mismatch Errors

Table 1. The detection of mismatch errors by sine-fit-based estimation algorithm and GA optimization.

Sub-ADC	Error Type
	$o_m$	$o_m^{\prime }$	$o_m^{″}$	$g_m$	$g_m^{\prime }$	$g_m^{″}$	$r_m$	$r_m^{\prime }$	$r_m^{″}$
ADC0	0.1	0.1000	0.0049 × ${10}^{-4}$	0.0	0.0000	−0.0001 × ${10}^{-4}$	10	7.0251	−0.0998
ADC1	0.2	0.2000	0.0098 × ${10}^{-4}$	0.4	0.4000	0.0195 × ${10}^{-4}$	40	37.9693	0.4000
ADC2	0.1	0.1000	0.1610 × ${10}^{-4}$	0.3	0.3000	−0.2488 × ${10}^{-4}$	50	48.9833	−0.2502
ADC3	0.3	0.3000	−0.0146 × ${10}^{-4}$	0.4	0.4000	−0.1366 × ${10}^{-4}$	40	40.0438	−0.0004

shows the actual mismatch errors, the estimated mismatch errors by the sine-fit-based estimation algorithm and the detected mismatch errors by GA optimization (four significant digits are retained in the estimated results).

Table 1 is given to show that the sine-fit-based estimation algorithm has high estimation accuracy for the offset error and the gain error but low estimation accuracy for the sampling time error. The proposed algorithm based on GA optimization mitigates the effect of timing mismatch between sub-ADCs greatly.

Figure 5 expresses the optimization process of the GA. It can be found from Figure 5 that the value of fitness function F changes with the number of iterations. The proposed algorithm converges after about 60 iterations, and the minimum fitness function F of the best individual (I) is 2.355 × ${10}^{-3}$.

3.2. Correction of Mismatch Errors

The output spectra of the four-channel TIADC before correction are shown in Figure 6a. It can be seen from Figure 6a that the spurious spectra appear in the frequencies of (16 MHz-$f_{in}$), 16 MHz, (16 MHz+$f_{in}$), (32 MHz-$f_{in}$) and 32 MHz, respectively. Due to the low frequency setting of $f_{in}$, spurious lines appear in (16 MHz-$f_{in}$) and (16 MHz+$f_{in}$) coinciding with the spurious line in 16 MHz, and a spurious line appears in (32 MHz-$f_{in}$) coinciding with that in 32 MHz. The description will not be repeated in subsequent simulations. The distortion is caused by the channel offset, gain and timing mismatch, which limits the dynamic performance of the TIADC severely. The SFDR of the TIADC is only 19.69 dB, the SNDR is only 16.02 dB and the effective number of bits (ENOB) is only 2.37 bits.

The output spectra of the four-channel TIADC after the first correction are exhibited in Figure 6b. The SFDR is improved to 57.10 dB, the SNDR is improved to 49.35 dB and the ENOB is improved to 7.91 bits. It can be found that the spurious spectra are reduced to some extent. However, the first estimation accuracy of the sampling time error is low and the calibration effect is limited. As a result, the performance of the TIADC system is still limited by the noise introduced by ADCs and the noise caused by the timing mismatch. For an 18-bit high-resolution TIADC, the performance is far from the requirements. In fact, the dynamic range (DR) of the TIADC needs to be greater than 100 dB.

The output spectra of the four-channel TIADC after the second fine correction for offset error and gain error are exhibited in Figure 6c. It can be seen that compared with the signal after the first calibration, the spurs caused by channel mismatch are reduced dramatically. In addition, the white noise introduced by ADCs is greatly decreased by the correction of frequency domain filtering. The SFDR is enhanced to 87.90 dB, the SNDR is enhanced to 80.38 dB and the ENOB is enhanced to 13.06 bits, which indicates the effectiveness of the proposed calibration method based on GA optimization.

The output spectra of the four-channel TIADC after the calibration of Farrow fractional delay filters are depicted in Figure 6d. Here, the order of the designed Farrow filter is 8, and the polynomial order for the Farrow structure is 5. The normalized bandwidth is 0.5. As can be seen, compared with Figure 6c, the spurs due to timing mismatch are further reduced. The proposed Farrow structure obtains an SFDR improvement of approximately 20 dB and an SNDR improvement of approximately 17 dB. The ENOB of the TIADC is enhanced from 13.06 bits to 15.93 bits. Moreover, this moment, the Walden figure of merit (FOM) is 100.44 fJ/conversion-steps with the system running at 64 MHz (Ref. [30]).

The situation of SFDR and SNDR versus normalized input frequency is illustrated in Figure 7a,b. It can be found that the SFDR and SNDR before calibration and after calibration decrease with the input frequency increment. The reason is the impact of the sampling time mismatch increases with the input frequency increment, which makes the proposed calibration technique have the best calibration effect for low-frequency inputs.

3.3. Comparison with Other Work

The characteristics of this calibration technique and several other TIADC calibration techniques are compared in

Table 2. Main characteristics parameters: a summary.

Characteristics	Ref. [21]	Ref. [31]	Ref. [32]	Ref. [33]	Ref. [22]	This Work
All digital	no	yes	yes	yes	yes	yes
Mismatch type	timing	timing	offset, gain and timing	timing	offset, gain, timing and bandwidth	offset, gain and timing
Add ref. channel	no	no	yes	no	no	no
M (# of channels)	4	4	4	8	2	4
Wide freq. range	yes	yes	no	yes	yes	yes
Resolution (bit)	8	11	12	10	14	18

. Compared with other calibration techniques, the proposed work can be used for offset, gain and sampling time mismatch without using the additional reference channel. The proposed work also has the advantages of being all digital and used in the calibration for high-resolution (16-bit, even 18-bit) TIADCs, although the calibration effect of high-frequency input is relatively poor.

3.4. Hardware Validation

Here, the hardware implementation of the calibration algorithm based on GA optimization is designed in Vivado. To implement the algorithm on the hardware, the key circuits of the algorithm are finished and converted into hardware description language (HDL). In this section, the implementation results of the synthesis and FPGA calibration are described.

The HDL design is synthesized to a gate-level netlist using the Vivado synthesis tool. As shown in

Table 3. FPGA synthesis results.

Family	Virtex VII
Device	xc7vx485tffg1157-1
LUT	30480/303600 (10%)
LUTRAM	13768/130800 (11%)
Flip-Flop	30576/607200 (5%)
DSP	516/2800 (18%)

, the Xilinx Virtex VII FPGA chip xc7vx485tffg1157-1 is used to validate the algorithm. The synthesized results exhibit that the design consumes only a few percentages of the hardware resources in the FPGA chip.

Figure 8a,b show the FPGA verification results of the proposed calibration technique. Here, the input frequency $f_{in}$ is 5 MHz, and the clock frequency is 64 MHz. The offset, gain and timing mismatches are the same as those of the MATLAB simulation conditions. The results indicate that offset and gain mismatch spurs are removed completely and spurs due to timing mismatch are reduced dramatically. The SFDR is enhanced from 10.51 dB to 89.18 dB and the SNDR is enhanced from 6.11 dB to 82.66 dB. The effectiveness of the proposed TIADC calibration technique is validated by these experimental results.

4. Conclusions

An efficient all-digital calibration method based on genetic algorithm optimization which can detect and correct the offset, the gain and the timing mismatch in an M-channel TIADC system is proposed in this paper. By a sine-fit-based estimation algorithm, the mismatch errors are estimated, and the optimized mismatch errors are detected by the genetic algorithm. The calibration method is realized by the derived algorithm and a proposed fractional delay filter based on Farrow structure. The hardware implementation of the proposed algorithm is validated on the FPGA. The final results show that only a few FPGA hardware resources are used. The validation results show that this calibration technique is effective in reducing the time skew mismatch errors and improving the SFDRs/SNDRs of TIADCs. The proposed technique is also effective for the calibration of high-resolution TIADCs.