A Design Methodology of High-Efficiency Dimmable Current Sink for Current-Regulated Drivers

Abstract

This paper proposes a high-efficiency and dimmable current sink topology along with a design methodology for low node processes. The design methodology is demonstrated using a boost-based WLED driver application. In this work, the focus is on current regulation rather than voltage regulation. Therefore, the proposed topology exploits a smaller and faster NMOS pass device, replacing the conventional PMOS-based LDO arrangement. An amplifier-boosted pass-transistor current sink topology combined with a 5-bit programmable degenerated source resistor is being utilized for high-efficiency and brightness control. The realized WLED driver validates the proposed topology and the design methodology utilizing 40 nm CMOS TSMC technology. The design takes advantage of the programmability of the resistor to enhance the system’s power efficiency. This programmable resistor enables dimmability via current segmentation with a 1 mA step for a total of 25 mA. For a 500 mV voltage ripple at the DC-DC converter output driving 6 WLEDs with a 3.2 V forward voltage drop each, a worst-case current ripple of 200 µA and simulated efficiency of 97.6% is achieved for optimum pass-transistor size.

1. Introduction

LED-based systems such as smartphones, TVs and other consumer electronic applications are becoming very popular. These systems require high efficiency and accurate brightness control. Thus, current drivers are ubiquitous. With the increase in performance requirements, namely, efficiency, current accuracy and dimmability, which are needed in many applications, an optimized current sink driver solution is vital [1,2,3,4]. Modern IC chips are rich with digital content favoring lower node processes [5,6]. Moreover, lower node processes yield both lower area and power loss. However, designing a current sink driver using a lower node process is challenging due to the lower output impedance of the MOS device, i.e., $r_o$ [7,8]. Due to the popularity of the current sink, a systematic, scalable and easy-to-follow design methodology is needed [9,10,11,12,13,14].

Figure 1 depicts a typical application of a current sink driver as part of an LED driver. Here the current sink driver ensures that the desired current level passes through the LED string [15,16]. The DC-DC converter produces an output voltage that is suitable for the load from a given input voltage. Due to the switching nature of the converter, a ripple voltage superimposed over a regulated output average voltage is produced. Consequently, the LED current is being affected by this ripple resulting in a ripple current that passes through the LEDs. A simple current sink driver could be implemented using a sensing resistor [17], as shown in Figure 2. In this topology, the resulting LED current is prone to ripple in the output voltage, i.e., $\Delta I_{LED}=\Delta V_{out}/R_{sense}$ [18]. Furthermore, the varying forward voltage of the LEDs leads to an imbalanced current among strings in multi-string arrangements, even in an equal number of LEDs per string [19].

Therefore, a more robust current sink driver topology is needed to suppress the current ripple effect on the sensing point. In the solution proposed in [20], shown in Figure 3, an error amplifier and PMOS pass-transistor are introduced between the DC-DC converter output and the LED string. The error amplifier forces the LED current to be insensitive to a total forward voltage drop across the LED in any given string. This is achieved by forcing the voltage over the sensing resistor to equal a reference $V_{x\left(ref\right)}$. The PMOS pass device’s presence between the DC-DC output and the LED string output voltage reduces the voltage ripple at the output node, hence, the resulting current ripple. This topology requires a high voltage amplifier and PMOS device, deeming it impractical to ingrate on the same chip.

The circuit in Figure 4 is an alternative option for realizing a current sink [21]. This topology features similar advantages as the previous solution in overcoming the LEDs’ forward voltage variation and minimizing the current ripple. Here, the current is directly regulated using an NMOS instead of a PMOS pass-transistor. Thus, making it more suitable for current-sensitive devices such as LED with current-dependent brightness. Moreover, the low voltage error amplifier and the NMOS device might easily be integrated on the same chip.

Table 1. Strengths and weaknesses of the reviewed current sink driver topologies.

Topology	Size (1)	Efficiency (1)	Integrability	Complexity	Sensitivity to Current Ripple (2)
Sensing resistor current sink driver	Small	Low	Hard	Simple	Very sensitive
PMOS-based current sink driver	Large	Moderate	Very hard	Complex	Sensitive
NMOS-based current sink driver	Medium	High	Easy	Moderate	Less sensitive

⁽¹⁾ for the same $\Delta I_{LED}$ requirement. ⁽²⁾ absolute accuracy.

summarizes the strengths and weaknesses of the reviewed relevant art mentioned above. The current sink driver size, sensitivity to ripple, easiness of integration and system complexity are the metrics used to compare the cited topologies. This comparison favors the NMOS-device-based topology based on the chosen critical metrics listed in the summary table. This topology is modified in this work to achieve a programmable current sink driver by utilizing a programmable resistor to enable current dimmability and enhance system efficiency. This work proposes a design methodology for this solution and utilizes a WLED driver application example for demonstration. The proposed methodology guides and assists the designer to reach an acceptable solution given different power efficiency, size and gain-bandwidth-product (GBP) conflicting factors. This methodology applies to any process node size and helps reduce product design life cycle.

This paper is organized as follows: the programmable resistor current sink topology is described in Section 2. The design methodology and an application example are discussed in Section 3. Finally, concluding remarks are provided in Section 4.

2. Programmable Resistor Current Sink Topology

The proposed topology with a programmable resistor bank is depicted in Figure 5. The circuit consists of an N number of LED strings; each has an amplifier-boosted pass-transistor (M1) and a digitally-programmable integrated resistor. The $V_{out}$ represents the output voltage of the DC-DC converter. There are two options to realize current dimmability/brightness control; programmable $V_{ref}$ or programmable resistor. This work uses a 5-bit programmable resistor bank to control the LED current with 25 segments of a 1 mA resolution step. Note that the $V_{ref}$ is set to a constant voltage value of 150 mV [22,23]. Here, the efficiency improvement is realized by a programmable resistor instead of reference voltage programmability.

The current sink’s power loss comprises three components; the boosting amplifier quiescent current, pass-transistor device, and sensing resistor. The boosting amplifier power loss can be ignored as its quiescent current is much lower than the string’s current. The power consumption in the pass-transistor is given as:

$$P_{loss\left(n-MOS\right)}=V_{DS}\times I_{LED}$$

(1)

Here the $V_{DS}$ is proportional to the current passing through the string and inversely proportional to the device aspect ratio (i.e., W/L). Therefore, in dimmable designs, the maximum LED current dictates the device’s size based on the power consumption budget. This portion of power loss is comparable in both designs: fixed sensing resistor and programmable resistor. The power loss in the sensing resistor is given by:

$$P_{loss\left(Rsens\right)}=V_{Rsens}\times I_{LED}$$

(2)

If the $I_{LED}$ is controlled by changing the $V_{ref}$, the power loss will vary linearly with $I_{LED}$ because the boosting amplifier forces $V_{Rsens}$ to equal $V_{ref}$ However, in the case where $I_{LED}$ is controlled by changing the sensing-resistor value, the power loss in the sensing resistor will be independent of $I_{LED}$ value and only dependent on the preset reference voltage level. So, for designs that require dimmability, the latter solution is more power-efficient. The previous observation is illustrated in Figure 6.

It is worth mentioning that there is a trade-off between efficiency and accuracy. Increasing the drain-to-source voltage ($V_{DS}$), decreases the transistor’s output resistance ($r_o$) and, consequently, degrades the current accuracy for a specific channel length of the pass-transistor. It is easier to design the boosting amplifier for a fixed reference voltage rather than a variable value, as the former requires a lower input common-mode range for an identical gain target [24].

Due to the finite bandwidth of the DC-DC stage controller, $V_{out}$ contains a ripple ($\Delta V_o$) in addition to the DC component. This ripple is dominated by a fundamental frequency that matches the converter’s switching frequency ($f_{sw}$). An ideal current sink driver should be able to force a ripple-free LED DC current, regardless of the voltage ripple. Practically, $\Delta V_o$ affects the current components by imposing current ripple $\Delta I$ due to the finite output resistance of the current driver. The output resistance of the proposed circuit is approximated by:

$$R_{out}=A_i·\left[A+1\right]·R_{sens}+R_{sens}+r_o\approx A_i·\left[A+1\right]·R_{sens}$$

(3)

where $A_i$ is the intrinsic gain of the pass-transistor $M_1$ (expressed as: $g_m\times r_o$), $r_o$ is the small-signal AC resistance of the pass-transistor operating in saturation and A is the boosting amplifier open-loop gain.

The higher the $R_{out}$ of the current sink, the higher the current accuracy. This can be achieved by increasing the intrinsic gain and/or the boosting amplifier gain. For a fixed device’s current and channel length, maximizing $A_i$ would require increasing device width (W) or the $V_{DS}$. The latter option is not selected since it leads to higher power dissipation. Consequently, the optimal device width is chosen to achieve the desired $A_i$ value. However, the boosting amplifier DC gain (A) is limited by the maximum achievable GBP. A maximum gain can be achieved for a specific maximum bandwidth, which is dictated by the switching frequency. The gain is determined by the GBP requirement and the bandwidth.

3. Design Methodology and an Application Example Simulation

The proposed design methodology is introduced in this section and illustrated via a WLED driver example simulation.

3.1. Design Methodology

The flowchart depicted in Figure 7 summarizes the design steps of the proposed circuit. Adhering to this methodology helps to achieve high $R_{out}$, optimal size and power dissipation for a given GBP of the boosting amplifier.

The maximum output voltage ripple of the DC-DC converter and the ripple current design target decide the minimum required $R_{out}$ of the current driver. The minimum needed $R_{out}$ is calculated at the maximum LED string current ($I_{LED\left(MAX\right)}$). The design starts with choosing the channel length L that is twice the minimum process node $L_{min}$.

The corresponding sensing resistance value ($R_{sens}=V_{ref}/I_{LED\left(MAX\right)}$) can now be selected. The boosting amplifier DC gain (A) can be determined depending on the switching frequency of the DC-DC converter and the amplifier’s GBP. Having determined A and $R_{sens}$, the approximate intrinsic gain value of the pass-transistor ($A_i$) can be estimated from Equation (3). Depending on the power budget target, the optimum drain-source voltage ($V_{DSopti}$) in step 5 can be calculated using the following Equation (4)

$$P_{loss\left(MAX\right)}=I_{LED\left(MAX\right)}\left[V_{DSopti}+V_{Rsens}+\frac{\Delta V_{out}}{2}\right]$$

(4)

A family of curves relating the intrinsic gain $A_i$ and the size of the pass-transistor versus $V_{DS}$ are developed at different δ, where δ is the difference between the $V_{GS}$ and $V_{DS},$ as shown in Figure 8. These curves are developed by sweeping $V_{DS}$ and adjusting the device size using the $g_m/I_D$ method while keeping the device’s drain current constant $I_{LED\left(MAX\right)}$ [25].

A suitable value of δ that satisfies $V_{DSopti}$ and $A_i$ is found using the developed family curves in step 6. If the appropriate intrinsic gain is not met, a new longer device’s channel should be selected then the procedure repeats. For the selected $A_i$ value and using δ and $V_{DSopti}$ determined previously, the transistor width W is extracted from the curves in step 7. This chart is developed by sweeping $V_{DS}$ at different δ, keeping a constant device current using the $g_m/I_D$ method. If the picked device size is prohibitively large, the procedure returns to step 1 and increments the channel length. A detailed description of the design procedure of the boosting amplifier is found in [26,27]. This design methodology includes the most critical design parameters that benefit system-level metrics (i.e., efficiency, size and controllability). Furthermore, this methodology might seamlessly apply to any system-level converter architecture encompassing a current sink driver.

3.2. WLED Design Example

This section illustrates the design methodology using a WLED design example depicted in Figure 9. Picking this popular system that uses a current sink driver solution highlights the system-level need for a rubout design methodology. Figure 9 shows a boost converter followed by a WLED string and current sink driver. The following design example focuses on the current sink driver part to validate the proposed solution functionality and verify the design methodology. The chosen design specifications are listed in

Table 2. Design specification of the WLED example.

Parameter	Values
Input voltage (a)	3.2–4.2 V
WLED string current	1–25 mA (dimmable)
Current resolution	1 mA
Current ripple	<1%
String arrangement	6 WLEDs
WLED forward voltage drop	3.2 V
Output voltage ripple	<2.5%
Op-amp quiescent current	100 µA
Switching frequency $\left(f_{sw}\right)$	1 MHz
GBP	100 MHz
Efficiency (of current driver)	>97%

^(a) battery level.

. This data is based on the work presented in [8,19]. The TSMC 40 nm CMOS technology is utilized in the ADS CAD tool to implement and simulate the design.

According to the depicted design methodology in Figure 7 and DC-DC converter parameters, the minimum output resistance of the current driver that satisfies the current ripple for the given output voltage ripple of the converter is calculated as:

$$R_{out}=\frac{\Delta V}{\Delta I}=\frac{2.5\%\ast 20}{1\%\ast 25\mathrm{m}}=2.5 \mathrm{k}\mathsf{\Omega }$$

(5)

Knowing that the string output voltage is the voltage drop across 6 WLEDs and the voltage drop across the current sink driver, approximated here by 600 mV, then;

$$V_{out}=6\times 3.2 \mathrm{V}+600 \mathrm{mV} \approx 20 \mathrm{V}$$

(6)

The boosting amplifier open-loop gain is determined by the target GBP and the switching frequency:

$$A=\frac{GBP}{F_{sw}}=\frac{100 \mathrm{MHz}}{1 \mathrm{MHz}}=100$$

(7)

The minimum sensing resistance value must be determined to calculate the required intrinsic gain. A low voltage of 150 mV is selected as a reference voltage ($V_{ref}$), leading to a 6 Ω minimum sensing resistor value at $I_{LEDMax}$. Consequently, the intrinsic gain value according to Equation (3) should be higher than:

$$A_i\ge \frac{R_{Out}}{\left[\left(A+1\right)\times R_{sens}\right]}=\frac{2.5 \mathrm{k}}{\left[\left(101\times 6\right)\right]}=4.125$$

(8)

Following the efficiency requirement, the voltage drop across the current sink driver is determined as:

$$V_x=\left(1-0.97\right)\times \frac{V_{out}\times I_{LEDMax}}{I_{LEDMax}}=600 \mathrm{mV}$$

(9)

The $V_{DSopti}$ as illustrated in Figure 5, can be estimated by:

$$V_{DSopti}=V_x-\frac{\Delta V}{2}+V_{ref}=600 \mathrm{mV}-250 \mathrm{mV}-150 \mathrm{mV}=200 \mathrm{mV}$$

(10)

Figure 10 and Figure 11 show the $A_i$ and transistor’s size versus $V_{DS}$ for different δ at a fixed current of 25 mA, respectively. These curves are developed for a channel length of 80 nm. The target $A_i$ value at the optimum $V_{DS}$ found in Equation (10) can be achieved at two points (δ = 450 mV and 400 mV). Here, the optimum δ that satisfies both the intrinsic gain and minimizes the pass-transistor size is 450 mV. The device’s size is determined using Figure 11 to be W = 405 µm. It is noteworthy that the device’s size decreases with $V_{DS}$. For higher efficiency, a lower drain-source voltage is preferred. However, the advantage in the size reduction diminishes as the $V_{DS}$ increases. Therefore, there is a design trade-off between the system efficiency and the device’s area.

3.3. Simulation Results

This section presents the simulation results for the demonstration example based on the proposed design methodology using the ADS CAD tool. Figure 12 shows different string currents, with ripple zoomed, at three levels. Note that the LED current has 25 segments with 1 mA segment step each. Figure 12 clearly shows that the worst-case ripple value is at the highest current level (25 mA) as anticipated during the design process. The ΔI was 206 µA for the worst case. The ripple value drops to 2.3 µA at the lowest current level of 1 mA.

The voltage waveform at the pass-transistor drain, $v_x\left(t\right)$, and the sensing resistor voltage are shown in Figure 13. The average value of $V_x$ is around 480 mV compared to 600 mV previously calculated. The reason for this deviation is the optimization undertaken to reduce the power dissipation (efficiency enhancement) while keeping the current ripple ΔI within the level of the design specifications. The resulting power dissipation is reduced from theoretically calculated ~15 mW to 12 mW at the maximum current of 25 mA. This reduces current sink driver losses by 20% and enhances the efficiency to ~97.6%. In a physical implementation, the nonidealities of the actual hardware components might compromise this simulated efficiency result.

The voltage waveform across the programmable resistor $V_{Rsens}\left(t\right)$ is also displayed in Figure 13. Its value is smaller than the calculated value of 150 mV due to the finite gain of the boosting amplifier (a systematic error). Note that the ripple on this waveform is negligible compared to the ripple in the drain voltage waveform $v_x\left(t\right)$.

4. Conclusions

This paper presented a high-efficiency current sink driver and its design methodology for current regulating purposes. Unlike the conventional methods, this topology regulates the current directly using an NMOS pass-transistor in place of PMOS. Thus, the proposed solution is suitable for current-sensitive devices such as LEDs with current-dependent brightness. This makes the topology more suitable for any DC-DC converter-driven application that suffers from output voltage ripple. Furthermore, the proposed solution comprises an integrated programmable resistor bank that enables digital control with a user-defined current resolution step. Using the programmable resistor for dimming proved superior to the variable reference method. In addition, a systematic design methodology based on the $g_m/I_D$ method is proposed. This design methodology leads to a set of candidate solutions for the pass-transistor size at specified efficiency and GBP design parameters. The proposed methodology can be applied to any process node, including 40 nm CMOS technology. A boost-based WLED driver application example is utilized to validate the proposed current sink driver topology and its design methodology. In the design example, a 1 mA resolution step for a total of 25 mA is implemented by the programmable resistor bank to enable the dimmability of WLEDs. For a 500 mV voltage ripple at the DC-DC converter output driving 6 WLEDs, with a 3.2 V forward voltage drop each, a worst-case current ripple of 200 µA and 97.6% efficiency is achieved for an optimal pass-transistor size. It is noteworthy that the proposed current sink driver can be applied to more sophisticated systems and topologies, including multi-string WLED designs and any variant of DC-DC converters.