1. Introduction
The operational transconductance amplifier (OTA) is a key element for analog CMOS integrated circuit (IC) design as it is virtually present in any monolithic electronic system that bases its performance on accurate high-gain closed-loop configurations. However, designing OTAs with acceptable performance is becoming increasingly difficult in modern CMOS technologies. In fact, nanoscale nodes require supply voltages of less than 1 V [
1,
2,
3,
4,
5,
6]. Furthermore, extending the autonomy of battery-powered or even harvested-powered devices places severe constraints on the current consumption, and this is particularly detrimental to analog and mixed-signal implementations.
The design approaches that are usually exploited to implement an OTA with stringent low-power and low-voltage constraints are based on the adoption of bulk-driven (body-driven) transistors [
7,
8,
9,
10,
11,
12,
13,
14], on weak inversion operation [
15,
16,
17,
18,
19,
20,
21,
22], or a combination of both of them [
23,
24,
25,
26,
27,
28,
29,
30,
31,
32,
33].
The body-driven approach is especially suited in applications where the supply voltage is comparable or even lower than the transistor threshold voltage and a wide input common-mode range (ideally rail-to-rail) is required at the same time [
2,
9]. However, the main drawback of the bulk-driven approach is that the bulk transconductance is about 60 to 90% lower than the gate transconductance for equal bias current and transistor dimensions, leading to both poor DC gain and gain-bandwidth performance. At the cost of increased area occupation, the adoption of multistage OTAs can overcome the former issue of DC gain [
11,
29,
31] but the gain-bandwidth penalty can be overcome only by increasing the input stage transconductance and, in turn, the quiescent current of the input stage. As an interesting alternative, the input equivalent transconductance of a bulk-driven differential pair can be increased by exploiting partial positive feedback techniques [
10,
12,
34,
35].
Following the latter approach, we describe in this paper a bulk-driven single-stage OTA whose topology is a modified version of the one developed in [
4]. The solution boosts the bulk transconductance of the differential pair to a level similar to or even higher than that of a conventional gate-driven stage [
36]. Compared to the solution in [
12], the proposed one is characterized by some distinctive features. Namely, subthreshold-biased MOS transistors are exploited to meet ultra-low-voltage supply requirements, which are further reduced by eliminating the tail current generator in the differential pair. Moreover, the pseudo-differential behavior caused by the elimination of the tail generator is avoided, approaching a truly differential OTA performance. These strategies, together with an optimized design, have resulted in a single-stage OTA with excellent performance, validated through experimental measurements on prototypes designed in standard 180-nm CMOS technology.
The paper is organized as follows.
Section 2 describes the principle of operation of the circuit and related derivation of main design equations.
Section 3 reports the validation of the OTA through experimental measurements and the comparison with other solutions in the literature, showing a significant advance of the state of the art. Finally, some concluding remarks are offered in
Section 4.
2. The Proposed Amplifier
The schematic diagram of the proposed single-stage OTA is shown in
Figure 1. Where not explicitly drawn, the bulk terminal of each transistor is assumed to be connected to its source. The circuit is made up of the bulk-driven non-tailed differential pair M
1–M
2 loaded by current mirror M
3–M
4 and M
5–M
6. The additional current mirror M
9–M
10 implements differential to single-ended conversion. The bias current in M
1 and M
2 is set through the diode-connected transistor M
0, which generates voltage
VB to be applied to the gates of M
1–M
2. The bulk terminal of M
0 is biased by the voltage divider
R1–
R2, which is basically the analog ground i.e., the quiescent input voltage of the pair. More specifically, M
0 and M
1 (M
2) act as a current mirror provided that
Vin− =
Vin+ = (
R1VSS +
R2VDD)/(
R1 +
R2), and in this case we get
ID1,2 =
IBias(
W/
L)
1,2/(
W/
L)
0.
Like the solution proposed in [
12,
36], an additional cross-coupled load made up of transistors M
7 and M
8 is exploited to produce a local positive feedback that boosts the equivalent differential transconductance,
Gm. Indeed, assuming (W/L)
9 = (W/L)
10, i.e., unitary current mirror M
9–M
10, and defining parameters
α and
β as
and
straightforward small-signal analysis gives
where
gmb1,2 is the bulk transconductance of M
1 and M
2.
It can be noted that, because of the absence of the tail current generator, M1–M2 is a pseudo-differential pair. However, thanks to the action of M7 and M8, the whole OTA provides a quasi-differential behavior. Indeed, Equation (3a,b) show that id3 and id5 depend on a α-weighted difference between vin+ and vin−, with ideal truly differential behavior achieved for α approaching 1.
Assuming a balanced differential input, i.e.,
vin+ =
vd/2 and
vin− = −
vd/2, and no mismatches in the OTA current mirrors, the differential-mode transconductance,
Gm, is found to be
where
iout is the OTA short-circuit output current.
It is apparent that the differential-mode transconductance can be significantly increased by choosing suitable values of the transistor aspect ratios in (1) and (2). Of course, parameter α must be lower than 1 to ensure that the magnitude of the local positive feedback is kept below unity, to prevent the amplifier from becoming a latch. Although values very close to 1 can, in principle, generate a very large
Gm increase, it is advisable to set
α less than 0.9 to have a sufficient safety margin against process mismatches [
34,
35], while achieving a quite good differential behavior.
The complete OTA open loop transfer function, taking into account the parasitic capacitances and capacitive load, is expressed by
where
ro is the OTA output resistance equal to
rd10//
rd6,
is the sum of the load capacitance and the parasitic capacitances and
Ci,
I = 1, 2, 3, represents the total parasitic capacitance at nodes 1, 2 and 3. Assuming
CL is much higher than the parasitic capacitances, the high-frequency poles and zeros can be neglected and the rightmost approximation in (5) holds. As usual, the gain-bandwidth product is therefore given by
From Equation (3a,b) we can also evaluate the OTA transconductance under common-mode input signal (i.e.,
vin+ =
vin− =
vcm). Ideally, in this case, the symmetry of the topology would nullify the common-mode transconductance,
Gm,cm, as can be easily seen if we take the difference of
id3 and
id5. To have a more realistic result, we should consider the mismatches between the bulk transconductances of M
1 and M
2 and parameter
α, by defining
After some algebraic manipulations we get
where in the approximation we neglected the term
in the denominator because it is much lower than 1.
It is seen that the common-mode transconductance is proportional to the sum of the relative tolerances of gmb1,2 and parameter α. Additional degradation is also caused by mismatches in the β parameter and in the current mirror gain M9–M10, here neglected for simplicity. All these errors can be relevant due to the simple current mirror topologies adopted and can be counteracted by choosing large MOSFET channel lengths and careful layout.
By taking the ratio of (4) and (8) one can evaluate the common-mode rejection ratio (CMRR) which, as a result, is exclusively dependent on the last factor between brackets in (8).
3. Results and Comparison
The circuit in
Figure 1 was designed and fabricated using a standard 180-nm CMOS process supplied by STMicroelectronics. Note that like all the recent sub-350-nm processes, the adopted technology allows the use of triple-well NMOS transistors, thus allowing independent control of the bulk terminals. The circuit layout and the chip microphotograph are shown in
Figure 2. The occupied area is 866.25 μm
2.
The nominal supply voltage and bias current is set equal to 400 mV and 5 nA, respectively, forcing all the transistors to work in the subthreshold region. The total nominal DC current consumption is equal to 81.35 nA. Note that with such value of VDD the potential forward biasing of the bulk-source pn junction is inherently avoided.
According to the adopted transistor dimensions summarized in
Table 1, parameters
α and
β are nominally equal to 0.83 and 15, respectively. Consequently, the bulk transconductance of M
1 and M
2, equal to 4.71 μA/V, is boosted by about 88 times, yielding from (6) a theoretical
GBW equal to about 5 kHz for a nominal load capacitance of 150 pF.
The measured open-loop Bode plots (magnitude and phase) of a representative OTA sample is depicted in
Figure 3 while
Figure 4 shows the measured gain for all the samples superimposed to the simulated one.
Table 2 summarizes the measured main performance metrics averaged over the ten samples. The variability of the parameters is evaluated through the relative standard deviation which is lower than about 30% in all cases.
Figure 5 shows the transient response of the same sample in unity-gain feedback configuration for
CL equal to 30 pF (loading capacitance equal to 30 pF represents the total load due to the package, the oscilloscope probe, and the PCB), 150 pF and 1 nF, confirming that the approximated single-pole transfer function in (5) well describes the OTA behavior.
The robustness of the OTA over process, temperature and mismatch variations is assessed through corner simulations and Monte Carlo analysis. Results are summarized in
Table 3,
Table 4,
Table 5 and
Table 6 where the main amplifier specifications are simulated over three different temperatures (namely −10 °C, 27 °C and 85 °C) in all transistor corners, showing that the amplifier is stable in all conditions. Moreover, Monte Carlo simulation results over 100 runs confirm the robustness of the OTA, the relative standard deviation being lower than 25% in all cases.
Finally, the robustness over supply voltage variations is assessed in
Figure 6 where the simulated step response in unity-gain configuration is reported for different capacitive load conditions and ±10% voltage variations.
Table 6 compares the proposed OTA with other experimentally tested solutions in the literature working with a supply voltage lower than 1 V. In order to assess the trade-off between speed performance and total bias current,
IT, (and, indirectly, power consumption) for a given load, we adopt in
Table 3 the traditional figures of merit.
where
SR is the average slew rate. To take into account also the area occupation, two additional figures of merit are adopted:
It is apparent that the proposed solution exhibits the best small-signal performance with a 4.77 X and 17.28 X improvement of
IFOMS and
IFOMAS over the best solutions in
Table 3. Similar conclusions apply to the large-signal performance, where the improvement of
IFOML and
IFOMAL is equal to 2.16 X and 24.49 X. Note, however, that the gain of the proposed solution is the lowest one, being a single-stage OTA.