On Unstable Spatial Modes and Patterns in Cellular and Graph Neural Circuits

Round 1

Reviewer 1 Report

This paper discussed the dynamics and principle of pattern formation in a couple of classes of cellular and graph neural circuits, emphasizing the existence of unstable spatial modes. The paper is well-structured. However, a minor revision is needed before it is considered to be accepted:

(1) In Figure 1, the representations of a) and b) are inconsistent with those in the caption, should they be unified?

(2) What variables are represented by the vertical coordinates of the model in Figure 3, which are not explained in the figure.

(3) Some parameters in the theoretical derivation of the model are not explained exactly what they represent, and it is recommended to cite some representative references, such as Polymer, 2015, 74(15), 182-192，Syst. Control Lett., 2017, 101, 21-27, Automatica, 2017, 80, 10-16, etc.

(4) The paper needs more improvement in language, for example, the double quotation mark in line 273 are incorrectly written.

(5) Some abbreviations first appearing were not explained, such as CMOS in the page 7, line 295.

(6) In part 7, authors described how initial conditions determine the dynamics of spatial patterns, are there any other influencing factors besides initial conditions?

(7) Please check carefully and revise the format of the reference, for example, the double quotation marks are incorrectly written in references 2 and 3.

Comments for author File: Comments.pdf

Author Response

Reviewer 1

Thank you very much for your comments and observations.

(1) In Figure 1, the representations of a) and b) are inconsistent with those in the caption, should they be unified?

I introduced the text ”and nonlinear resistor characteristic” at line 49

(2) What variables are represented by the vertical coordinates of the model in Figure 3, which are not explained in the figure.

I introduced the text “for the u voltages in Fig.1a” at line 99.

(3) Some parameters in the theoretical derivation of the model are not explained exactly what they represent, and it is recommended to cite some representative references, such as Polymer, 2015, 74(15), 182-192，Syst. Control Lett., 2017, 101, 21-27, Automatica, 2017, 80, 10-16, etc.

You are right that some parameters are not (sufficiently) explained – however, the aim of the paper is to present in a unifying manner results on patterns in various architectures which were described in detail in the cited references and, moreover, to show a new application of pattern formation theory based on unstable modes.

(4) The paper needs more improvement in language, for example, the double quotation mark in line 273 are incorrectly written.

Replaced with “polarity”.  I have made efforts to be more careful with English.

(5) Some abbreviations first appearing were not explained, such as CMOS in the page 7, line 295.

Added: CMOS transistor (active) one.

(6) In part 7, authors described how initial conditions determine the dynamics of spatial patterns, are there any other influencing factors besides initial conditions?

The idea of the paper is to stress how unstable modes produce patterns. Indeed, the shape of the transient depends of the circuits parameters and perhaps the nonlinearities; I did not considered as being relevant the duration of the transient but only the final pattern. Moreover, I wanted to stress that, at least in principle, the final patterns crucially depend on the sign of the unstable mode in the initial condition for one unstable mode no matter how small is it.

(7) Please check carefully and revise the format of the reference, for example, the double quotation marks are incorrectly written in references 2 and 3.

Thank you for your observation. I made the necessary changes.

Reviewer 2 Report

There are some factors the authors need to consider:

1.      Could you use alphabetical sequence to array the key words.

2.      All the figures are not clear. Could you use better resolution figures?

3.      Could you mark the transistor size in Fig. 8?

4.      On line 333, which value is V1, V2, V3 and V4 in Fig. 8?

5.      On line 313, it shows the capacitor is 20pF, while the capacitor in Fig. 7 is 10pF.

6.      In Fig. 8, which is V1, V2, V3 and V4, corresponding to Fig. 7

7.      Could you use a table to summarize all simulation cases?

Author Response

Reviewer 2

Thank you very much for your comments and observations.

1. Could you use alphabetical sequence to array the key words.

Done.

 

2. All the figures are not clear. Could you use better resolution figures?

Most figures have been cropped from Cadence simulations. I hope that, if the paper will be accepted, during the editing process, some improvements could be done.

3. Could you mark the transistor size in Fig. 8?

I mentioned at line 332 All transistor sizes were l=1.80u, w=0.5u (I have used a large l to ensure better linearity)

4. On line 333, which value is V1, V2, V3 and V4 in Fig. 8?

The schematics in Fig. 8 are for the floating positive and negative resistances in Fig. 7. In other words, the resistances in Fig. 7 were replaced by positive and negative active realizations shown in Fig. 8.

To be clearer, I have made computer simulations with the same architecture in Fig. 7 once with standard resistances and second with the same resistances replaced by active ones shown, for positive and negative case in Fig. 8.

I mentioned at line 329 that: The node numbering is the same for both realizations, i.e., that of Fig. 7.

5. On line 313, it shows the capacitor is 20pF, while the capacitor in Fig. 7 is 10pF.

Sorry for the mistake and shame on me! I have corrected to 10 pF.

6. In Fig. 8, which is V1, V2, V3 and V4, corresponding to Fig. 7

Please see the answer to Observation 4.

7. Could you use a table to summarize all simulation cases?

The aim of the simulations were on the one hand to show several cases to confirm expected behavior and, on the other hand that the behavior is, at least in certain conditions, conserved for active realizations of the positive and negative resistances. In other words, the last part of the papers is only a kind of proof of concept.

Reviewer 3 Report

The manuscript should be carefully reviewed, clarifications and additions are necessary.

The introduction should briefly place the study in a broad context and highlight why it is important. The current state of the research field should be carefully reviewed. Almost 50% (10/21 references) of the references are self-cited. The author should introduce short sentences to explain the relevance of the cited papers with respect to the context in which they are cited.

Lines 40, 260, 273, 294, 296, 301, 328, 402, 404: “… we briefly …”; “We count …”; “… we are interested …”; “… we present … “; “We adopted …”; “… we have …”; “… we will present …”; “We have presented …”; “We illustrated …”; Does the paper have more than one author?

The quality of the figures should be improved.

The research results are not presented clearly enough.

The conclusions and the abstract should be rewritten and more focused on the results obtained and not just general discussion. You should use values to justify statements from conclusions.

Author Response

Reviewer 3

Thank you very much for your comments and observations. And apologies for my carelessness you mentioned.

The manuscript should be carefully reviewed, clarifications and additions are necessary.

The introduction should briefly place the study in a broad context and highlight why it is important. The current state of the research field should be carefully reviewed. Almost 50% (10/21 references) of the references are self-cited. The author should introduce short sentences to explain the relevance of the cited papers with respect to the context in which they are cited.

 

I have made a thorough review; the changes being marked using “track changes” The following texts have been added in the introduction.

 

Line 37 …and conditions for pattern formation have been derived.

 

Line 41  Conditions for pattern formation due to unstable spatial modes have been determined as well using the mechanism of mode decoupling described in [7]

 

Line 45 Since the equations are described by symmetric matrices, mode decoupling is possible and unstable modes can be put in evidence. The main interest in dynamics leading to pattern formation has been initially the need of modelling various phenomena often associated to the so-called symmetry breaking, i.e., getting patterns in homogeneous architectures from random initial conditions seemingly with no applications in electronics. In this paper the above architectures able to produce patterns as a result of the existence of unstable spatial modes are briefly revised, and a new application called spatial comparator is presented and illustrated with simulations.

 

Lines 40, 260, 273, 294, 296, 301, 328, 402, 404: “… we briefly …”; “We count …”; “… we are interested …”; “… we present … “; “We adopted …”; “… we have …”; “… we will present …”; “We have presented …”; “We illustrated …”; Does the paper have more than one author?

 

Sorry! It was my definite mistake to have included so many inappropriate expressions. Indeed, there is only one author!  I have reviewed the text and made the necessary corrections.

The quality of the figures should be improved.

Most figures were cropped from Cadence simulations. I hope, if the paper will be accepted, that they could be improved.

The research results are not presented clearly enough. The conclusions and the abstract should be rewritten and more focused on the results obtained and not just general discussion. You should use values to justify statements from conclusions.

I have made modifications (using “track changes”) in the text hoping things will be clearer. I stressed the fact that the main results is that of proposing an application inspired by the pattern formation mechanism.

The abstract is now:

The aim of this paper is to discuss several aspects regarding the dynamics and pattern formation in a couple of cellular and graph neural circuits type architectures and to propose a new application. A unifying approach for these types of neural circuits based on unstable spatial modes using the mode decoupling technique is presented. Besides, the main objective is that of showing the way the dynamics can be prescribed by speculating the relationship between the extended graph Laplacian and nodal equations of a specific architecture. Based on the above, the possibility of designing a so-called spatial comparator that can extract the sign of a prescribed spatial mode contained in a spatial signal, using unstable circuits for which that mode is associated with a right half plane eigenvalue is analyzed and illustrated with simulations in CMOS technology.

 

and the Concluding remarks are now:

 

The dynamics and principle of pattern formation in a couple of classes of cellular and graph neural circuits have been presented and discussed, emphasizing the common character of all realizations, i.e., the existence of unstable spatial modes. The way in which analytical solutions can be obtained by using the decoupling technique, based on the orthogonality of the spatial modes has been illustrated. For each case there has been briefly outlined the way the equations can be decoupled using the amplitudes of the modes as the new dynamical variables. Besides these theoretical aspects, in the last part, as a proof of concept, an example showing the possibility of identifying a “hidden” unstable mode by designing a graph neural circuit with prescribed eigenvalues and eigenvectors has been presented. Thus, it has been proved that circuits with prescribed eigenvectors and eigenvalues can be designed to detect the presence and the sign of a small unstable mode among the other stable ones. Simulations including a CMOS realization confirmed the analytical results; of course, the author is aware of the limitations due to parasitic and tolerances which might restrict the range of signal variation. However, the presented proof of concept shows how the subject of pattern formation could be associated to the design of what has been called a spatial comparator.

Round 2

Reviewer 2 Report

For the plot, the data could be exported from Cadence and plot in Matlab or Excel for better resolution. 

Viso or PPT can be used to plot the circuit schematic with high resolution.

 

Two examples of good plots can be found in

1. https://www.mdpi.com/2079-9292/10/6/736

2. https://www.mdpi.com/2079-9292/10/1/68

 

 

Author Response

Thank you very much! I made several improvements of the figures. 

Reviewer 3 Report

The author has improved the presentation of his manuscript.

However, the quality of the figures should be improved.

Author Response

Thank you very much! I made several improvements of the figures.