A Novel Autocorrelation Combined MM-CDR Time-Interleaved ADC Timing Calibration in 28 nm CMOS Technology
Round 1
Reviewer 1 Report
1- The abstract needs more interest and rewriting some paragraphs.
2- There are still some aspects that can be improved (for grammar and punctuations). Improve the technical writing of your paper, where there are several grammatical errors and spelling I think they need to be checked out.
3- The conclusion needs more efforts to elaborate the achieved results with respect to the future work,
4- The practical part is very important,
5- Future work is an important part of the conclusion.
6- A comparison table with previous studies is very important.
7- Short brief explanation has given by the authors, it's clearly research therefore the objection of the proposed method has gained.
Author Response
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Author Response File: 
Author Response.pdf
Reviewer 2 Report
To solve the TI-ADC problems of high-speed ADC receivers, which include sub-ADC timing mismatch, the authors used auto-correlation with an existing Mueller-Müller clock to calibrate it (MM-CDR). When skews are changed to +0.4 ps, +0.2 ps, -0.59 ps, and 0 ps, the ADC's SFDR and SNDR jump from 37.24 dB and 31.28 dB to 48.07 dB and 34.56 dB. Their recommended skew calibration loop is 695 m2 and 0.126 mW, lowering the size and power usage of the digital CDR loop.
1. The proposed MM-CDR TI ADC did not mention the nanometer process or technology used. What is it?
2. Moreover, the paper mentioned that it utilized an 8 GHz clock. Is there any technology that can accommodate an 8 GHz clock, especially the pads?
3. It is stated in the abstract that "area and power consumption of our proposed skew calibration loop are 695 μm2 and 0.126 mW". Could you show the floorplan and layout of the proposed system? However, it seems that the authors used only Simulink for their simulation. But, they mentioned area consumption, so an equivalent circuit in silicon is proposed. Please confirm.
4. Why is there no performance comparison with prior works?
Author Response
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Author Response File: Author Response.pdf
Reviewer 3 Report
· The abstract mentioned, “The traditional skew detection and calibration circuits consume a lot of power and area of the receiver system”. This point can be enriched with this reference, for example, E. -H. Chen, R. Yousry and C. -K. K. Yang, "Power Optimized ADC-Based Serial Link Receiver," in IEEE Journal of Solid-State Circuits, vol. 47, no. 4, pp. 938-951, April 2012, doi: 10.1109/JSSC.2012.2185356.
· Could you explain the proposed method in (Subsection 1.3 and Section 2) with a figure that describes the parameters like time deviation, error direction, etc., and the use of the Mueller-Müller method to put in context your contribution?
· Despite your cited sources in “[15-18]”, could you explain in more detail the difference in your contribution with the following published paper?
o H. Faig, S. Cohen, L. Gantz, and D. Sadot, "Low-Cost TI-ADC Timing Calibration Circuit," in Optical Fiber Communication Conference (OFC) 2020, OSA Technical Digest (Optica Publishing Group, 2020), paper Th3J.3.
https://opg.optica.org/abstract.cfm?URI=OFC-2020-Th3J.3
· How are related figure 2 and equations (1) and (3)?
· Which block in figure 3 represents your contribution?
· Skew loop in figure 3 groups with a red-line some blocks; subsequently, figure 4 represents skew loop in MM-CDR, but now it contains the decimation block that was out of the red-line in figure 3. Please clarify the figures and blocks contained.
· Could you use another letter for error-direction Ej to avoid confusion with the expected value, E letter?
· Use the same font in figures and sentences, for example, Esum1~4
· Tck is not defined but it is used in figures 5 and 6
· Check sentences like “Showing in Figure”, “we digitally synthesize the”
· What are Anoise and Asignal in figure 7?
· Could you cite a reference for the sentence “Foreground calibration may be used in an environment where circuit performance remains stable …”?
· Use Power Spectral Density instead of “output spectrum” in “Figure 12(a) and (b) display the simulated output spectrum”
· Could you extend the process of “digitally synthesize the skew loop”? Which technology and tools do you use for the “digital synthesis”?
· Could you compare these results in terms of power, area, and data rate with others works?
· If it is possible, add some references from Electronics Journal.
· Extend the conclusion section pointing out the novelty and usefulness of the work.
Author Response
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Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
The version now is good
Author Response
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Author Response File: Author Response.pdf
Reviewer 2 Report
The authors already complied with almost all of the comments. One more thing. Could you clarify in more detail the differences between your contribution and the one described in the following attached published study, despite the fact that you have acknowledged sources related to ADC? Please discuss the advantages and strengths of this study over the latest published work this year.
C.-C. Wang, et al., (2022), A 2.71 fJ/conversion step 10-bit 50 MSPS split-capacitor array SAR ADC for FOG systems, International Journal of Electronics, DOI: 10.1080/00207217.2022.2118861
Comments for author File: Comments.pdf
Author Response
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Author Response File: Author Response.pdf
Reviewer 3 Report
The recommendations were attended by the authors in the new version of the manuscript.
Author Response
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Author Response File: Author Response.pdf
Round 3
Reviewer 2 Report
The authors already gave their satisfying replies to my comments and suggestions.
