A BIST Scheme for Dynamic Comparators

Abstract

This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, a feedback loop is designed using the characteristics of the comparator; monitoring the voltage in the feedback loop can determine the presence of a circuit fault. The proposed BIST scheme and the circuit under testing are realized at the transistor level. The proposed BIST scheme was simulated using HSPICE. The simulated fault coverage is approximately 87.8% with 90 test circuits. To further verify the effectiveness of the proposed BIST scheme, six faults were injected into the real circuit. The test results were consistent with the simulation results.

1. Introduction

Testing and diagnostic techniques develop with the progress of technology and the increase in integration. A built-in self-test (BIST) is one of the most challenging techniques for integrated circuits. BISTs can help save costs on the initial design [1,2,3].

BIST schemes for integrated circuits include a BIST circuit to obtain the attenuation frequency distortion, the variation of gain with input level, and the signal-to-total distortion through the DAC to the ADC [4]; a BIST circuit is also proposed for fault diagnosis of the ADC using a code-width test in [5]. However, these schemes are aimed at the system and do not apply to a fault test of the module circuit.

BIST schemes for the module circuit include a BIST circuit for fault diagnosis of an operational amplifier using chaotic oscillation [6], and a BIST circuit is proposed for fault diagnosis of sample-and-hold circuits based on the common mode in [7]. However, none of these schemes are suitable for dynamic comparators.

As a special comparator, a dynamic comparator is widely used because of its high speed and low power consumption. There are some reports of test strategies for the offset of the comparator proposed in [8,9].

However, there are few works on the fault diagnosis scheme for dynamic comparators. In this paper, a BIST scheme is proposed for detecting catastrophic faults in dynamic comparators. Section 2 previews the dynamic comparator under testing. Section 3 presents the proposed BIST scheme. The simulation results are set in Section 4. Section 5 presents the test results and discussion. Finally, Section 6 concludes the work.

2. The Dynamic Comparator under Testing

The dynamic comparator in [10] is shown in Figure 1 as the circuit under testing (CUT). CLK is the clock signal, which controls the “RESET” phase and “COMPARE” phase of the dynamic comparator. V_N and V_P are the input signals for the two comparison signals. O_N and O_P are the output signals for the comparison results.

In the “RESET” phase, CLK is logic “0”. The voltage of nodes 1, 2, 3, and 4 are pulled up to V_DD via M₁₀, M₁₁, M₈, and M₉, respectively. The output signals O_N and O_P are both logic “0”.

In the “COMPARE” phase, CLK is logic “1”. The voltage of node 5 is pulled down to GND via M₁. The voltages of nodes 1 and 2 decrease from the V_DD at different rates. The descent rate depends on the magnitude of the input signals V_N and V_P. As the voltage of nodes 1 and 2 falls to V_DD − V_THN, the voltage of nodes 3 and 4 decreases from the V_DD at different rates. The descent rate depends on the magnitude of the voltage of nodes 1 and 2.

Due to the difference in the rate of descent, the node voltage that drops slowest will eventually be pulled up to V_DD by the latch structure M_4–7 until it stabilizes.

Because of the latch structure, the output of the dynamic comparator only has logic “1” and logic “0”. This special property leads to the difference between the properties of dynamic comparators and amplifiers. Therefore, it is necessary to design a BIST scheme specifically for dynamic comparators.

3. The Proposed BIST Scheme for a Dynamic Comparator

The proposed BIST scheme for a dynamic comparator is shown in Figure 2. In this schematic, the properties of the comparator are used to establish a feedback loop, and by monitoring the voltage in the feedback loop the presence of a circuit fault can be determined.

When the BIST scheme is implemented, EN is logic “1”. Two NOR gates constitute an RS trigger. If VP is greater than V_N, the O_P is logic “1” and the O_N is logic “0” in the “COMPARE” phase. Then, the voltage of node 6 will be logic “0”. The voltage of node 7 will then increase via M₁₃ until the voltage of node 7 is higher than V_P. Then, the O_P is logic “0” and the O_N is logic “1” in the “COMPARE” phase. The voltage of node 6 will then be logic “1”. The voltage of node 7 will reduce via M₁₂ until the voltage of node 7 is lower than V_P. V_N will fluctuate repeatedly up and down around V_P.

Therefore, the voltage of the V_N can be monitored to determine whether there is a fault in the circuit. If the voltage of V_N fluctuates around V_P in a range, the circuit is fault-free, and this causes the window comparator to output logic “1”. Otherwise, the window comparator outputs logic “0”. According to the simulation results, the window boundary of the window comparison was designed to be 0.85V to 0.95V.

The structure of the window comparator in [11] that is used in this case is shown in Figure 3. The window comparator compares the input voltage to the window boundary. The window boundary is determined by a lower-limit voltage (V_L) and an upper-limit voltage (V_H). If the input signal (V_IN) is between the lower-limit voltage (V_L) and upper-limit voltage (V_H), the output signal is logic “1”. If the input signal (V_IN) is lower than the lower-limit voltage (V_L) or higher than the upper-limit voltage (VH), the output signal is logic “0”. The window boundary can be adjusted by adjusting the W/L of the four inverters.

4. Simulation Results

In this case, all possible catastrophic short and open faults with MOS transistors were considered. The short fault was performed by a serial connection with a 10 Ω resistor, and the open fault was performed by a parallel connection with a 10M Ω resistor and a 100f F capacitor. The six types of catastrophic faults were gate-drain short (GDS), gate-source short (DSS), drain-source short (DSS), gate open (GO), drain open (DO), and source open (SO). Moreover, only a signal fault was injected in the simulation, and the total number of fault circuits was 90.

Figure 4 shows the simulation results of the fault-free state. Figure 4a,b are the transient simulation waveforms of V_N and V_P and F, respectively. At the beginning of the test, the voltage of V_N is much higher than that of V_P. Furthermore, the output signal V_N is outside the window. Therefore, the output signal F is logic “0”. Because of the feedback system, the voltage of V_N continues to drop and finally enters the oscillation interval, fluctuating around the voltage value of V_P. Furthermore, the output signal V_N is in the window. Therefore, the output signal F becomes logic “1”. The faulty circuits with GOs of M_1,8–15 showed similar results.

The first fault type is when the voltage of V_N is always lower than 0.85V, which is the lower bound of the comparator window. The output signal F is always logic “0”, which indicates the circuit has a fault. Figure 5a,b show the simulation result of the faulty circuit with a GDS of M₁. The faulty circuits with GSSs of M_8–11,13 showed similar results. Figure 5c,d show the simulation result of the faulty circuit with a GDS of M₁₀. The faulty circuits with GDSs of M_12,13 and a DSS of M₁₂ showed similar results.

The second fault type is that the oscillating range of the V_N voltage crosses the window boundary of the window comparator. The output signal F has a periodic pulse, which indicates the circuit has a fault. Figure 6a,b show the simulation result of the faulty circuit with a GDS of M₂. Figure 6c,d show the simulation result of the faulty circuit with a DO of M₈. The faulty circuits with SOs of M_8,9 showed similar results. Figure 6e,f show the simulation result of the faulty circuit with a DO of M₁₁. The faulty circuits with a GO of M₇ and SOs of M_7,11 showed similar results. Figure 6g,h show the simulation result of the faulty circuit with an SO of M₆. The faulty circuits with an SO of M₁₀ showed similar results.

The third fault type is when the voltage of V_N crosses the upper and lower boundaries of the window comparator a finite number of times. The output signal F has a finite pulse, which indicates the circuit has a fault. Figure 7a,b show the simulation result of the faulty circuit with a GDS of M₃. The faulty circuits with GDSs of M_4-7, DSSs of M_2,7,9,11,15, GSSs of M_1,5,6,14, DOs of M_3,5,14, and SOs of M_3,5,14 showed similar results. Figure 7c,d show the simulation result of the faulty circuit with a GDS of M₈. The faulty circuits with an SO of M₁₂ showed similar results. Figure 7e,f show the simulation result of the faulty circuit with a DSS of M₁₃. The faulty circuits with a DO of M_9,12 showed similar results. Figure 7g,h show the simulation result of the faulty circuit with a DSS of M₄. The faulty circuits with GDSs of M_9,11, a GSS of M₂, a GO of M₃, and DOs of M_6,10,13 showed similar results.

The fourth fault type is when the voltage of V_N is always higher than 0.95 V, which is the upper bound of the comparator window. The output signal F is always logic “0”, which indicates the circuit has a fault. Figure 8a,b show the simulation result of the faulty circuit with a GDS of M₁₄. The faulty circuits with a GDS of M₁₅, DSSs of M_{1,3,6,8,10,14}, GSSs of M_3,4,7,12,15, DOs of M_1,2,4,15, and SOs of M_1,2,4,15 showed similar results. Figure 8c,d show the simulation result of the faulty circuit with a DSS of M₅. The faulty circuits with a DO of M₇ showed similar results.

Figure 9a,b show the simulation result of the faulty circuit with a GO of M₂. Figure 9c,d show the simulation result of the fault circuit with a GO of M₄. The faulty circuits with a GO of M₆ showed similar results. Figure 9e,f show the simulation result of the faulty circuit with a GO of M₅. Considering that in the actual test, if the output signal F performs a limited pulse it may not be observed, the GO fault types of M_4,6 were regarded as undetected.

In summary, there are three scenarios for the F signal. The first case is the steady state of logic “1” at the end; the second case is the steady state of logic “0” at the end; and the third case is to always transform between logic “0” and logic “1”. The first case is recorded as fault-free, and the other two cases are recorded as fault recognition. The simulation results shown in

Table 1. Simulation results of injected and detected fault.

Fault Types	Injected Faults	Detected Faults
GDS	15	15
GSS	15	15
DSS	15	15
GO 1	15	4
DO	15	15
SO	15	15

¹ The detected MOS transistors are M₂, M₃, M₅, and M₇.

were determined by the results after 25 μs. The simulated fault coverage is approximately 87.8% with 90 test circuits.

5. Test Results

To further verify the feasibility of the BIST scheme, one fault-free circuit and six faulty circuits were implemented in ROHM 180 nm CMOS technology. The specific six fault circuits were DO of M₁, GO of M₂, SO of M₃, DSS of M₄, GDS of M₅, and GSS of M₆.

5.1. Test Results

Figure 10 shows the test result of the fault-free circuit. Channel 1 is the CLK signal, channel 2 is the V_N signal, channel 3 is the F signal, and channel 4 is the V_P signal. As shown in Figure 10a, the voltage of the V_P signal is 900 mV, and the voltage of the V_N signal fluctuates around 900 mV. Similarly, as shown in Figure 10b, the voltage of the V_P signal is 600 mV, and the voltage of the V_N signal fluctuates around 600 mV. As analyzed, the V_N signal can follow the V_P signal.

The window boundary of the comparator was designed to be from 850 mV to 950 mV. Unfortunately, the window comparator did not identify correctly. Fortunately, the feasibility of the scheme can still be seen. The fault-free circuit and the faulty circuits with a DSS of M₄ both show the results.

Figure 11 shows the test result of the faulty circuit with a DO of M₁. As shown in Figure 11a, the voltage of the V_P signal is 900 mV, and the voltage of the V_N signal fluctuates around 900 mV. The difference is, as shown in Figure 11b, that the voltage of the V_P signal is 600 mV, and the voltage of the V_N signal fluctuates around 900 mV. The voltage of V_N is maintained at 900 mV. As analyzed, the V_N signal cannot follow the V_P signal. However, the voltage of V_N is maintained at 900 mV. The five faulty circuits with a DO of M₁, GO of M₂, SO of M₃, GDS of M₅, and GSS of M₆ all show the results.

5.2. Discussion

Although the test proved the feasibility of the solution, it was unusual for the V_N to maintain a voltage of 900 mV in the faulty circuit. The authors believe that this is probably the highest voltage a circuit can measure. Because there is no input buffer added at the input side, this may result in a maximum voltage of 1.8 V inside the circuit, but only 900 mV is measured.

To confirm this conjecture, the voltage of the V_N port was not detected, and the test was carried out. Figure 12 shows the test results of the fault-free circuit without the V_N port. Channel 1 is the CLK signal, channel 3 is the F signal, and channel 4 is the V_P signal. The F signal will periodically exhibit logic “1”. This indicates that the voltage of the V_N signal reaches the window boundary.

Furthermore, the test results indicate that the fluctuation range of V_N needs to be determined by further testing, and the window boundary of the comparator needs to be redesigned.

6. Conclusions

A dynamic comparator is a typically mixed-signal circuit widely used in high-speed and low-power consumption design. However, there are few works on fault diagnosis schemes for dynamic comparators. This work proposed a dynamic comparator scheme for detecting catastrophic faults. In this scheme, a feedback loop was designed using the characteristics of the comparator and monitoring the voltage in the feedback loop to determine the presence of a circuit fault. The proposed BIST scheme was designed and simulated in ROHM 180 nm CMOS technology. The simulated fault coverage is approximately 87.8% with 90 test circuits. To further verify the effectiveness of the proposed BIST scheme, one fault-free state and six faults were implemented in the real circuit. The test results show that the scheme is effective. However, the design still falls short. The boundaries of the comparator window require more data to determine.