1. Introduction
Testing and diagnostic techniques develop with the progress of technology and the increase in integration. A built-in self-test (BIST) is one of the most challenging techniques for integrated circuits. BISTs can help save costs on the initial design [
1,
2,
3].
BIST schemes for integrated circuits include a BIST circuit to obtain the attenuation frequency distortion, the variation of gain with input level, and the signal-to-total distortion through the DAC to the ADC [
4]; a BIST circuit is also proposed for fault diagnosis of the ADC using a code-width test in [
5]. However, these schemes are aimed at the system and do not apply to a fault test of the module circuit.
BIST schemes for the module circuit include a BIST circuit for fault diagnosis of an operational amplifier using chaotic oscillation [
6], and a BIST circuit is proposed for fault diagnosis of sample-and-hold circuits based on the common mode in [
7]. However, none of these schemes are suitable for dynamic comparators.
As a special comparator, a dynamic comparator is widely used because of its high speed and low power consumption. There are some reports of test strategies for the offset of the comparator proposed in [
8,
9].
However, there are few works on the fault diagnosis scheme for dynamic comparators. In this paper, a BIST scheme is proposed for detecting catastrophic faults in dynamic comparators.
Section 2 previews the dynamic comparator under testing.
Section 3 presents the proposed BIST scheme. The simulation results are set in
Section 4.
Section 5 presents the test results and discussion. Finally,
Section 6 concludes the work.
2. The Dynamic Comparator under Testing
The dynamic comparator in [
10] is shown in
Figure 1 as the circuit under testing (CUT).
CLK is the clock signal, which controls the “RESET” phase and “COMPARE” phase of the dynamic comparator.
VN and
VP are the input signals for the two comparison signals.
ON and
OP are the output signals for the comparison results.
In the “RESET” phase, CLK is logic “0”. The voltage of nodes 1, 2, 3, and 4 are pulled up to VDD via M10, M11, M8, and M9, respectively. The output signals ON and OP are both logic “0”.
In the “COMPARE” phase, CLK is logic “1”. The voltage of node 5 is pulled down to GND via M1. The voltages of nodes 1 and 2 decrease from the VDD at different rates. The descent rate depends on the magnitude of the input signals VN and VP. As the voltage of nodes 1 and 2 falls to VDD − VTHN, the voltage of nodes 3 and 4 decreases from the VDD at different rates. The descent rate depends on the magnitude of the voltage of nodes 1 and 2.
Due to the difference in the rate of descent, the node voltage that drops slowest will eventually be pulled up to VDD by the latch structure M4–7 until it stabilizes.
Because of the latch structure, the output of the dynamic comparator only has logic “1” and logic “0”. This special property leads to the difference between the properties of dynamic comparators and amplifiers. Therefore, it is necessary to design a BIST scheme specifically for dynamic comparators.
3. The Proposed BIST Scheme for a Dynamic Comparator
The proposed BIST scheme for a dynamic comparator is shown in
Figure 2. In this schematic, the properties of the comparator are used to establish a feedback loop, and by monitoring the voltage in the feedback loop the presence of a circuit fault can be determined.
When the BIST scheme is implemented, EN is logic “1”. Two NOR gates constitute an RS trigger. If VP is greater than VN, the OP is logic “1” and the ON is logic “0” in the “COMPARE” phase. Then, the voltage of node 6 will be logic “0”. The voltage of node 7 will then increase via M13 until the voltage of node 7 is higher than VP. Then, the OP is logic “0” and the ON is logic “1” in the “COMPARE” phase. The voltage of node 6 will then be logic “1”. The voltage of node 7 will reduce via M12 until the voltage of node 7 is lower than VP. VN will fluctuate repeatedly up and down around VP.
Therefore, the voltage of the VN can be monitored to determine whether there is a fault in the circuit. If the voltage of VN fluctuates around VP in a range, the circuit is fault-free, and this causes the window comparator to output logic “1”. Otherwise, the window comparator outputs logic “0”. According to the simulation results, the window boundary of the window comparison was designed to be 0.85V to 0.95V.
The structure of the window comparator in [
11] that is used in this case is shown in
Figure 3. The window comparator compares the input voltage to the window boundary. The window boundary is determined by a lower-limit voltage (
VL) and an upper-limit voltage (
VH). If the input signal (
VIN) is between the lower-limit voltage (
VL) and upper-limit voltage (
VH), the output signal is logic “1”. If the input signal (
VIN) is lower than the lower-limit voltage (
VL) or higher than the upper-limit voltage (VH), the output signal is logic “0”. The window boundary can be adjusted by adjusting the W/L of the four inverters.
4. Simulation Results
In this case, all possible catastrophic short and open faults with MOS transistors were considered. The short fault was performed by a serial connection with a 10 Ω resistor, and the open fault was performed by a parallel connection with a 10M Ω resistor and a 100f F capacitor. The six types of catastrophic faults were gate-drain short (GDS), gate-source short (DSS), drain-source short (DSS), gate open (GO), drain open (DO), and source open (SO). Moreover, only a signal fault was injected in the simulation, and the total number of fault circuits was 90.
Figure 4 shows the simulation results of the fault-free state.
Figure 4a,b are the transient simulation waveforms of
VN and
VP and
F, respectively. At the beginning of the test, the voltage of
VN is much higher than that of
VP. Furthermore, the output signal
VN is outside the window. Therefore, the output signal
F is logic “0”. Because of the feedback system, the voltage of
VN continues to drop and finally enters the oscillation interval, fluctuating around the voltage value of
VP. Furthermore, the output signal
VN is in the window. Therefore, the output signal
F becomes logic “1”. The faulty circuits with GOs of
M1,8–15 showed similar results.
The first fault type is when the voltage of
VN is always lower than 0.85V, which is the lower bound of the comparator window. The output signal
F is always logic “0”, which indicates the circuit has a fault.
Figure 5a,b show the simulation result of the faulty circuit with a GDS of
M1. The faulty circuits with GSSs of
M8–11,13 showed similar results.
Figure 5c,d show the simulation result of the faulty circuit with a GDS of
M10. The faulty circuits with GDSs of
M12,13 and a DSS of
M12 showed similar results.
The second fault type is that the oscillating range of the
VN voltage crosses the window boundary of the window comparator. The output signal
F has a periodic pulse, which indicates the circuit has a fault.
Figure 6a,b show the simulation result of the faulty circuit with a GDS of
M2.
Figure 6c,d show the simulation result of the faulty circuit with a DO of
M8. The faulty circuits with SOs of
M8,9 showed similar results.
Figure 6e,f show the simulation result of the faulty circuit with a DO of
M11. The faulty circuits with a GO of
M7 and SOs of
M7,11 showed similar results.
Figure 6g,h show the simulation result of the faulty circuit with an SO of
M6. The faulty circuits with an SO of
M10 showed similar results.
The third fault type is when the voltage of
VN crosses the upper and lower boundaries of the window comparator a finite number of times. The output signal
F has a finite pulse, which indicates the circuit has a fault.
Figure 7a,b show the simulation result of the faulty circuit with a GDS of
M3. The faulty circuits with GDSs of
M4-7, DSSs of
M2,7,9,11,15, GSSs of
M1,5,6,14, DOs of
M3,5,14, and SOs of
M3,5,14 showed similar results.
Figure 7c,d show the simulation result of the faulty circuit with a GDS of
M8. The faulty circuits with an SO of
M12 showed similar results.
Figure 7e,f show the simulation result of the faulty circuit with a DSS of
M13. The faulty circuits with a DO of
M9,12 showed similar results.
Figure 7g,h show the simulation result of the faulty circuit with a DSS of
M4. The faulty circuits with GDSs of
M9,11, a GSS of
M2, a GO of
M3, and DOs of
M6,10,13 showed similar results.
The fourth fault type is when the voltage of
VN is always higher than 0.95 V, which is the upper bound of the comparator window. The output signal
F is always logic “0”, which indicates the circuit has a fault.
Figure 8a,b show the simulation result of the faulty circuit with a GDS of
M14. The faulty circuits with a GDS of
M15, DSSs of
M1,3,6,8,10,14, GSSs of
M3,4,7,12,15, DOs of
M1,2,4,15, and SOs of
M1,2,4,15 showed similar results.
Figure 8c,d show the simulation result of the faulty circuit with a DSS of
M5. The faulty circuits with a DO of
M7 showed similar results.
Figure 9a,b show the simulation result of the faulty circuit with a GO of
M2.
Figure 9c,d show the simulation result of the fault circuit with a GO of
M4. The faulty circuits with a GO of
M6 showed similar results.
Figure 9e,f show the simulation result of the faulty circuit with a GO of
M5. Considering that in the actual test, if the output signal
F performs a limited pulse it may not be observed, the GO fault types of
M4,6 were regarded as undetected.
In summary, there are three scenarios for the
F signal. The first case is the steady state of logic “1” at the end; the second case is the steady state of logic “0” at the end; and the third case is to always transform between logic “0” and logic “1”. The first case is recorded as fault-free, and the other two cases are recorded as fault recognition. The simulation results shown in
Table 1 were determined by the results after 25 μs. The simulated fault coverage is approximately 87.8% with 90 test circuits.
5. Test Results
To further verify the feasibility of the BIST scheme, one fault-free circuit and six faulty circuits were implemented in ROHM 180 nm CMOS technology. The specific six fault circuits were DO of M1, GO of M2, SO of M3, DSS of M4, GDS of M5, and GSS of M6.
5.1. Test Results
Figure 10 shows the test result of the fault-free circuit. Channel 1 is the
CLK signal, channel 2 is the
VN signal, channel 3 is the
F signal, and channel 4 is the
VP signal. As shown in
Figure 10a, the voltage of the
VP signal is 900 mV, and the voltage of the
VN signal fluctuates around 900 mV. Similarly, as shown in
Figure 10b, the voltage of the
VP signal is 600 mV, and the voltage of the
VN signal fluctuates around 600 mV. As analyzed, the
VN signal can follow the
VP signal.
The window boundary of the comparator was designed to be from 850 mV to 950 mV. Unfortunately, the window comparator did not identify correctly. Fortunately, the feasibility of the scheme can still be seen. The fault-free circuit and the faulty circuits with a DSS of M4 both show the results.
Figure 11 shows the test result of the faulty circuit with a DO of
M1. As shown in
Figure 11a, the voltage of the
VP signal is 900 mV, and the voltage of the
VN signal fluctuates around 900 mV. The difference is, as shown in
Figure 11b, that the voltage of the
VP signal is 600 mV, and the voltage of the
VN signal fluctuates around 900 mV. The voltage of
VN is maintained at 900 mV. As analyzed, the
VN signal cannot follow the
VP signal. However, the voltage of
VN is maintained at 900 mV. The five faulty circuits with a DO of
M1, GO of
M2, SO of
M3, GDS of
M5, and GSS of
M6 all show the results.
5.2. Discussion
Although the test proved the feasibility of the solution, it was unusual for the VN to maintain a voltage of 900 mV in the faulty circuit. The authors believe that this is probably the highest voltage a circuit can measure. Because there is no input buffer added at the input side, this may result in a maximum voltage of 1.8 V inside the circuit, but only 900 mV is measured.
To confirm this conjecture, the voltage of the
VN port was not detected, and the test was carried out.
Figure 12 shows the test results of the fault-free circuit without the
VN port. Channel 1 is the
CLK signal, channel 3 is the
F signal, and channel 4 is the
VP signal. The
F signal will periodically exhibit logic “1”. This indicates that the voltage of the
VN signal reaches the window boundary.
Furthermore, the test results indicate that the fluctuation range of VN needs to be determined by further testing, and the window boundary of the comparator needs to be redesigned.