A Referenceless Digital CDR with a Half-Rate Jitter-Tolerant FD and a Multi-Bit Decimator

Abstract

A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant frequency detector (FD) and a multi-bit decimator is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital quadricorrelator frequency detector (JT-DQFD). Additionally, we proposed a multi-bit decimator circuit that losslessly down-samples up/down data from a phase detector to reduce the recovered clock jitter. The down-sampled multi-bit phase information is processed by a digital loop filter to adjust the phase of the recovered clock. Fabricated in a 28-nm CMOS technology, the test chip achieves a power efficiency of 1.3 pJ/bit at 10 Gb/s.

1. Introduction

In modern SOCs, the size of chipset is limited by the number of package balls or bumps, rather than the silicon die area itself. Thus, in mobile SOCs that require a small form-factor, analog or parallel interfaces are replaced with serial interfaces (SerDes) for reducing the number of interconnections as shown in Figure 1. In this Serdes technology, clock-and-data-recovery circuits (CDR) that recover the clock and data information from the arbitrary input stream are the most important block. For stand-alone operations, we adopted the PLL-based CDR that does not require an external clock source. Additionally, we applied digital-CDR (D-CDR) configuration for its design portability [1,2,3,4,5,6,7] to a half-speed clock scheme, which cuts the operating speed of the phase detector in half.

Even though there is a crystal oscillator on a cellular phone board for various sub-systems, clock distributions for multiple CDRs increase board- or package-level design complexity. Thus, we implemented the referenceless frequency locking scheme. However, a digital quadricorrelator frequency detector (DQFD), which has been widely used in frequency acquisition, has a deadzone problem that causes lock time delay or lock fail if the input signal is jittery [8,9,10,11]. In addition, a half-rate configuration of DQFD requires eight-phase clocks, which increase the power and area of an oscillator circuit. To overcome these problems, we proposed a half-rate jitter-tolerant frequency detector circuit with four-phase clocks.

In most D-CDRs, a bangbang phase detector (BBPD) is used for its digital-friendly behaviors [12]. However, because of its binary operation, it generates much quantization noise, which affects the output jitter performance. In general, the high-speed phase information from the BBPD is decimated to ease the speed requirement of the following digital loop filter, but conventional decimator circuits inevitably lose some information during the decimation operation. Thus, multi-level BBPDs [13,14,15,16,17] have been introduced to reduce quantization noise. As this requires multiple BBPDs and other building blocks that operate at a full rate, the power consumption linearly increases as the resolution is increased. Thus, we propose a low-power, multi-bit decimator circuit with a BBPD that can decimate the phase difference information with lower quantization noise.

In this paper, we first discuss several approaches to implementing low-power D-CDRs, and then present the architecture and design details of the proposed D-CDR in Section 2. In Section 3, the measurement results are provided. Finally, the key contributions of this paper are summarized in Section 4.

2. Digital CDR Architecture

Figure 2 shows the proposed receiver architecture including an on-die-termination (ODT), a CML-to-CMOS converter, and a D-CDR. The pseudo-differential CML-to-CMOS converter amplifies the input differential signal and achieves rail-to-rail swing. Compared with the conventional, fully differential amplifier, a tail current source has been removed to achieve a wider input range. Then, a half-rate jitter-tolerant DQFD (JT-DQFD) in a frequency locked loop (FLL) detects the frequency difference between the incoming data and the recovered clock. The up and down signals from FD are integrated in a digital integrator circuit, then a lock detector and a frequency bank controller drive a digitally controlled oscillator (DCO) for frequency locking. When frequency acquisition is completed, the lock detector gives the authority for the DCO to a phase locked loop. In the phase locked loop, a half-rate BBPD compares the phase difference between the incoming data and recovered clock, and generates two up and two down signals because of its half-rate configuration. Then, a three-bit decimator downsamples the phase information by a factor of eight, and the proportional-integral digital loop filter (PI-DLF) processes the digitized phase information to adjust the phase of the recovered clock.

2.1. Jitter-Tolerant Frequency Detector

Figure 3a shows the schematic of the proposed half-rate JT-DQFD and the conventional half-rate DQFD. For the half-rate DQFD configuration using the conventional scheme, an eight-phase DCO is required to generate CLK45 and CLK135 along with CLK0 and CLK90, which increases power consumption, chip area, and clock network complexity. For a compact design, we implemented the same function using four-phase clocks by delaying input data by 45 degrees (using DLY block in Figure 3a). The state diagram of the conventional half-rate DQFD is shown in Figure 3b. The state (STATE), which is determined by Q_A and Q_B, changes clockwise when 2·F_CLK > F_DATA, and it rotates counter-clockwise when 2·F_CLK < F_DATA. Note that sampling events only occur at the falling transitions of Q_B, so DN is asserted high when the state changes from III (VII) to IV (VIII) and UP is asserted high when the state changes from II (VI) to I (V) in a conventional half-rate DQFD. However, the actual input signal, DIN, has a jitter, as shown in Figure 4, so it causes detection errors during frequency-locking operations. For example, if 2·F_CLK > F_DATA (FAST), the frequency detector outputs down (DN) at the falling edge of Q_B and the state should remain the same until the recovered clock frequency becomes lower than the frequency of input data (2· F_CLK < F_DATA). However, because of the input jitter, Q_B fluctuates between high and low when Q_B changes from low to high (e.g., State I(V) → II(VI)). During this unstable situation, wrong UP can be sampled while the previous value DN should be held. As a result of this detection error, frequency locking can take more time or eventually fail.

To circumvent this problem, we have adopted the jitter-tolerant scheme in [8] and modified it to the half-rate configuration. Figure 4b illustrates the operation of the proposed JT-DQFD. When 2· F_CLK > F_DATA, DN is sampled at the falling edge of Q_B and it is held until the FD samples UP signal. Even in this scheme, jitter-induced sampling errors still exist in UP and DN signals, but the information generated from STATE II (VI) and III (VII), where the detection errors could happen, was blocked so that the errors do not affect the final value in a digital integrator. As a half of the states are blocked in the JT-DQFD, a gain decreases accordingly, but it could be compensated by adjusting the threshold level in a lock detector.

Figure 5 compares the transfer characteristics of the conventional DQFD and the proposed JT-DQFD. The average output values of FDs are measured through the simulation at 10 Gb/s, and the input data include random jitter (RJ) of 0.1 UI–0.3 UI. As shown in Figure 5a, when the frequency error is between −10 kppm and +10 kppm, the output of the conventional FD entails frequency detection errors, resulting in a deadzone problem. On the other hand, the proposed JT-DQFD does not show the deadzone problem in the same jitter conditions, as illustrated in Figure 5b.

As we have implemented the DLY block using inverter cells, the delay varies depending on the process, supply voltage, and temperature (PVT) variation, which raises concerns about the impact on FD’s behavior. However, the phase shift of the DLY block does not have to be exactly 0.25 UI. Considering that the purpose is to divide one UI into four STATEs, and the VCO provides the clean reference edges (CLK0 and CLK90), the maximum delay variation must be less than ±0.25 UI because CLK45 is centered between CLK0 and CLK90. Thus, the proposed scheme can properly work unless the logic delay is doubled. Figure 6 shows the characteristics of the proposed FD with variations in the input delay line. The simulation results confirm that the proposed FD functions properly even with ±30% delay variations and 0.2-UI random jitter. By implementing the DQFD with four-phase clocks, we can use a compact two-stage ring oscillator, and the required number of clock buffers is also halved.

2.2. Multi-Bit Decimator with a Bangbang Phase Detector

Figure 7a shows the conventional half-rate BBPD scheme that is incorporated with a majority voter and a decimator for down-sampling operation [1]. The majority voter determines the Polarity based on the multiple BBPD output signals. Then, the first flip-flop in the conventional decimator captures the polarity signal with CLK/2, and the captured data are sequentially resampled by flip-flops that operate with the 4× and 8× slower clocks. Thus, the high-speed polarity signal is subsampled with the 8× slower clock, making it impossible to capture transitions in the decimator’s input signal during the relatively long subsampling period. When the phase locking is completed, the BBPD alternately outputs up and down signals. Thus, even though the phase difference between the input data and the recovered clock is quite small, once the decimator samples a signal, the same value is maintained during a decimation period. As a result, regardless of the degree of phase difference, the DCO moves to one direction with the binary gain (UP or DN) during the sub-sampling period. Then, the proportional gain in digital loop filter should be decreased for reducing the recovered clock jitter.

The output jitter magnitude of the conventional BBPD based CDR can be appoximated as below [14].

$${\sigma }_{jout,RMS}\approx \sqrt{\frac{\sqrt{2\pi }}{8}·K_p·K_{DCO}·T_d·{\sigma }_{jin}}\left[\mathrm{UI}\right]$$

(1)

where the transition density of input data is assumed to be 0.5, $K_p$ is a proportional gain in a digital loop filter, $K_{DCO}$ is a unit frequency step in a DCO, $T_d$ is a loop latency, and ${\sigma }_{jin}$ is a standard deviation of a input jitter. To reduce the jitter magnitude, $K_p$ and $K_{DCO}$ should be reduced if other parameters, such as $T_d$ and ${\sigma }_{jin}$, are given. However, considering that the jitter transfer bandwidth (JTRAN) is approximately proportional to $K_p$ and $K_{DCO}$ as shown in Equation (2), we cannot reduce $K_p$ and $K_{DCO}$ values to a negligible level.

$$\mathrm{JTRAN}\approx K_{BBPD}·K_P·K_{DCO}[\mathrm{rad}/\mathrm{s}]$$

(2)

where $K_{BBPD}$ is a gain of BBPD.

For reducing the quantization noise of the BBPD, the multi-level BBPD (ML-BBPD) scheme has been introduced [15,16,17]. The multi-level BBPD consists of multiple BBPDs, delay components, and a thermometer to binary decoder, as shown in Figure 8a. The input data streams (DIN) are sequentially delayed by $T_d$, resulting in input signals with different phases for one data transition. Then, the signals enter into the multiple BBPDs that capture the input on the same clock edge to create up or down outputs. Thus, the BBPDs in ML-BBPD have different threshold phase as shown in Figure 8b. Compared with the 1st BBPD, the threshold phase of the Nth BBPD is shifted by N times $T_d$. As a result, we can have the magnitude information of the phase difference, as well as the polarity information of the phase difference between the input data and the clock edge as shown in Figure 8c. However, ML-BBPD has a penalty in power consumption because multiple BBPDs and delay components are running at a full-rate speed.

To overcome this problem, we proposed a counter-based multi-bit decimator circuit, which is shown in Figure 9a. The proposed decimator consists of a pulse generator and a three-bit up-counter. The pulse generator generates a pulse (DIN_C) when the incoming signal (DIN) sampled by the full-rate clock (CLK) is high. Then, the following up-counter counts the number of pulses. The counting results, DO_C<2:0>, are updated to the flip-flops in the PI-DLF, and the up-counter is reset when CLK/8 returns to high. Compared with the conventional decimator, the proposed decimator has the following advantages. First, by replacing the resampling flip-flops of the conventional decimator with the up-counter circuit, the possibility of information loss during a subsampling process is eliminated. Second, the output of the proposed decimator is proportional to the number of pulses; therefore, UP_0, DN_0, UP_1, and DN_1 are proportional to the number of “1” in up_0, dn_0, up_1, and dn_1, respectively. As illustrated in Figure 7b and Figure 9b, the conventional decimator captures the input data when CLK/8 goes high, and keeps the current value until the next rising edge of CLK/8 arrives whereas the proposed decimator accumulates the input data during a clock period of CLK/8. That is, the BBPD output is continuously converted to pulses and counted without any loss. Hence, the decimator output is proportional to the amount of phase difference, similar to that of ML-BBPDs. Figure 10 shows the results of the behavioral simulation (CppSim) to compare the recovered clocks according to the decimator configurations. The recovered clock with the proposed decimator shows a peak-to-peak jitter of 15 ps for 10,000 edge samples while the conventional decimator shows 21 ps at 10 Gbps.

2.3. PI-Control Digital Loop Filter

As shown in Figure 11, the multi-bit decimator provides a three-3-bit phase information (UP_0, DN_0, UP_1, DN_1) for each signal, so an arithmetic logic circuit incorporates the phase information into a single five-bit data as follows:

$$\mathrm{D}\_\mathrm{error}=(\mathrm{UP}\_0-\mathrm{DN}\_0)+(\mathrm{UP}\_1-\mathrm{DN}\_1)$$

(3)

where D_error is the output of the arithmetic logic in Figure 11. Then, the phase information is processed by a proportional-integral controller (PI-controller) to adjust a clock phase of a DCO. As the amount of jitter from a recovered clock is closely related to the loop latency as explained in Equation (2), we used minimum delay components (three flip-flop delays as shown in Figure 11). Additionally, a shifter logic is used for gain control of the proportional and integral paths (Ki and Kp).

2.4. Digitally Controlled Oscillator

Figure 12 shows the architecture of the implemented DCO that has five-5-bit binary-coded current-steering digital-to-analog converter (DAC) for frequency locking, and five-bit, thermometer-coded capacitive DAC for phase locking. A reference current (I_REF) with a low voltage cascode scheme generates a reference voltage (V_BN1), then the current is copied to the binary weighted current units. Compared to the thermometer-coded current DAC that shows higher current matching performance, the binary-weighted current DAC for a DCO requires precise current matching. Thus, identical current units are grouped to form binary current components. To find the optimal unit transistor size for current matching, the paper by Pelgrom [18] provides the equation as below:

$${\sigma }^2\left(\frac{△I}{I}\right)=\frac{1}{W·L}\left({A_{\beta }}^2+\frac{4·{A_{Vth}}^2}{{(V_{GS}-V_{TH})}^2}\right)$$

(4)

where W and L are the width and length of the unit transistor; $A_{\beta }$ and $A_{V_{th}}$ are process-dependent matching parameters. In addition, cascoding is necessary for boosting the output impedance of current sources. For low power consumption in a current-steering DAC, we should have a large current copy ratio from I_REF to I_DAC, and from I_DAC to I_DCO in Figure 12. However, a drawback of the large copy ratio is that the noise from a diode-connected transistor, M_NREF, is amplified. Therefore, passive filters are inserted between the current copy transistors, so the thermal and flicker noise from the bias generating transistors can be suppressed. In addition, C_LF helps improve power supply rejection ratio (PSRR) [19].

3. Measurement Results

The proposed CDR was fabricated in a 28 nm low-power CMOS technology with an area of 100 $\mathsf{\mu }$m × 90 $\mathsf{\mu }$m, as shown in Figure 13 [20]. The overall power consumption of the CDR, the CML-to-CMOS converter, and the bias generator was 13 mW from a 1-V supply at 10 Gb/s (12.7 mW for the CDR). The BER tester (Agilent J-BERT N4903B) provided a full-rate PRBS7-1 data to a wire-bonded test chip through the SMA cable, and 3-cm PCB trace from the SMA to the silicon die. Then, the recovered half-rate clock and data were input to the BER tester or oscilloscope. Figure 14 shows the simulated signal eye-diagram before and after the channel, and the CML-to-CMOS converter output. The received signal with a differential 0.67 V swing was amplified by the converter circuit to a swing of 2 V at the CMOS level.

Figure 15 shows the frequency-locking operation at 10 Gbps: (a) incremental search and (b) decremental search. When the frequency detector was not enabled, the DCO was free-running at the lowest frequency of the DCO. Once we started frequency locking, it started frequency accumulation from the middle code of the DCO (0 in 2’s complement format). The measured lock times were 1.5 $\mathsf{\mu }$s and 1.1 $\mathsf{\mu }$s for 8-code increments and 7-code decrements, respectively.

The recovered clock jitter was measured over 10,000 cycles using a digital oscilloscope (DSA 71254C), and the measured jitter was 3.03 ps_rms and 20.05 ps_pp for 10-Gbps PRBS7 input data, as shown in Figure 16. Additionally, the measured jitter tolerance (JTOL) at 10 Gb/s is shown in Figure 17. The high-frequency JTOL was approximately 0.25 UI, and the corner frequency was approximately 15 MHz. Figure 18 illustrates the power and area breakdown of the D-CDR. It shows that nearly half of the area and power consumption was taken by the DCO circuit. If we adopted the conventional half-rate DQFD with a 8-phase VCO circuit, the portion of the DCO could be increased more for driving the four-stage delay cells.

Table 1. Performance comparison with previous works.

	JSSC 16’ [3]	TCAS-1 16’ [4]	TCAS-I 17’ [5]	VLSI 19’ [6]	This Work
process [nm]	65	65	65	65	28
data rate [Gb/s]	4–10.5	0.8–6.5	10	4–20	9.5–10.5
supply [V]	1.2/1.0	1.2	1.2	1.2	1.0
clock rate	half-rate	half-rate	quarter-rate	half-rate	half-rate
data pattern	PRBS7 (JTOL) PRBS31(CLK)	PRBS31	PRBS7	PRBS31	PRBS7
clock jitter [ps${}_{\mathrm{rms}}$/ps${}_{\mathrm{pp}}$]	2.2/24	4.04/38.2	2.45/32.3	1.95/12.8	3.03/20.5
high frequency JTOL[UI]	0.4 *	-	0.22	0.42	0.25
area [mm]	1.63	0.018	0.117	0.045	0.009
power [mW]	22.5@10G	[email protected]	20.7@10G **	37.3@20G	13@10G ***
FoM [pJ/bit]	2.25	2.4	2.07 **	1.87	1.3 ***

* Inferred from JTOL results, ** including data recovery circuit, *** including CML-to-CMOS converter and bias generator.

summarizes the performance comparison of the proposed CDR with previously published digital CDRs.

4. Conclusions

This paper presents the design of a 10 Gb/s half-rate digital CDR that utilizes a half-rate JT-DQFD, a multi-bit decimator circuit, a PI-control DLF, and a low power DCO. The proposed half-rate JT-DQFD is implemented with only four-phase clocks while overcoming the deadzone problem during frequency acquisition. Additionally, the proposed multi-bit decimator with the PI-control DLF prevents the possible loss of phase information during a subsampling operation. The proposed CDR including CML-To-CMOS converter was fabricated in 28-nm CMOS technology, and achieves a power efficiency of 1.3 pJ/bit.