A Referenceless Digital CDR with a Half-Rate Jitter-Tolerant FD and a Multi-Bit Decimator

Round 1

Reviewer 1 Report

• Is the CDR system designed for Return-to-zero data as seems the case from the example data. Explain also the impact on the design choices
• 5: “unless the logic delay is not doubled”. Should it not be “unless the logic delay is doubled”
• For Fig. 7, Add the intermediate signals up_0, dn_0 etc. and also the Polarity signal
• If the data is sampled at half the clock rate (or every 90 degrees of CLK/8) then don't you miss information on the bit edge coz you are sampling only every other bit? Could you explain how this still provides information on the phase difference?
• Is the multi-level BBPD in fact not identical to a low-range flash TDC?
• For Fig. 9 Include the original data and use the same data as in Fig. 7 which means the up_0, dn_0 and other signals would also be the same and make the comparison more clear for the reader.
• Can you comment on the PSRR of the pseudodifferential cells in the ring oscillator

Author Response

Please find the attached file.

Author Response File: Author Response.pdf

Reviewer 2 Report

The author proposed a reference less clock and input data recovery circuit using half-rate jitter tolerant frequency detection technique. The author adopted PLL-based CDR and bang-bang phase detector techniques and make significant changes. The author proposed an input data delay-based technique along with a modified DQFD. The technique gives stable output up to variation which god sign. Overall, I found sufficient research in the article. I have just one concern about low power 28nm technology. The author does not reveal the name of the technology and specification such as is it bulk for FDSOI. Technological aspects. Process corner-based simulation results. How many pads are used to test the design? Is there any multiplexing at the input? The author should also change the result representation. Graphs do not have legends.

References are very old. The author should give reference to all included designs, theories, and important points. 

Author Response

Please find the attached file.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Previous comments have been adequately addressed and paper can be considered for publication