Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips
Round 1
Reviewer 1 Report
The paper proposed a novel dual change-sensing FF to redue dynamic power consumption and short-circuit currents, and comparied with other three FFs, it achieves more excellent comprehensive performance.
However, it will be better if the performance differences in Table 1 could be explained in depth.
Author Response
The paper proposed a novel dual change-sensing FF to reduce dynamic power consumption and short-circuit currents, and compared with other three FFs, it achieves more excellent comprehensive performance. However, it will be better if the performance differences in Table 1 could be explained in depth.
→ We are thankful for your kind comments. According to your comments, we explain the performance comparison about Table 1 in depth. Please see the blue and bold fonts from row #209 to row #224, Page 9.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
why 65-nm CMOS process was selected, not the latest one? No fabrication details are included. A new technique that a node to detect data changes in the CSFF has been separated into DCS-1 node 200 and DCS-2 node, respectively (Need more details for the justification)Author Response
Why 65-nm CMOS process was selected, not the latest one? No fabrication details are included. A new technique that a node to detect data changes in the CSFF has been separated into DCS-1 node 200 and DCS-2 node, respectively (Need more details for the justification)
→ Thank you for your comments. A Samsung 65nm CMOS technology has been used to fabricate the chip, because it was easily accessible for our University with a low price. We think, of course, the measured results of this paper must be the same with the latest CMOS technology, because the minimum transistor size is also adopted in the latest CMOS technology. Some fabrication details are included in the revised version. Please see the blue and bold fonts from row #159 to row #161, Page 7.
In order to significantly minimize the redundant transitions of conventional flip-flops, the proposed DCSFF shown in Fig.5 divides the CS nodes of CSFF shown in Fig.4 into two nodes (DCS-1 and DCS-2). DCS-1 and DCS-2 replace CS nodes when the data are rising and falling, respectively. For example, DCS-1 can eliminate the redundant transition when the input data are rising (Data = ”0” to “1”). Further, DCS-2 can eliminate the redundant transition when the input data are falling (Data = ”1” to “0”). Please see the blue and bold fonts from row #95 to row #104, Page 4.
Author Response File: Author Response.pdf
Reviewer 3 Report
The quality of the paper overall is good, but needs improvements (please get a proof reader). There are a lot of redundant phrases like "TGFF consumes a high-power dissipation due to a large number". The TGFF either consumes a lot of power (or dissipate) or has a high power dissipation, not both.
On row 42 the performance degradation might be due to the technology node used and so the phrase must be revised to take this into account.
On row 60-61 you cite [8-20] and then presents only 4 designs without mentioning the others, you either remove non-presented citation or present them all.
Figure 2. You mention TSPCFF but not show any result about this architecture, surely, having less internal nodes should consume little power, maybe comparable with your design.
Figure 11. lots of typos.
Figure 13. is not clear, too many arrows in my opinion, it is alread clear the power consumption of the various designs, and it is well explained in the text.
Rows 134>183: this paragraph is vague, more numbers should be given instead of "steeper", "smaller" and so on. A scientific paper should states facts, not be vague.
Again, Figure 14, the graphs is more clear without arrows and it is explained in the text.
Table1. Layout plays a major roles on power consumption (larger parasitics means more drawn power) but the size is given in arbitrary unit. More info should be given because is one of the major factor in what you are presenting.
Author Response
The quality of the paper overall is good, but needs improvements (please get a proof reader). There are a lot of redundant phrases like "TGFF consumes a high-power dissipation due to a large number". The TGFF either consumes a lot of power (or dissipate) or has a high power dissipation, not both.
→ Thank you for your kind comments. According to your kind comments, the phrase has been changed. Please see the blue and bold fonts from row #32 to row #33, Page 1.
On row 42 the performance degradation might be due to the technology node used and so the phrase must be revised to take this into account.
→ I am thankful for your comments. According to your kind comments, the phrase has been changed. Please see the blue and bold fonts from row #39 to row #43, Page 1.
On row 60-61 you cite [8-20] and then presents only 4 designs without mentioning the others, you either remove non-presented citation or present them all.
→ Thank you for your kind comments. I am sorry for the unsuitable references. The contents of references have been changed and revised. Since the references from [8] to [16] have been investigated and studied, all of them are presented in the references. Even though they are not shown in this paper, they make a great role to design a new circuit of flip-flop. Please consider it. Please see the blue and bold fonts from row #67 to row #69, Page 2.
Figure 2. You mention TSPCFF but not show any result about this architecture, surely, having less internal nodes should consume little power, maybe comparable with your design.
→ I am really thankful for your comments. Your comment is right. However, TSPCFF has many glitches and non-static behaviors, because there are a lot of floating nodes. Even though it has less internal nodes, many floating nodes generates huge short-circuit currents and large power consumption. By the way, the proposed DCSFF has no internal floating nodes. Please take it into account. Please see the blue and bold fonts from row #39 to row #43, Page 1.
Figure 11. lots of typos.
→ Thank you for your comments. According to your kind comments, the typos of Figure 11 has been changed. Please see the Figure 11, Page 7.
Figure 13. is not clear, too many arrows in my opinion, it is already clear the power consumption of the various designs, and it is well explained in the text.
→ I am thankful for your comments. According to your kind comments, a few arrows shown in Figure 13 has been eliminated. Please see the Figure 13, Page 8.
Rows 134>183: this paragraph is vague, more numbers should be given instead of "steeper", "smaller" and so on. A scientific paper should states facts, not be vague.
→ I am really thankful for your comments. Your comment is right. Even though many experimental results and numbers were ready for this paper, we did not insert them. More specific numbers are given and added into the revised version. Please see the blue and bold fonts from row #179 to row #189, Page 7 and 8.
Again, Figure 14, the graphs is more clear without arrows and it is explained in the text.
→ I am thankful for your comments. According to your kind comments, a few arrows shown in Figure 14 has been eliminated. Please see the Figure 14, Page 8.
Table1. Layout plays a major roles on power consumption (larger parasitics means more drawn power) but the size is given in arbitrary unit. More info should be given because is one of the major factor in what you are presenting.
→ Thank you for your comments. As you told me, the layout size has an important role to reduce power consumption, because the small layout size has lower parasitic elements. In this paper, however, the difference of layout size among the flip-flops was not so big. For example, the layout size of TGFF was 50um x 20um, namely 1000um2. That of the proposed DCSFF was 50um x 20.8um, namely 1040um2, while that of CSFF was 50um x 22.6um, namely 1130um2. Therefore, we just prepared the relative size of them in Table 1. We are very sorry to use the word of AU (Arbitrary Unit), but it has been eliminated in the revised version. Please consider it and see the Table 1, Page 9.
Author Response File: Author Response.pdf
Reviewer 4 Report
1. Authors mentioned drawbacks (mostly short circuit current problem) of previous flip-flops (TGFF, TSPCFF, S2CFF, CSFF) in introduction. However, it is difficult to understand about it. Can you please explain more in detail with using appropriate scenarios and Figures 1 to 4?
2. The proposed dual change-sensing flip-flop (DCSFF) reduces power consumption by eliminating a redundant transition compared to the change-sensing flip-flip (CSFF). When power consumption is compared, however, not only the flip-flop itself but also clock driver providing clock signal to the flip-flop should be considered. If the power consumption of the clock driver is higher because the clock node capacitance is bigger, then, it cannot say that the power consumption is reduced. In this respect, even though the DCSFF eliminates the reduntant transition, the number of transistors connected to clock signal is seven, whereas the number of transistors in case of CSFF is four. Thus, the DCSFF seems to consume more clock driver power compared to the CSFF. Please discuss it.
Author Response
- Authors mentioned drawbacks (mostly short circuit current problem) of previous flip-flops (TGFF, TSPCFF, S2CFF, CSFF) in introduction. However, it is difficult to understand about it. Can you please explain more in detail with using appropriate scenarios and Figures 1 to 4?
→ Thank you for your kind comments. According to your guide, more explanations and descriptions have been added and revised. Please see the blue and bold fonts from row #39 to row #60, Page 1 and 2.
- The proposed dual change-sensing flip-flop (DCSFF) reduces power consumption by eliminating a redundant transition compared to the change-sensing flip-flip (CSFF). When power consumption is compared, however, not only the flip-flop itself but also clock driver providing clock signal to the flip-flop should be considered. If the power consumption of the clock driver is higher because the clock node capacitance is bigger, then, it cannot say that the power consumption is reduced. In this respect, even though the DCSFF eliminates the redundant transition, the number of transistors connected to clock signal is seven, whereas the number of transistors in case of CSFF is four. Thus, the DCSFF seems to consume more clock driver power compared to the CSFF. Please discuss it.
→ I am really thankful for your comments. Your comment is right. As you told me, even though the DCSFF eliminates the redundant transition, the number of transistors connected to clock signal is seven, whereas the number of transistors in case of CSFF is four. However, all the transistors in those flip-flops are designed by the minimum transistor size. For example, the layout size of the proposed DCSFF was 50um x 20.8um, namely 1040um2, while that of CSFF was 50um x 22.6um, namely 1130um2. It means that the load of clock signal in case of DCSFF is almost the same as that of CSFF, even though the number of transistors connected to clock signals are different. Thus the power consumption caused by the clock driver is negligible, compared to the huge power consumption caused by the short circuit currents. From the chip experimental results, we could not check the difference of power consumption caused by clock drivers between DCSFF and CSFF. Please take it into accounts.
Author Response File: Author Response.pdf
Round 2
Reviewer 3 Report
You addressed all the weak parts of the paper, well done
Reviewer 4 Report
Thank you. I have no further question about this manuscript.
