Next Article in Journal
Quad-Band Circular Polarized Antenna for GNSS, 5G and WIFI-6E Applications
Previous Article in Journal
Performance Enhancement of Functional Delay and Sum Beamforming for Spherical Microphone Arrays
 
 
Article
Peer-Review Record

An Efficient Crypto Processor Architecture for Side-Channel Resistant Binary Huff Curves on FPGA

Electronics 2022, 11(7), 1131; https://doi.org/10.3390/electronics11071131
by Usama Umer 1,*, Muhammad Rashid 2,*, Adel R. Alharbi 3, Ahmed Alhomoud 4, Harish Kumar 5 and Atif Raza Jafri 1
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Electronics 2022, 11(7), 1131; https://doi.org/10.3390/electronics11071131
Submission received: 7 March 2022 / Revised: 24 March 2022 / Accepted: 28 March 2022 / Published: 2 April 2022
(This article belongs to the Section Circuit and Signal Processing)

Round 1

Reviewer 1 Report

The paper deals with a very interesting topic.

There are some issues that in my opinion have to be improved before the publication.

1 why a cryptoprocessor and not a hardware accelerator suitable for crypto operation?
In the literature, authors present several works in which the crypto computation is sped up using a hardware accelerator

 Cardarilli, G. C., Di Nunzio, L., Fazzolari, R., & Re, M. (2015). TDES cryptography algorithm acceleration using a reconfigurable functional unit. Paper presented at the 2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, 419-422. doi:10.1109/ICECS.2014.7050011


I think can be useful to clarify to the reader the difference between these two approaches
2) power consumption nowadays represents a crucial aspect. Is it possible to provide information about power dissipation?
3) Is it possible to put in evidence the performance of the proposed processor with respect to a MicroBlaze processor?
4) I suggest improving the literature analysis and comparison with it.

Author Response

The file is attached. 

Author Response File: Author Response.pdf

Reviewer 2 Report

This paper presents a cryptography processor for the binary Huff curves on FPGA. The following concerns need to be addressed.

  1. Tables 1, 2, and 3 are not readable enough. It would be better to one formula per row. They might be integrated into one table, where each of them is a separate column.
  2. The presented implementation seems to be rather straightforward, lacking of enough novelty.
  3. It seems that several previous architectures are better than the proposed one, limiting the contribution.
  4. How much BRAMs in FPGA were used in implementations?
  5. Is it possible to measure power consumptions of the architectures?
  6. Please present the throughput/slices metrics for Table 6.

Author Response

The file is attached. 

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Authors improve the article answering to the reviewers. For this reason I recommend the acceptance.

Reviewer 2 Report

The concerns have been addressed. Thank you.

Back to TopTop