A Wideband Low-Power Balun-LNA with Feedback and Current Reuse Technique

Abstract

This paper presents a low-noise amplifier (LNA) with single to differential conversion (Balun) for multi-standard radio applications. The proposed LNA combines a common-gate (CG) stage for wideband input matching and a common-source (CS) stage to cancel the noise and distortion of the CG stage. Using the proposed technique, a low noise figure (NF) is achieved while providing a wideband of operation. Furthermore, a feedback connection from the CS stage to the gate of the CG is employed to boost the transconductance of the CG stage ($g{m}_{CG}$), and an additional complementary transistor is applied at the CS stage using current reuse to increase the overall transconductance of the CS stage ($g{m}_{CS}$) without increasing the power consumed by the stage. This LNA was designed using TSMC 65 nm technology, and post-layout simulation results show operation across 0.5–5 GHz, a maximum power gain of 20 dB, 4 dB minimum NF, and third-order intercept point (IIP3) of −10 dBm while consuming only 5 mW of power from a 1.2 V supply.

1. Introduction

Wireless communication systems have evolved rapidly and are now among the most important aspects of daily life. Various wireless standards, such as Bluetooth, Wi-Fi, GPS, and 2G/3G/4G/5G cellular systems, use different frequency bands that require a transceiver that can operate with robust performance over a wide range of frequencies, while maintaining low power consumption, low occupied volume, good noise performance, and low cost [1].

Low-noise amplifier (LNA) as the first active block of the receiver system determines the receiver bandwidth and noise figure (NF) [2]. Trade-offs between input matching, NF, gain, bandwidth, and linearity should be considered in the design process. Single-ended LNAs lack sufficient power supply rejection and have limited second-order distortion performance. Therefore, differential signaling is preferable because of its robustness against power supply, substrate noise, and second-order distortion [3]. Single-to-differential conversion (balun) is required to convert a single-ended RF signal into a differential signal. However, off-chip passive baluns are typically lossy and narrowband; thus, several baluns are needed to accommodate wideband operation, which increases the overall cost. A well-known topology for broadband applications employs a common-gate (CG) common-source (CS) pair as an active balun. This topology provides high power gain and the ability to cancel thermal noise and distortion over wideband frequency ranges [3,4].

Previous studies on CG-CS topology [3,4,5,6,7,8,9,10,11,12] show that a balanced condition between the CG and CS stages is essential for the noise canceling condition. Furthermore, scaling between the transconductance of the CS stage ($g{m}_{CS}$) and the transconductance of the CG stage ($g{m}_{CG}$) also affects the NF performance [3]. To satisfy input matching, $g{m}_{CG}$ must be 20 mS. Thus, the drawback of this topology is its large power consumption, because $g{m}_{CS}$ needs to be significantly large to achieve better NF performance. Another critical issue is that the parasitic capacitances cause gain and phase imbalances due to the active circuit components. Previous work in [4] utilizes negative feedback from the source node of the cascoded CS stage to the gate of the CG stage. The voltage gain of the cascode CS stage is utilized to boost the $g{m}_{CG}$. The work in [5] improved the overall power consumption by employing negative feedback from the output of the CS stage to the gate of the CG stage, resulting in a higher effective $g{m}_{CG}$, reduced power consumption, and smaller size. Gain and phase imbalances can also be compensated using a passive capacitor between differential outputs. This technique is suitable for low-voltage applications, but its drawback is the headroom of the amplifier. Furthermore, the CS stage consumes a large amount of power because $g{m}_{CS}$ needs to be high for better noise performance. Other critical works in [6] and [8] proposed a balun CG-CS paired with the current reuse to further increase $gm/id$ efficiency but the trade-off between gain and bandwidth showed a marginal improvement factor. Authors in [12] proposed a CG-CS pair with the current reuse to decrease the power consumption and to improve the noise contribution of the CS stage as well, however the proposed design is just for a single-ended LNA and is not suitable for single to differential conversion.

This paper proposes a balun-LNA with CG-CS topology employing negative feedback on the CG stage and current reuse for the CS stage. Negative feedback utilizes the gain of the CS stage to increase $g{m}_{CG}$ for better input matching and to satisfy wideband operation. Current reuse is applied to increase the overall $g{m}_{CS}$ by adding a complementary transistor within the CS stage, resulting in higher transconductance scaling for better NF performance. Both negative feedback and current reuse keep the power consumption for the overall stages of the CG-CS topology low.

The remainder of this paper is organized as follows. Section 2 reviews the CG-CS active-balun topologies and their general properties. The analysis and properties of the current reuse technique are described in Section 3. The proposed LNA is described in Section 4, followed by a thorough analysis of its input matching, gain, and noise. Section 5 presents the simulation results of the proposed LNA, and conclusions are presented in Section 6.

2. CG-CS Active Balun Topologies

The circuit shown in Figure 1, proposed by [3], performs the balun operation over a wide frequency band and provides thermal noise cancelation of the CG stage, reducing the overall NF of the LNA. The input impedance of this topology is

$$Z_{in}=\frac{1}{g{m}_{CG}}·\left(1+\frac{R_{CG}}{rd{s}_{CG}}\right),$$

(1)

where $g{m}_{CG}$, $rd{s}_{CG}$, and $R_{CG}$ are the transconductance of $M_{CG}$, output resistance of $M_{CG}$, and load resistance of the CG stage, respectively. The input impedance of the LNA is approximately ${\left(g{m}_{CG}\right)}^{-1}$ if $rd{s}_{CG}$ is sufficiently large. Then, the input matching condition with an antenna’s impedance (typically 50 Ω) requires $g{m}_{CG}\approx 20 mS$; this limits the CG stage voltage gain and necessitates a relatively high bias current. The voltage gain of the LNA is

$$Av=g{m}_{CG}·R{o}_{CG}+g{m}_{CS}·R{o}_{CS},$$

(2)

where $R{o}_{CG}=R_{CG}\parallel rd{s}_{CG}$ and $R{o}_{CS}=R_{CS}\parallel rd{s}_{CS}$, and $g{m}_{CS}$, $R{o}_{CS}$, and $rd{s}_{CS}$ are the transconductance, resistance, and output resistance of the CS stage, respectively. The noise-canceling condition requires an equal gain for both stages with opposite phases. In addition, the scaling factor n between the two stages ($g{m}_{CS}=n·g{m}_{CG}$&$R_{CS}=R_{CG}/n$) reduces the noise contribution of the CS stage. Increasing n improves the NF of the LNA at the cost of increased power consumption. Perfect (balanced) conditions for noise-canceling are difficult to achieve because of the parasitic and process variations of passive devices.

3. Current Reuse Technique

The current reuse technique was applied to our proposed circuit to increase the overall transconductance without increasing the total power consumption. This technique is suitable for the CG-CS topology because a high $g{m}_{CS}$ is necessary for better performance. In this section, we analyze the transconductance, linearity, and output resistance of the proposed scheme. Figure 2 shows an inverter-type current reuse circuit as a general circuit topology.

3.1. Gm Calculation and Effect on Linearity

To calculate the transconductance ($G_m$), the output of the circuit is connected to the ground, as shown in Figure 2b. The total current sinked to the output ($I_{out}$) is

$$I_{out}=I_{o,p}-I_{o,n},$$

(3)

where $I_{o,p}$ and $I_{o,n}$ are the output currents of the PMOS and NMOS transistors, respectively. The overall transconductance $G_m$ is expressed as

$$G_m=\frac{\partial \left(I_{o,p}-I_{o,n}\right)}{\partial Vin}=g{m}_p+g{m}_n.$$

(4)

From Equation (4), $G_m$ is the sum of both the PMOS ($g{m}_p)$ and NMOS ($g{m}_n)$ transconductances. If both transistors are matched well, even-order distortions are canceled, leaving only the first-order (linear) term and higher odd-order components. The output current up to the third-order distortion terms is expressed as follows:

$$I_{out}=g{m}_p\left(-vin\right)+g{m}_{2,p}{\left(-vin\right)}^2+g{m}_{3,p}{\left(-vin\right)}^3-\left(g{m}_n\left(vin\right)+g{m}_{2,p}{\left(vin\right)}^2+g{m}_{3,p}{\left(vin\right)}^3\right),$$

(5)

$$I_{out}=-(g{m}_p+g{m}_n)\left(vin\right)+\left(g{m}_{2,p}-g{m}_{2,n}\right){\left(vin\right)}^2-\left(g{m}_{3,p}+g{m}_{3,n}\right){\left(-vin\right)}^3,$$

(6)

$$I_{out}\approx -(g{m}_p+g{m}_n)\left(vin\right)-\left(g{m}_{3,p}+g{m}_{3,n}\right){\left(-vin\right)}^3,$$

(7)

where $g{m}_{2,p/n}$, and $g{m}_{3,p/n}$ are second- and third-order nonlinear terms from the PMOS and NMOS transistors, respectively. Even though the third-order distortion component increased in Equation (7), the relative distortion with respect to the fundamental component is the same, and the third-order distortion component itself can be minimized by properly biasing both transistors.

3.2. Total Output Resistance

Figure 2c shows an equivalent small-signal model of the current reuse circuit. The drain-source resistance for both transistors is expressed by $Ro{,}_p$ and $Ro{,}_n$. To obtain the total output resistance, we null out any available input sources while injecting the test voltage source ($V_x$) into the output. Note that both inputs are grounded; thus, neither transconductance draws any current. Thus, the total current due to the test voltage ($I_x$) is

$$I_x=\frac{V_x}{R_{o,p}}+\frac{V_x}{R_{o,n}}=V_x\left(\frac{1}{R_{o,p}}+\frac{1}{R_{o,n}}\right),$$

(8)

$$R_{out}=\left(Ro{,}_p//R_{o,n}\right),$$

(9)

where $R_{out}$ is the total output resistance. This technique eliminates the usage of a resistor for the CS load in the CG-CS topology. Hence, the contribution of the resistor noise of the stage is reduced.

4. Wideband Balun-LNA with Feedback and Current Reuse Technique

Figure 3 shows the proposed wideband balun-LNA with the negative feedback for the CG stage and the current reuse technique for the CS stage. The CG stage provides input-matching and non-inverting signals at the CG output, whereas in the CS stage, the signal phase is inverted by $180°$. The output of the CS stage is fed back to the gate of the CG stage to increase the effective $g{m}_{CG}$ by the gain of the CS stage. Thus, the negative feedback connection relaxes the input matching condition without increasing the current of the CG stage or increasing the transistor size for a higher $g{m}_{CG}$. In contrast, the CS stage employs complementary CMOS transistors using current reuse. The gain of each stage is

$$A{v}_{CS}=(g{m}_{CS,n}+g{m}_{CS,p})·R{o}_{CS},$$

(10)

$$A{v}_{CG}=g{m}_{CG}\left(1+A{v}_{CS}\right)·R_{CG},$$

(11)

$$R{o}_{CS}=(g{m}_{CCS}rd{s}_{CCS}rd{s}_{CS,n}//rd{s}_{CS,p}),$$

(12)

where $A{v}_{CS}$ and $A{v}_{CG}$ are the gains of the CS and CG stages, respectively. Note that in (12), the CS stage output resistance $R{o}_{CS}$ is determined by the transconductance of the cascoded NMOS transistor $(g{m}_{CCS})$ and its output resistance $(rd{s}_{CCS},rd{s}_{CS,n}$) in parallel with the output resistance of the PMOS transistor $\left(rd{s}_{CS,p}\right)$. $R{o}_{CS}$ can be approximated as $rd{s}_{CS,p}$ because the cascoded NMOS transistor produces a much larger resistance at the CS output stage. The PMOS and NMOS transistors share the same current; therefore, the overall $G{m}_{CS}$ is effectively doubled.

4.1. Input Matching

Note that in (11), the CG stage transconductance is increased by a factor of $1+A{v}_{CS}$ due to the negative feedback employed from the CS stage output to the CG stage gate. Therefore, the input impedance of the proposed LNA can be approximated as

$$Z_{in}\cong \frac{1}{g{m}_{CG}\left(1+A{v}_{CS}\right)}//\frac{1}{s{C}_p},$$

(13)

It is clear from Equation (13) that the required $g{m}_{CG}$ for the matching condition is reduced significantly, allowing the CG stage to have lower current consumption and size. The parasitic capacitance $C_p$, which is determined by the input pad, transistor size of the CG and CS stages, and bias transistors, is also reduced owing to the proposed scheme.

4.2. Noise Analysis

The important property of the CG-CS balun-LNA topology is that the thermal noise of the CG transistor is fully canceled when the gains of the CG and CS stages are balanced. The NF of the proposed LNA employing feedback and current reuse is

$$NF=1+\frac{\gamma g{m}_{CG}·{\left(R_{CG}-R_S·g{m}_{CS}·R_{CS}\right)}^2}{R_S·A{v}_{diff}^2}+\frac{\gamma (g{m}_{CS,n}+g{m}_{CS,p})·R{o}_{CS}^2·{\left(1+g{m}_{CG}\left(R_{CG}+R_S\right)\right)}^2}{R_S·A{v}_{diff}^2}+\frac{R_{CG}·{\left(g{m}_{CG}\left(1+A{v}_{CS}\right)·R_S\right)}^2}{R_S·A{v}_{diff}^2},$$

(14)

where $A{v}_{diff}$ is the differential gain, which can be expressed as

$$A{v}_{diff}=A{v}_{CG}+A{v}_{CS}.$$

(15)

The second term is the noise contribution owing to the CG stage, and its contribution is fully canceled when the balanced gain condition is met. The third term is the noise contribution due to the CS stage, and its noise is spread among the PMOS and NMOS transistors, whereas the last term is the noise due to the CG stage load resistance. Equation (14) does not consider the current mirror noise contributions, which can be significantly smaller with the feedback scheme [4].

5. Simulation Results

The balun-LNA was designed using TSMC 65 nm technology. Its device dimensions and bias points are indicated in

Table 1. Device dimension and bias point.

Device	Dimension
MCG MCS,n, MCCS MCS,p MBias1 MBias2	10/0.65 μm
	32/0.65 μm 32/0.65 μm 2/0.65 μm
	4/0.65 μm
RCG RGate	280 Ω
	1.5 kΩ
Cc Cac1, Cac2 CF	10 pF
	1.2 pF
	5 pF

. The balun-LNA layout is illustrated in Figure 4. The total area of the chip is 475 × 366 μm, including the balun-LNA core, common-mode feedback for gain and phase imbalance compensation, buffer (source follower) to interface balun-LNA outputs to off-chip ports, and pads. The active area of the LNA core is only 150 × 150 μm. The PMOS and NMOS CS stages are designed to match each other such that the second-order distortion produced by the stage is eliminated. The CG stage is designed to match a 50 Ω input impedance ($g{m}_{CG}\left(1+A{v}_{CS}\right)=20 mS)$. As shown in Table 1, with a given transistor size, the CG stage only consumes 0.375 mA of current, in contrast with the conventional topology, which requires approximately 4 mA of current to obtain the same transconductance [2]. CS stage consumes the largest current in the overall stage by 3.7 mA. With the given size and bias condition, the transconductance of the CS stage is 2.5 times larger than the CG stage. The current reuse technique improved the $gm/id$ efficiency of the CS stage. Both positive output and negative output are sensed by common-mode feedback to ensure the stable gain and phase imbalance for robustness operation across PVT variation.

Figure 5 shows a post-layout simulation of the input/output impedance matching performance $(|S_{11}\left|/|S_{22}\right|$) and power gain $(|S_{21}|$) of the total circuit and core, where the effect of the buffer is de-embedded. The simulated $\left|S_{11}\right|$ and $\left|S_{22}\right|$ values are well below −10 dB over a frequency range of 0.5–5 GHz. The maximum power gain of the proposed Balun-LNA is 20 dB and the maximum power gain with the effect of the buffer is 13 dB, including the intrinsic 6 dB loss from the output matching. The buffer was designed with a source follower architecture and consumes 4 mA of current, which can be avoided in the receiver front end, where the LNA is driving the mixer on-chip [1].

Figure 6 shows the NF of the entire circuit (LNA core and buffer) and LNA core while de-embedding the buffer contribution, and the NF calculated from Equation (14) and designed device parameters is also shown. The calculated NF is 3.55 dB, while the LNA core shows an NF of 4 dB across the range of 0.5–2 GHz. The NF is increased in the post-layout simulation owing to the contribution of parasitic resistance, bias (current mirror), and other passive devices, such as R_Gate, which are not included in Equation (14). The CS stage provides the highest noise contribution for the LNA core, which is spread among the PMOS and NMOS transistors. With the buffer effect, the overall NF is increased by 0.8 dB owing to the contribution of the source follower and passive RC connection for high pass response. Within the frequency of operation, the NF for both the LNA core and the whole circuit shows favorable and stable results.

As mentioned in Equations (5)–(7), the current reuse technique affects third-order distortion performance. The distortion of the CG stage is also canceled along with the NF as long as both stages are in a balanced condition. IIP3 of the proposed LNA is mostly determined by the linearity of the CS stage itself. Linearity tests were performed using two different tones located at 2.4 GHz and 2.45 GHz (50 MHz spacing) (Figure 7a) and sweeping the injection tones from 0.5 GHz to 5 GHz with 50 MHz and 100 MHz tone spacing (Figure 7b). IIP3 of the LNA shows a minimum −12 dBm for both 50 MHz and 100 MHz tone spacing. Increased IIP3 across the frequency occurred due to lower gain at a higher frequency, which also reduces higher frequency harmonics.

Wideband LNA with noise-canceling ability has to offer stable performance against process, voltage, and temperature (PVT) variations. To ensure the robustness of the circuit, the core LNA is simulated across typical, slow-slow (SS), and fast-fast (FF) process corners at room temperature (27°) as well as different temperatures at −25°, and 80° Celsius as depicted in Figure 8. The power gain of the core LNA (Figure 8a,b) shows a maximum of 19 dB, 20 dB, and 20.7 dB for −25°, 27°, and 80° Celsius, respectively. This result shows an insensitive response of the proposed LNA against temperature variations. SS corner gives a maximum power gain of 18 dB, while FF corner gives 18.9 dB. SS corner affected the power gain at a higher frequency by 2 dB, while FF corner affected the gain at a lower frequency. However, both SS and FF corners are still showing high gain performance of the proposed LNA.

Input matching (Figure 8c,d) of the proposed LNA shows robustness against temperature variations. At −10 dB the point of low temperature shifted to 0.5–5.2 GHz, while high temperature shifted to 0.45–4.8 GHz. Furthermore, process corners are shifting the −10 dB point of the LNA by 0.4–3.3 and 0.65–8 GHz for SS, and FF corners, respectively. The noise figure of an amplifier is mainly determined by its white (thermal) noise performance. Therefore, the NF corner simulation (Figure 8e,f) of the proposed shows temperature dependency. NF at −25°, 27°, and 80° are 3.65 dB, 4 dB, and 4.3 dB, respectively. Process variations at the SS and FF corners (Figure 8e) increase the noise contribution in higher frequency and lower frequency, respectively. The minimum NF of the SS corner is 4.25 dB, while the FF corner is 4 dB. All of $\left|S_{21}\right|$, $\left|S_{11}\right|$, and NF corners simulation results show small variation which confirms that our design is robust against PVT variation.

Furthermore, Monte Carlo (MC) simulations with 300 samples were run for $\left|S_{21}\right|$ and NF to evaluate the stability (robustness) of gain and minimum noise figure against the statistical variations as shown in Figure 9. Both simulations were carried out across 0.1–10 GHz frequency. Maximum $\left|S_{21}\right|$ (Figure 9a) gives a mean of 19.55 and a standard deviation of 1.925. Minimum NF (Figure 9b) of the proposed LNA gives a mean of 3.998 dB and a standard deviation of 0.182 dB. NF that is lower than 4.2 dB is 93% of total samples. Both maximum $\left|S_{21}\right|$ and minimum NF show stable results across the mismatch and process variability.

In [13], the phase imbalance was required to be within ±5° to suppress local oscillator (LO) leakage by more than 25 dBc. The gain and phase imbalance between the positive and negative outputs for the total circuit is shown in Figure 10. The parasitic from the devices and interconnect routings is compensated with the aid of common-mode feedback. The gain and phase imbalance of the LNA is only 0.15 to −0.54 dB and 0.2° to −0.3°, respectively, over the frequency of operation (0.5–5 GHz). Both results show effective and stable operation for the noise canceling condition as well.

The overall performance of the proposed LNA and previous works for balun-LNAs is compared in

Table 2. Performance comparison table.

Parameter	This Work S	[3] M	[5] M	[6] S	[7] M	[8] M	[9] M	[10] M
Frequency [GHz]	0.5–5	0.2–5.2	0.1–2	0.21–1.1	1.2–2	0.13–0.93	0.1–1	3–5 *
Gain [dB]	20	15.6	16	24–30	16	16.6–19.6	14	30 *
Gain Imbalance [dB]	0.15–(−0.54)	0.7	0.5	2	0.6	-	1.4	0.4
Phase Imbalance [deg]	0.2–(−0.3)	2	5	15	7	-	-	1.8
NF [dB]	4–4.5	<3.5	3.8–5	2.8–3.8	3.8	3.6–5	4	3.6–4.3 *
IIP3 [dBm]	−10	>0	0.5	−13	-	>−8.5	2	−24 *
Power [mW]	5	21	3	5.58	9.2	3	2.7	19 *
Supply [V]	1.2	1.2	1.2	1.8	1.2	1.8	1.2	1.2
Area [mm2]	0.173 a	0.01 b	0.075 b	0.24 a	-	0.18 b	0.0992 b	0.734 a
Technology [CMOS]	65 nm	65 nm	130 nm	180 nm	65 nm	180 nm	130 nm	130 nm
FoM	6	1.19	2.87	5.6	0.39	2.11	1.11	2.59

^S: Simulated result; ^M: Measurement result; ^a: Total area; ^b: Active area; *: Measurement result including effects of buffer and active balun.

. Conventional CG-CS balun LNA topology [3] shows higher bandwidth and lower NF, but the power consumption is much higher than our design. Feedback CG-CS LNA without current reuse [5] has slightly lower power consumption, gain, and noise figure but exhibits much lower bandwidth than our work, which shows better power efficiency due to the proposed current reuse technique. The design proposed by [8] applied the same complementary NMOS/PMOS technique and has a high gain with low power consumption but gain and bandwidth are very limited due to the dependency of load resistance, compared to the bandwidth of our work which is significantly higher. LNA with active balun proposed by [10] has the highest gain among other designs but at the cost of linearity degradation and increased power consumption. For performance comparison, the following figure of merit (FoM) [14,15] is used, which is typically used for LNA and low noise circuits.

$$FoM=\frac{G_{max}\left[Lin\right].BW\left(GHz\right)}{P_{DC}\left[mW\right].\left(N{F}_{min}\left[Lin\right]-1\right)},$$

where $G_{max}$, BW, $P_{DC}$, $N{F}_{min}$ are maximum gain, bandwidth, power consumption, and noise figure, respectively. Our LNA-balun shows the highest FOM among other works. Our proposed design further shows a fine performance for wideband operation, gain, and noise with minimum power consumption.

6. Conclusions

A wideband low-power balun LNA employing negative feedback and current reuse was presented in this paper. In the proposed scheme, the gain of the CS stage is further utilized by employing a negative feedback connection to increase the effective $g{m}_{CG}$, providing better input matching, while a complementary PMOS transistor is applied at the CS stage using the current reuse technique to improve the overall $g{m}_{CS}$ for better transconductance scaling. The current reuse technique can also eliminate the second-order distortion produced by the CS stage. These techniques reduce the overall power consumption, while the wideband frequency of operation, high gain performance, and NF are well maintained.

The proposed LNA is designed using the TSMC 65 nm technology. Compared with the other balun LNAs listed in Table 2, our design shows a high gain and high bandwidth, while keeping NF and power consumption low. Without any on-chip inductor, the total area occupied by the circuit is only 475 × 366 μm.