3D Heterogenous Integrated Wideband Switchable Bandpass Filter Bank for Millimeter Wave Applications

Abstract

This article proposes a three-dimensional heterogenous-integrated (3DHI) switchable bandpass filter bank with two independent wideband filter channels that cover 26–40 GHz and 32.5–40 GHz, respectively. An accurate wafer-level process with a high hollowed ratio of the applied 8-inch high-resistivity-silicon (HR-Si) interposer wafers is presented to form both compact filter channels. Above the interdigital filter patterns fabricated on the bottom interposer wafer, deep cavities are etched in the cap interposer wafer to improve the quality factor of the filter bank. Besides the cavities, the cap interposer wafer is 35% hollow inside, which two bare dies of GaAs single-pole double-throw (SPDT) switches and two thin film resistors are attached to the bottom interposer after the wafer-to-wafer (W2W) bonding. To ensure good out-of-band performance, a 3D EM co-simulation of the switch layout at the chip level and filter patterns at the package level is applied. Measurement results show that the switchable filter bank achieves a high isolation of 50 dB and a competitive shape factor (BW_30dB/BW_3dB) of about 1.3. In addition, the size of the switchable filter bank is only 7.0 mm × 3.5 mm × 0.6 mm, and the weight is only 0.1 g.

1. Introduction

With the increasing trend of multiband and reconfigurability in modern microwave communication systems, switchable filter banks have attracted more and more attention. Commonly, switchable filter banks are designed in planar technology employing PIN diodes, FETs, microelectromechanical systems (MEMS) switches, and varactors [1,2]. To meet the requirement of high performance in wideband applications, more filter channels are integrated into one switchable filter bank module, which increases the module complexity and the package size of systems.

To address the above challenging issues, researchers focus on exploring different fabrication processes to improve the integration and compactness, including multilayer printed circuit board (PCB) [3,4,5], low temperature cofired ceramic (LTCC) [6,7], silicon wafer [8,9,10,11], and other materials [12]. Multilayer PCB is often considered a low-cost technology, but it still suffers from the low integration density of electronic systems and low isolation. LTCC shows remarkable RF performance, which has a minimal loss at microwave and high integration but provides limited quality factor. Advanced silicon-based processes are to achieve compact size, excellent quality factor, and adequate isolation. Therefore, the 3DHI process with HR-Si is promising to achieve these extraordinary performances.

In previous 3DHI switchable filter bank designs [8,9,10,11], switch chips are commonly embedded inside the HR-Si interposer cavities before interposer stacking. In addition, these works show good performances with multiple adjacent frequency bands and narrow band overlaps, which are mainly operated at several specific frequencies for active detection or known communication missions. However, for applications such as passive reconnaissance receivers, real-time passive detections of unknown ultra-wideband signals are performed. For regular filter banks with multiple adjacent bands, due to the band discontinuity, unknown vital signals in one band might be missed when the filter bank is shifting among other bands. Therefore, an ultra-wideband preselect filter channel is preferred with a large instantaneous bandwidth.

In this article, a generalized design of a 3DHI switchable bandpass filter bank for the passive detection of Ka band unknown signals is proposed with high integration, high isolation, and high shape factors. Two compact wideband filter channels with large band overlap are integrated by two stacked HR-Si interposer wafers, one of which covers an ultra-wideband of 26–40 GHz for around-the-clock spectrum surveillance and the other one covers a relatively narrow band of 32.5–40 GHz for vital radar signal reconnaissance with a large signal-to-clutter ratio. To approach high efficiency, low cost, and high process consistency, a wafer-level process adapted to a 35% hollowed 8-inch interposer wafer is presented, which is compatible with the following switch chip embedding process. To achieve high channel isolation, a 3D co-simulation of the switch layout at the chip level and filter patterns at the package level are presented.

The organization of this article is discussed as follows: In Section 2, a detailed design procedure and simulation results of the switchable filter bank are proposed. Subsequently, Section 3 illustrates the fabrication process. Section 4 presents measured results and the discussion. Section 5 concludes this article.

2. Design of Switchable Filter Bank

2.1. System Architecture

The proposed switchable filter bank consists of two SPDT switches and two bandpass filters (BPFs), as shown in Figure 1. For the SPDT switch, VEE is the −5 V DC supply pad, and V1 is the control signal pad, which selects two different filter channels with a TTL logic level of “0” (0 V) or “1” (5 V). When the state is “1”, filter channel 1 (26–40 GHz) is turned on. In this operating mode, the switchable filter bank works as an ultra-wideband preselect filter for around-the-clock spectrum surveillance with a 14 GHz instantaneous bandwidth. On one hand, the ultra-wideband covers most near-Earth communication bands (from 26–32.5 GHz), such as Starlink of the US [13] and Star Network of China [14], and on the other hand, it covers most Ka band radar spectrum (from 32.5–40 GHz) [15]. To improve the signal-to-clutter ratio of weak spectrum signals, filter channel 2 with a narrower bandwidth (32.5–40 GHz) is selected by changing the logic level to “0” for more important radar signal reconnaissance [16,17]. Within the limited filter bank dimensions, only the two filter channels mentioned above are integrated.

2.2. Bandpass Filter Design

Since typical unshielded or half-shielded resonators such as microstrip resonators have low-quality factors and inevitable channel crosstalk, this article employs two-layer HR-Si interposers with TSV fences and metal layers to create electromagnetic shielding and increase the quality factor of the filter bank, as shown in Figure 2. Above the metal filter patterns fabricated on the 200 μm-thick bottom interposer wafer, 200 μm-deep cavities are etched in the 300 μm-thick cap interposer wafer to further improve the quality factors. Due to the advantages of a compact structure and a wide range of design parameters, a short-circuited quarter-wavelength interdigital filter topology is used to design both filter channels [18,19]. Considering the tradeoff between the high shape factor and compact size of the filters, the Chebyshev lowpass prototype filter is selected for both filters with the filter order n = 13, and the element values $g_j$ can be obtained. The coupling coefficient $k_{j,j+1}$ and the external quality factor Q of the filter can be calculated using the following equations [20]:

$$k_{j,j+1}=\frac{FBW}{\sqrt{g_j{g}_{j+1}}}$$

(1)

$$Q_{e1}=\frac{g_0{g}_1}{FBW} Q_{en}=\frac{g_n{g}_{n+1}}{FBW}$$

(2)

where FBW is the fractional bandwidth of the designed filter.

After deducing the initial physical parameters for the interdigital bandpass filter, including the coupling space and the widths and lengths of resonators, the filter structure is modeled and optimized using HFSS. By adjusting the widths of the 1st and 13th resonators and the tap-in positions, terminal matching is improved to achieve ultrawide operational bandwidths. The optimized geometry parameters shown in Figure 2 include: w1 = 0.2 mm, w2 = 0.154 mm, w3 = 0.15 mm, w4 = 0.154 mm, l1 = 0.809 mm, l2 = 0.711 mm, l3 = 0.761 mm, l4 = 0.663 mm, s1 = 0.039 mm, s2 = 0.061 mm, s3 = 0.066 mm, s4 = 0.069 mm, s5 = 0.07 mm, s6 = 0.071 mm, s7 = 0.073 mm, s8 = 0.126 mm, s9 = 0.136 mm, s10 = 0.146 mm, s11 = 0.151 mm, and s12 = 0.151 mm.

Figure 3 shows the simulation results of bandpass filter channel 1 (26–40 GHz) and bandpass filter channel 2 (32.5–40 GHz). For filter channel 1, the insertion loss is less than 2.6 dB at 33 GHz, the return loss in the passband is higher than 10 dB, and the stopband rejection is greater than 40 dBc at the frequency range below 22 GHz and above 43 GHz. For filter channel 2, the insertion loss is less than 4.1 dB at 36 GHz, the return loss in the passband is higher than 10 dB, and the stopband rejection is greater than 40 dBc at the frequency range below 28 GHz and above 43 GHz.

2.3. Codesign of Filter and Switch

The constructure of the switchable filter bank is shown in Figure 4. Two bare dies of GaAs SPDT switches are mounted on the bottom interposer within the hollowed region of the cap interposer. For channel selection in this design, a GaAs pHEMT switch (G7803, Zhejiang Chengchang Technology, Hangzhou, China) is utilized. It shows a typical insertion loss of 1.5 dB, a low switching time of less than 20 ns, and an isolation of around 35 dB.

Switches and filter channels are connected through wire bonding. Considering the increasing parasitic coupling and crosstalk in the millimeter wave band, when co-designing the switchable filter bank, it is necessary to consider the isolation degradation between input and output terminals and between the two filter channels.

Commonly, in order to obtain the performance of a filter bank, S-parameters from both the circuit simulation of the switch chip and the EM simulation of the filter channels are achieved, and then the cascaded S-parameters are calculated. However, in this design, the control signal pads of the two SPDT switches are connected, which may cause weak crosstalk between the two RF terminals through the control signal line. Considering the high out-of-band rejection requirement of this work, crosstalks located in the rejection bands are unacceptable. Therefore, to ensure good out-of-band performance, a 3D EM co-simulation of the switch layout at the chip level and filter patterns at the package level is applied. For simplification, active transistors in switch chips are treated as short to ground for the “Off” state and open to ground for the “On” state. Weak but non-negligible crosstalk is found at 48 GHz when filter channel 2 (32.5–40 GHz) is selected. The E-field distribution of the crosstalk by the 3D EM co-simulation is shown in Figure 5a. To better show the path of the weak crosstalk, the color bar of the E-field is limited to 1 × 10⁵ V/m. To alleviate the crosstalk between the input and output terminals of the filter bank, two 100 Ω thin film resistors are implemented in series between the V1 pads of each switch.

Figure 6 illustrates the switchable filter bank’s simulation results with and without the resistors. It can be observed that the stopband rejection has improved from 30 dBc to 45 dBc. Although grounded TSV fences are set between the two filter channels to achieve a high level of channel isolation, slight RF signal leakage still exists through the two SPDT switches. Especially when filter channel 2 (32.5–40 GHz) is turned on, RF crosstalk exists through switches and filter channel 1 (26–40 GHz). As a result, stopband rejection ranging from 26 to 32.5 GHz in channel 2 degrades and can be treated as channel isolation for the switchable filter bank. Figure 6 shows that up to 60 dB of channel isolation can be achieved.

3. Fabrication Using Wafer-Level 3DHI

To realize the above two-layer interposer design with a high-efficiency, low-cost, and high-consistency wafer-level process, the following 3DHI process adapted to a 35% hollowed 8-inch interposer wafer is presented, which is compatible with the followed switch chip embedding process. The distribution map of the hollowed regions and cavities on the wafer is shown in Figure 7. The process of each interposer wafer and the assembly of the two-layer interposer structure will be discussed below in detail.

3.1. Cap Interposer Wafer

Figure 8 shows the main fabrication process steps for the cap interposer. At first, a 677 μm HR-Si wafer with a resistivity of around 3000 Ω·cm is given. A lithography step is performed using a positive-tone photoresist to specify the location of the TSVs. After lithography, φ60 μm × 300 μm TSV is formed on the wafer by a deep reactive ion etching (DRIE) process based on a modified BOSCH process [21]. Then, TSVs are deposited with a 2 μm SiO₂ layer and followed by physical vapor deposition (PVD) sputtering to give nominal thicknesses of 0.5 μm Ti and 3 μm Cu, which work as a barrier/seed layer. In the next step, TSVs are filled by combing the conformal electroplating process and the bottom-up electroplating process. To level the copper filling with the surrounding wafer surface, Cu and Ti are removed with chemical-mechanical polishing (CMP). After the TSV formation, the Cu re-distributed layer (RDL) is finished using the Ni/Cu/Au electroplating process. After the front-side processing of the interposer wafers is completed, a support wafer is bonded using temporary adhesive bonding. The silicon must be ground to the remaining thickness of the TSV depth so that the backside of the wafer can be reached.

In the following fabrication steps, the 200 μm-deep cavity is etched using DRIE from the reverse side. After oxide deposition, Cu RDL is completed using the Cu electroplating process. In addition, the most challenging part of this construction of the cap interposer is to form the 300 μm-deep hollow, which is 35% of the whole cap wafer. The hollowing etching process is similar to the cavity etching process, but the amount of photoresist in various places must be properly regulated. In addition, the photoresist on the bottom of cavities must be thick enough to avoid over-etching. At the end of the process, the cap interposer is finished with support wafer debonding and wafer cleaning.

Figure 8. Process flow of the cap interposer wafer.

Figure 8. Process flow of the cap interposer wafer.

3.2. Bottom Interposer Wafer

The main fabrication steps for the bottom interposer are depicted in Figure 9. The Bosch process is applied to etch the φ30 μm × 200 μm TSVs. After TSVs are filled with Cu, the excess copper is fully removed, leaving the copper-filled blind holes’ surface flush with the wafer’s surface. Then, Cu RDL is finished by using the Ni/Cu/Au electroplating process. When the front-side processing of the interposer wafers is completed, temporary adhesive bonding is used to affix a support wafer. In the following fabrication steps, the same procedure is used to treat the opposite surface [22].

3.3. Interposer Wafer Stacking

Following the fabrication of the two interposers, the 35% hollowed cap interposer wafer is stacked onto the bottom interposer wafer to form the filter bank with the wafer-to-wafer (W2W) bonding process. The total thickness variation (TTV) of the wafer is a crucial indicator of W2W bonding, which is normally confined to 1 μm or less. In the fusion bonding procedure, Sn is initially heated to generate metal compounds with copper. The stability of the produced alloy heavily depends on the Sn layer thickness and bonding time. Certainly, the alloy is also impacted by the bonding temperature. With the low heating rate, the melting of Sn is incomplete, and the alloy layer bubbles. On the other hand, when the heating temperature is excessively high, it is simple for Sn to overflow. To avoid RF performance degradation, the offset of the two interposer wafers is controlled to be less than 5 μm.

After W2W bonding of the two interposers, two bare dies of SPDT switches are attached by utilizing conducting resin, as shown in Figure 10. Subsequently, wire bonding is employed as the interconnection between embedded bare dies and interposers. Additionally, the fabrication process is finished after wafer dicing. Compared to the design in [9], W2W bonding of the two interposers is conducted before switch chip embedding and wire bonding, which can effectively increase the product’s yield and reliability.

4. Measured Results and Discussion

Based on the above process, the switchable filter bank is fabricated. Figure 11a,b show the HR-Si cap and bottom interposer wafers. Figure 11c,d show the photo and the X-ray image of the switchable filter bank. The overall size is 7.00 mm × 3.50 mm × 0.60 mm, and the weight is 0.1 g.

The S-parameters of the switchable filter bank are measured using a semiconductor parameter analyzer (B1500A) and a vector network analyzer (N5247B) with 150-μm-pitch ground-signal–ground (GSG) RF probes. As shown in Figure 12, the test results of the two filter channels show that the passband return losses are both larger than 10 dB, which are in close agreement with the simulation results. The measured insertion losses are 4.8–6.9 dB for filter channel 1 (26–40 GHz) and 6.3–8.1 dB for filter channel 2 (32.5–40 GHz). The insertion loss degradation and frequency deviation are mostly attributed to nonideal material losses and fabrication tolerance. Based on our analysis, sparse SiO₂ deposition by PECVD in the fabrication process is most likely the dominant factor for the insertion loss degradation and frequency deviation. To verify the issue, GCPW lines with different lengths fabricated on redistribution layers 3 and 4 are simulated and measured to fit the material parameters. When the optimized relative dielectric constant and loss tangent of the 2 μm-thick SiO₂ layers are approaching 3 and 0.02, respectively, the best fitting is achieved. Furthermore, these corrected material parameters are applied to the simulation of the switchable filter bank. The simulated, modified, and measured results of the filter bank are shown in Figure 12. The modified simulation results are in close agreement with the measured ones. The stopband rejection of filter channel 2, which ranged from 26 GHz to 32.5 GHz, is treated as the channel isolation of the switchable filter bank, which is more than 50 dB. It is worth noting that the competitive shape factors (BW_30dB/BW_3dB) of the two filter channels are (43.1–24.1 GHz)/(40.7–25.7 GHz) = 1.27 and (42–31 GHz)/(40.5–32.2 GHz) = 1.33, respectively.

Table 1. Comparison with previous works.

Ref.	Passband (GHz)	Insertion Loss (dB)	Return Loss (dB)	Isolation (dB)	Relative BW3dB	Shape Factor (BW30dB/BW3dB)	Process	Size $({\mathit{\lambda }}_{\mathit{g}}\times {\mathit{\lambda }}_{\mathit{g}}\times {\mathit{\lambda }}_{\mathit{g}}) *$
[8]	18–20	9	10	40	13%	1.6	HR-Si based 3DHI	$1.84 \times 1.60 \times 0.10$ $\left(0.29{\lambda }_g^3\right)$
	20–24	7	11		21%	1.3
	24–28	7	11		18%	1.3
	28–32	8	10		17%	1.3
	32–36	9	11		13%	1.3
	36–40	9	10		12%	1.3
[10]	6–8	6	12	40	31%	1.3	HR-Si based 3DHI	$0.80 \times 0.44 \times 0.04$ $\left(0.02{\lambda }_g^3\right)$
	8–10	6	13		29%	1.3
	10–12	6	15		25%	1.3
	12–14	6	14		21%	1.3
	14–16	7	10		17%	1.4
	16–18	10	10		15%	1.4
[12]	57–66	9	12	/	16%	/	Quartz with gold layer	/
	71–86	5	8		14%
[5]	11–13.5	4.3	13	/	23%	1.3	PCBs with metal package	$5.35 \times 3.41 \times 1.76$ $\left(32.10{\lambda }_g^3\right)$
	12.8–15.7	4.4	10		22%	1.4
	14.5–17.5	4.6	12		21%	1.5
	16.3–20	4.7	11		23%	1.5
This work	26–40	6.9	10	50	45%	1.3	HR-Si based 3DHI	$0.77 \times 0.39 \times 0.07$ $\left(0.02{\lambda }_g^3\right)$
	32.5–40	8.1	10		23%	1.3

* ${\lambda }_g$ indicates the wavelength at the central frequency of the switchable filter banks.

summarizes the performance comparison to previous works on switchable filter banks. The designed filter bank in this article shows ultra-wide bandwidth and a competitively small shape factor in millimeter-wave with minimal compact size.

5. Conclusions

In this article, a switchable bandpass filter bank that covers 26–40 GHz and 32.5–40 GHz is designed and implemented with a 3DHI process. Compact wideband filter channels are integrated by two stacked HR-Si interposer wafers with cavities, TSV fences and metal layers to create electromagnetic shielding and increase the quality factor of the filter bank. A wafer-level process adapted to a 35% hollowed 8-inch interposer wafer is applied, which is compatible with the followed switch chip embedding process. The test results show good agreement with the simulation results and achieve a competitive shape factor of about 1.3. Assisted by the 3D co-simulation of switch layout at chip level and filter patterns at package level, more than 50 dB of isolated channels are measured. The provided fabrication process is promising for millimeter wave communication applications.