Sidewall Modification Process for Trench Silicon Power Devices

Abstract

In this study, trench sidewall modification processes were designed to improve profile uniformity and thereby enhance the electrical performance of silicon power devices in large-scale production. The effects of trench sidewall modification on the morphology, structure and electrical properties were studied. Plasma-induced damage in etching processes was also observed and briefly explained. Straight and smooth sidewall profiles were achieved through adjusting the SF₆/CHF₃ proportion in a combined etchant gas flow in the main etching procedure. By comparing HRSEM images from different etching protocols, it was evident that an enhanced CHF₃ flow formed a proper passivation of the sidewall, eliminating the ion damages that are common in current main etch steps. To address the impurities introduced from the etchant gas and improve the gate oxide uniformity, further steps of depolymerization were applied in a plasma asher chamber, followed by wet clean steps. In the meantime, the plasma-induced charge accumulation effect was reduced by UV curing. Improved trench sidewall profiles and the gate oxide uniformity contributed to a lower leakage current between the gate and source terminals, leading to an overall yield enhancement of device properties in large-scale silicon wafer fabrication.

1. Introduction

As with rapid developments in consumer electronics and electric vehicles, silicon power devices play an increasingly crucial role [1]. Compared with silicon planar devices, which were the main application devices, trench structures enable a much smaller drain on resistance (Rdson) for the same chip area, significantly reducing overall conduction losses [2,3]. As the key stage in silicon power MOSFET manufacturing, trench etching processes directly influence the effect of subsequent processes as well as device performance. Ideal etching processes exhibit the following characteristics [2,4]:

• Anisotropic etching that requires a surface reaction to proceed in only the vertical direction without lateral undercutting. In this way, we are able to ensure that the exact same geometry as on the resist is accurately replicated on the etched film;
• Good etching selectivity that permits the etching rate of the resist, used as a mask, and the layer below, such as SiO₂ or Si₃N₄, to be much smaller than the etching rate of the etched film; this ensures the effectiveness of resist masking during the process by avoiding potential damages to other materials beneath the film from over-etching;
• Large batch processing with reliability and reproducibility, low cost and minimal environmental pollution, as are the requirements for production on an industrial scale.

Moreover, silicon etching of devices has high requirements for the accuracy of etching topography under high control precision. The Bosch process has been applied in the fabrication of deep-trench devices such as MEMS devices and silicon photodetectors [4,5,6]. The advantages of the Bosch process are its high etching verticality and excellent rate uniformity, as well as a high ratio and good repeatability. However, the Bosch process will inevitably form scalloped wrinkles on the sidewalls, which will affect the polysilicon backfill process and lead to device breakdown. Researchers have attempted a variety of methods to eliminate sidewall scallop wrinkles, but these methods are difficult to apply to the trench etching process of power devices due to possible contamination by metal ions or complicated processes and insignificant effects [7]. Inductively coupled plasma (ICP) etching is another common etching method that is compatible for Spilt-Gate trench (SGT) devices in terms of its large depth/width aspect ratios [8]; however, the sidewall topography requirements for the 5:1 aspect ratio required for trench power devices are hardly met.

Reactive-ion etching (RIE) with a directional etching process that utilizes ion bombardment to remove material has been adopted for low-voltage silicon device fabrication, and previous investigations regarding etching processes have concentrated on its relationship to process parameters, such as gas flow rate, temperature and pressure [9]. Reactive free radicals generated from F-, Cl- and Br-based etching gases react with silicon to easily form vaporized species [10]. Layers of polymer films condensed by etching gases and side products on the surface of the side wall reduce the lateral etching to a certain extent. A dynamic equilibrium established between vertical processes and lateral polymerization gives rise to a smooth sidewall profile control [11]. However, large-scale wafer production could involve much more reactant gases, such as HBr, CHF₃ and O₂, and the temperature and radio frequency (RF) power should also be taken into consideration [4]. In this case, we studied the effects of various etching atmospheres on the trench silicon structure to obtain a smooth sidewall profile and uniform interface between gate oxide and silicon, aiming to determine the relationship between trench etching process parameters and morphology and the silicon power device electric parameter. Furthermore, we found that a SF₆-rich etching atmosphere and plasma-induced charge accumulation effect caused a jagged sidewall morphology that plays a critical role in the current leakage between the gate and source terminals. By using an optimized dry etching and wet polymer removal process, uneven sidewalls and gate oxide current leakage can be effectively solved, and such pathways also illustrate a reliable solution for fabricating high-yield, low-voltage, trench structure power devices.

2. Methodology

The silicon trench fabrication process is illustrated in Figure 1. Prior to the silicon etching process, hard mask (HM) deposition and a lithography process (critical dimension: 0.3 μm) were conducted using a phosphorus-doped silicon epitaxy wafer (725 μm, 8 inches) as the substrate. To evaluate the sidewall uniformity of the silicon trench, the etching process was divided into main etching and over etching steps to form the silicon trench and bottom rounding effect.

To further investigate the electric properties, a simulation of the fabrication of a low-voltage trench silicon device is illustrated in Figure S1. For sample fabrication, HM removal and sacrifice oxide removal were conducted after the trench etching procedures, the trench structure was filled with 600 A gate oxide and 8000 A doped poly-silicon. After the oxide interlayer dielectric SiO₂ was formed (PECVD, 7000 A), contact hole opening (CD: 0.35 μm) and metal deposition were performed. The silicon wafers were ground to 200 μm to lower the drain-source on-state resistance; the backside electrode Ti/Ni/Ag was thermally evaporated with thickness of 1.2 K/2.5 K/10 K angstrom, respectively. HRSEM was used to observe the cross-section morphology of the silicon device samples after focus ion beam (FIB) preparation. The I-V test system was used to examine electrical parameters, such as Vth (threshold Voltage), IGSS (gate-source leakage current) and IDSS (drain-source leakage current); the detailed information is listed in Figure S2.

3. Results and Discussion

Figure 2a shows a schematic of the trench MOSFET device structure. The source, drain and gate are marked with blue, orange and pink color, respectively; the electron movement direction is also marked with pink color. When positive voltage is applied between the gate and source, a vertical channel is formed in the area adjacent to the P- base and gate. The electron will move from the gate oxide to the drift area and will finally flow vertically through the interior of the wafer to drain into the electrode. It can be seen that the width of the gate is much smaller than that of a vertically conducting planar structure and, therefore, has a smaller cell size and a lower on-state resistance. Figure 2b illustrates the SEM image of the source and gate area; for the source area, the top metal (AlCu) is connected with the N+ region through contact via the hole, gate oxide and gate (doped poly-silicon), which are isolated by interlayer dielectric (ILD).

There are multiple factors that should be considered in silicon etching processes to form trench structures [10,12]. Etching radicals could react with Si and SiO₂ due to the absence of photoresist blocking at this stage, as illustrated by the formulas below:

SF₆ + Si → SiF (gas) + S

(1)

CHF₃+ Si → SiF (gas) + S

(2)

CF₄ + Si → SiF (gas) + C

(3)

C₄F₈ + SiO₂ → SiF (gas) + CO₂ (gas)

(4)

Unlike the isotropic process of wet etching, silicon dry etching on low-voltage devices focuses on the <100> plane only. Fluorine- and chlorine-based etching gases react with silicon substrates with high etching selectivity. The impact of HM SiO₂ on etching parameters, the ultimate profile and electrical performances are not considered here in spite of the losses of SiO₂ in this stage due to HM removal after the completion of the etching processes.

3.1. Initial Etching Process

Initial attempts regarding trench etching processes include the breakthrough (BT) step that removes the surface oxides and organic impurities, followed by the main etch (ME)1 and ME2 steps, which are used to form ideal profiles by utilizing the high-efficiency vertical direction. The specific parameters are listed in

Table 1. Etching process parameters for the initial protocol.

Step	Pressure (mTorr)	RF_UP(W)	RF_BIAS(W)	Time (s)	Gas Flow Rate (sccm)
Breakthrough	4	400	40	20	50 CF4
Main Etch 1	4	800	150	130	150 HBR/20 SF6/10 O2
Main Etch 2	25	500	60	20	60 SF6/30 CHF3/100 O2
Rounding	15	1000	0	10	75 CF4/15 O2

.

After the completion of the silicon trench etching stage, the uppermost SiO₂ HM layer is removed in order to generate gate oxide. Figure 3a shows an HRSEM image of the cross section of a low-voltage silicon trench MOSFET device. An extensive jagged morphology was observed between the gate oxide and silicon interface, demonstrating an uneven distribution of gate oxide thickness. The gate oxide thicknesses of different regions in the trench structure are shown in Figure 3b; the upper region of the trench presented a gate oxide thickness of about 60 nm, but the bottom region only had a thickness of 35 nm. The average thickness of the upper trench region was nearly twice that of the bottom of the trench; the range of thicknesses between each individual region was significant with a gate oxide homogeneity of over 10%. In addition to the HM and sacrifice oxide wet removal processes, which might consume silicon on the top corners of the trench, varied gate-oxide thicknesses could be contributed to gate–oxide formation steps; however, a jagged morphology with uneven thickness could easily be a gate-oxide curvature near the bottom part that could easily cause a breakdown or current leakage [13]. Specifically, plasma-accelerated ions collided with the trench sidewall at a small angle and were reflected to the bottom corners of the sidewall. To examine the microscopic damage, Figure S3 shows the cross-section SEM images using the protocol from Table 1; the interface between the polysilicon and gate oxide showed a jagged morphology that matches the result from Figure 1. The microscope damage may be related to the thickness deviation of hundreds of angstrom in the gate oxide producing an electron shading effect [14,15]. The sheath potential accelerates the ions straight down to reach the bottom of the trench, preparing the area for efficient etching by neutral chlorine atoms. However, the electron charges at the top of the trench, if asymmetric, can distort the ion trajectories so that the ions hit the bottom sidewalls, imparting a positive charge on them. This will result in the formation of a self-consistent distribution of potentials and ion orbits. The charging of the sidewalls will not be symmetrical if the features are not all the same size.

Figure S2 illustrates the bin-map distribution of the yield results for the device and shows that more than 35% of the total cells failed to reach the threshold, especially for the IGSS parameter. The majority of failed dies were distributed in the marginal region of the wafer, which may be related to the etching process [16]. IGSS and Vth tests could elucidate the gate oxide properties by further investigating the relationship between etching protocols and device electrical performances. Figure 4 illustrates the IGSS curve, showing a rising trend with increasing voltage. When the voltage approached 10 V, the current exceeded the threshold of 100 nA [17].

Figure 5 shows the threshold voltage measurements under the test condition Vgs = 0 V; the current significantly surged as voltage exceeded 0.5 V, demonstrating a low Vth that failed to meet the device requirements. Poor-quality gate oxide may be caused by plasma charging during the etching process. The physical effect of dry etching refers to the bias between the silicon wafer and the plasma, which will accelerate the particles to effectively bombard the silicon wafer surface. Plasma may destroy the surface structure of the wafer since the silicon surface is negatively charged during the etching reaction. Unlike planar MOSFET structures that consider the RF displacement current directly damaging the surface of the gate oxide, ion and electron currents can be collected by a polysilicon gate electrode which works as antenna and the gate oxide layer can be seen as a capacitor. When more and more charge is collected on the gate, the gate voltage increases, eventually causing FN tunneling through the gate oxide. Electron flux balances the loss of positive ions in the plasma region during each RF cycle. At an ideal homogeneous plasma condition, the ion and electron currents are locally balanced over individual RF cycles leading to the surface potential being close to the substrate potential. For a non-uniform plasma distribution scenario, the electron and ion currents are not in a local overall net equilibrium near the electrodes; the presence of net plasma currents leads to local charging on the surface. Polished silicon wafer substrates show a continuous trend with uniform potential; however, the trench and gate terminals are separated and discontinuous. The gate electrodes at different locations have different potentials, and plasma could induce charge accumulation on the trench sidewall and bottom regimes. Charges accumulating on the sidewalls and surface of the trench under the etching atmosphere could lead to damage at the layer interface. The fundamental cause of sidewall interface damage is the uneven distribution of positive ions and electrons when the plasma is generated. The process of releasing a charge is more difficult using high level electronegativity gases, such as SF₆ and CF₄, which aggravate the non-equilibrium charges in the non-conductor [5,18]. The F-N current effect will occur when the charge accumulates to a certain extent on the surface, which leads to gate oxide layer damage.

Further, a high etching rate at the corner and sidewall with a low etch rate towards the center may cause an uneven sidewall, which has been reported to occur with chemical etching [19]. Higher temperatures cause a higher sidewall etching rate and lower polymer deposition rate, leading to sidewall erosion and undercut profiles.

3.2. Depolymerization and Polymer Removal

Experiments with modified parameters, such as pressure, RF power and temperature, were attempted to reduce the jagged morphology; the results are shown in Figure S4. However, little obvious elimination of plasma damages was observed.

Table 2. Etching process parameters by adding a UV curing protocol.

Step	Pressure (mTorr)	RF_UP (W)	RF_BIAS (W)	Time (s)	Gas Flow Rate (sccm)
Breakthrough	4	400	40	20	50 CF4
Main Etch 1	4	800	150	130	150 HBR/20 SF6/10 O2
Main Etch 2	25	500	60	20	60 SF6/45 CHF3/100 O2
Rounding	15	1000	0	10	75 CF4/15 O2
UV curing	4	300	0	60	200 O2/10 N2/8 H2

shows the updated etching and UV curing protocol. The polymer removal protocol consisted of the following steps: dilute HF (100:1) for 120 s, SC1(NH₃•H₂O:H₂O₂:H₂O = 1:5:100) for 180 s and diluted NH₄F (10:1) for 100 s.

Figure 6 shows the HRSEM image as a result of using the etching protocol from Table 2. The accumulation of electrical charges could be neutralized by UV light after each etching rounding step; additionally, the side products generated during the etching processes could attach to the inner trench wall and polymerize. The following steps will suffer from an uneven formation of gate oxides without sufficient cleaning. A polymer removal protocol is an option to solve these issues.

Figure 7 shows the IGSS curve using the etching protocol from Table 2; the slope depicts the I_GS value rapidly increasing with a small amount of V_GS. However, even with the rising trend, the value of the current stayed below the threshold of 100 nA.

Varied reactant gas flow rates and the resulting changes in constituent ratios could also lead to a reduced jagged morphology besides the aforementioned causes. The electronegativity of CHF₃ is not strong, helping with sidewall passivation; the effective ratio of CHF₃ and SF₆ can balance a vertical etching function and sidewall protection that induces uniform sidewalls. The ideal inclination angle of the trench structure is 85–89° in order to match the subsequent deposition of sacrificial oxide and gate oxide. In addition, oxygen is introduced in UV curing steps to react with the C and H polymers generated by etching and attached to the sidewall, which plays a cleaning role.

3.3. Updated Main Etching Protocol

Table 3. Etching process parameters by the updated main etching protocol.

Step	Pressure (mTorr)	RF_UP (W)	RF_BIAS (W)	Time (s)	Gas Flow Rate (sccm)
Breakthrough	4	400	40	20	50 CF4
Main Etch 1	4	800	150	130	150 HBR/15 SF6/10 O2
Main Etch 2	25	500	60	20	55 SF6/45 CHF3/100 O2
Rounding	15	1000	0	10	75 CF4/15 O2

shows the updated protocol by changing the main etching parameters; the SF₆ gas flow rate was set lower than described in the protocols in Table 1 and Table 2, which helped to further decrease the jagged sidewall morphology.

Figure 8a shows the device HRSEM image as a result of using the etching protocol from Table 3, in which the uniformity of the gate oxide was improved with thicknesses around 400 A to 450 A. A threshold thickness of 300 A has been noted to avoid device voltage breakdown, which is well below the thicknesses in our study [20]. The following sequences, such as etching of the rounding steps, the smooth bottom of the sacrifice oxide protocol and the subsequent gate oxide protocol can be optimized to further enhance the uniformity of the gate oxide. The value of the leak current corresponding to the IGSS was evidently lowered with the improvement of the flow process, remaining far below the threshold of 100 nA (Figure 8b). Figure 9 demonstrates the overall bin-map with multiple electrical parameters for the device. Bins that meet the minimum electrical requirements are colored in green. The overall yield of the devices was about 96.5%, which is a large improvement compared to the results in Figures S5 and S6. The failure areas were scattered in a random pattern, unlike the photolithography failure, where the failure areas in the same position across different shots were observed, or etching-related failure, where numerous outer rings were evident.

4. Conclusions

Herein, we described an optimization process for the etching trench sidewall profiles of silicon low-voltage devices. The different etching gas protocols showed a sidewall passivation gain improvement with an increased amount of CHF₃ and decreased amount of SF₆. After adding depolymerization and wet removal of the polymer attached to the etching reaction chamber, the gate oxide uniformity and electrical parameters of the device were significantly improved. The results suggest that UV curing could eliminate the plasma-induced charge accumulation effect, and the wet polymer removal process could reduce the by-products from the etching process. The optimized processes could be applied in trench-structure devices, such as trench photodiodes and trench-isolated LGADs.