Drift Resilient Frequency-Based Sensor Interface Architectures with Adaptive Clock Frequency

Round 1

Reviewer 1 Report

Referencing quite obvious statements (e.g. first paragraph of Instroduction section) is a little bit annoying. 

Consider unification of figures 1-3. Differential mode is shown in three different graphical ways - phase inversion (Fig 1), summer with Vcm (Fig. 2) and value labels (Fig. 3)

I found no mentions on irradiation experiments - consequently announcing study of TID impact in the abstract is unapproporiate. Maybe mismatch phenomena after irradiation are similar to that of VT variation, maybe not... Generally - the abstract should be more specific and probbably shorten -to point out particular contribution only, not the state of the art

Table 4. Since the paper describes concept and experimental data for actually two implementations - both deserve a column in this comparison. On the other hand I would suggest further expansion and comparing with results obtainted by other research groups

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

The paper proposes two different architectures for compensated sensor interfaces to reduce offset errors due to environmental changes in harsh conditions, such as high radiation.

The paper is well presented, with sufficient background and introductory information.

The development of the architectures, their working principles, and their mathematical derivations are well explained.

The experimental verification of the performance of the architectures is adequately described, an analysis of the results is included, and the conclusions extracted from them are coherent.

Author Response

The authors would like to thank the reviewer for taking the time to read through our paper and give valuable feedback and insights about our paper. 

Reviewer 3 Report

Dear Authors, these are my comments about this research, 

The authors describe that the developed concept was implemented in FPGA, , however no evidence of this is shown, or at what level it was implemented, it was done using VHDL.

I request that all acronyms be expounded upon when they are initially mentioned. I recommend avoiding the utilization of figures within the introductory section.

Multiple architectures are proposed; however, I cannot discern the methodology employed to implement them on the FPGA as previously mentioned.

The gain error of Architecture-1, as depicted in Figure 7, exhibits a consistent value of zero without any discernible variation. The reason for this phenomenon remains unclear.

In Figure 10, the Power Spectral Density (PSD) is presented for two scenarios: when clock sources are swapped and when a 6.25% mismatch exists between the two Voltage-to-Frequency Converters (VFCs). Surprisingly, no distinction is observable between the two cases. It appears that the figures are inadequate in demonstrating any noticeable improvements, which is also evident in Figure 15, showcasing the relationship between output gain error and emulated supply drift for Architecture-2.

Although the research work is interesting, the contribution and the appropriateness of the tests conducted to validate the resilience of the proposed system under unstable supply conditions are not clearly elucidated. I propose that the results be described in greater detail. Additionally, I am also concerned about the figures that in most of them no significant improvement is observed.

Best Regards

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 3 Report

Dear authors,

 

I have reviewed the changes in the new version of the manuscript and I consider that the comments of the major revision that I sent have been corrected.

 

Best Regards