Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

Round 1

Reviewer 1 Report

The paper deals with a novel full adder based on pass transistors, showing power reduction compared to a conventional CMOS based circuit. The proposed full adder is than used for the design of 8 bit signed multiplier.

 

Comments:

 

All used acronym must be defined for better understanding.

 

Several typos should be corrected.

 

The state of the art reported in section 2 must be improved by discussing recently published paper on similar topics, for instance:

 

M Amitha and Deepa “Comparison between CMOS full adder and PTL full adder “2021 IOP Conf. Ser.: Mater. Sci. Eng. 1065 012047.

D. Durga Prasad, M. Dileep, Ch. Rama Krishna “Design and Implementation of Full Adder using Different XOR Gates” International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-4, 2020.

 

The authors should explain in more details why the proposed full adder based on PTL allows better performances, when compared to 28T and 16T-1992

 

Fig. 16 must be replotted clearly showing all the connections.

 

In section 4 (PTL Based Multiplier) the better performance achievements should be not only listed, but also motivated.

 

Author Response

Dear editor and review,

Please fine the response to the reviewer`s comments in the attachment in PDF format.

Sincerely yours

Ningyuan 

Author Response File: Author Response.pdf

Reviewer 2 Report

 

In this work, the authors propose a novel 18T PTL-based full adder and design a multiplier based on the proposed full adder. Full adder is a widely investigated area of research and is of great importance to the scientific and engineering community. The article is technically sound, and the results demonstrate some improvement from previously reported structures under certain conditions. However, the manuscript needs to be better structured and written. Thus, several suggestions are provided to improve the quality of the manuscript before it can be considered for publication:

1. Several typographical errors throughout the text. Authors are suggested to proofread the article thoroughly before submission. Some of them are pointed out here:

-- Section 'Abstract', Line 02. Replace 'basis' with 'basic'.

-- Page 02, Section 'Introduction', Line 70. Replace 'peper' with 'paper'.

-- Page 05, Section '2', Line 104. Replace 'engough' with 'enough'.

-- Page 07, Section '3.1', Line 143. Replace 'Theatrically' with 'Theoretically'.

-- Page 11, Section '3.3', Line 196. Replace 'gliched' with 'glitched'.

-- Page 12, Section '4', Line 222 and 227. Replace 'Propatating' with 'Propagating' and 'reasonalbe' with 'reasonable'.

-- Page 14, Section '5', Line 252. Replace 'Althougn' with 'Although'.

-- Figure 16, caption. Replace 'circuti' with 'circuit'.

2. Page 03. Figure 2. "Cout" is labeled as "Co" as referenced in the text.

3. Page 03, Line 78. Replace 'As shown in 3,' with 'As shown in Figure 3,'.

4. Figure 20 Caption is wrong. The figure does not show the layout as mentioned.

5. Figure 21. The graph shows the worst-case delay, but the caption mentions power consumption.

Needs extensive improvement.

Author Response

Dear editor and reviewer,

Please see the response to the review comments in the attachment.

Sincerely yours,

Ningyuan

Author Response File: Author Response.pdf

Reviewer 3 Report

The paper presents an improved version of an existing PTL (pass transistor logic) adder and its application in a hybrid PTL-CMOS multiplier implementation focused on power consumption reduction. The proposed improvement seems to be elegant and adequate. Another interesting point is the consideration of the power consumption of input and output buffers due to the characteristics of some PTL adders implementation, whose inputs also acts as power sources.

Following there are some points to consider, where the number in the parenthesis indicates the number of the line of the text:

i) In the Abstratc, it's pointed that CMOS based circuits are power hungry (4). This is in comparision to what? Maybe hungry isn't a good term, also.

ii) Consider to include a brief description of PTL (39).

iii) Is there any example (reference) about standard cells full adders PTL based (44)?

iv) Is there any reference about PTL issues (50)?

v) Remove (55)

vi) Since glitches and flipping cases are relevante analysis conditions, shouldn't possible to consider dynamic power consumption, besides static power consumption?

vii) Is possible to include "conventional" power consumption of proposed adder in Table 4, in addition to proposed power consumption method, just for comparative analysis?

viii) It's no clear how is obtained the minimum value of m (187). 

The text is easy to be undestood, but there are some minor corrections:

i) power 'consumption' (43)

ii) 'compatative' (117)

iii) 'invertor' (130)

iv) 'is' instead of 'was' (135)

v) 'consumeption' (153)

vi) 'obatin' (159)

vii) '26?' (216)

viii) 'Propatating' (222)

ix) 'powr' (255)

x) 'performanace' (259)

Author Response

Dear editor and reviewer,

Please find the response to the review comments in the attachment.

Sincerely yours,

Ningyuan

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

The manuscript has been sufficiently improved to warrant publication in Electronics.