CMOS Tunable Pseudo-Resistor with Low Harmonic Distortion

Abstract

In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor’s dynamic range, improving its linearity. A fabricated cell was characterized providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. Additionally, the pseudo-resistor was incorporated into a high-pass OTA filter showing a THD below 0.2% for input voltages in the range ≤ 0.3 V_p. The simulations were compared with experimental measurements in a CMOS-fabricated cell, which verified the proposal’s feasibility.

1. Introduction

Pseudo-resistors (P-Rs) are devices based on MOS transistors working in the subthreshold regime, which emulate passive high-value resistors. These active resistors overcome any integrated CMOS passive resistors made of high-resistivity materials such as polysilicon, where large area amounts are necessary to achieve high-value resistors in the MΩ–GΩ range. For this reason, these compact P-Rs are preferred to be used in integrated biomedicine filter design, where high-value resistors are required to set the ultra-low cutoff frequencies for ECG, EEG, and EMG waves in the range from 0.01 Hz to 10 kHz [1]. Typically, non-tunable P-Rs consist of two or multiple series-connected MOS transistors, as presented in Figure 1 [2,3,4,5]. Thanks to their low complexity and compactness, these devices can provide high resistance values in the GΩ range. However, the main drawback of these non-tunable P-Rs is that they have a fixed resistance value and do not offer any adjustable capability.

On the other hand, tunable P-Rs allow different resistance values to be set in a given range. This critical fact allows us to set the cutoff frequencies for different applications from the filter design perspective. Tunable P-Rs, unlike non-tunable ones, commonly employ controllable voltage sources, as shown in Figure 2 [6,7,8,9,10,11,12]. These voltage sources establish the V_SG potential on the PMOS transistors and consequently set the channel conductivity.

There exist four topologies, as shown in Figure 2, two of them where a single controlled bias voltage source is used for both transistors M1 and M2, and bulk terminals can be connected to the outputs V_a/V_b or connected to the internal node “x”, Figure 2a. Other two are depicted in Figure 2b, where two bias voltage sources are used for each PMOS transistor, and as in the previous topology, bulk connections can go to the outside nodes V_a/V_b or the internal node “x”. These controlled bias voltage sources play a crucial role in the P-R performance since a slight inaccuracy can change the P-R resistance considerably.

This work proposes a new compact controlled bias voltage source that is almost insensitive to the unwanted MOS bulk-effect and provides a stable V_SG potential over the P-R dynamic range. Furthermore, this condition allows for improving the P-R linearity. In Section 2, a proposed P-R with a voltage follower free of body effect as a bias circuit is presented. Section 3 provides simulations and measurements of the proposed P-R. Section 4 presents the simulation results of an OTA-based high-pass filter using the proposed P-R. Finally, conclusions are presented in Section 5.

2. Proposed Tunable P-R with a Compact Controlled Bias Voltage Source Free of Bulk-Effect

Many of the currently used P-Rs are based on previous work [6], where a P-R in the form of Figure 2a with bulks connected to V_a/V_b is considered. This proposal uses an NMOS typical source-follower (level-shifter) as a controlled bias voltage source for providing V_SG, as shown in Figure 3a. The novelty of this circuit is its simplicity and the fact that the control circuitry (level-shifter for V_SG) has high input resistance; hence, no current from the P-R itself is extracted or modified affecting its effective resistance value. A significant drawback is that as the threshold voltage of M3 changes due to the bulk-effect, the V_SG potential offered by this circuit is not constant over the P-R dynamic range; this fact eventually changes the resistance provided by the P-R. Another possibility is to use a PMOS instead of an NMOS to provide a level-shifter; therefore, the use of transdiode configuration, as depicted in Figure 3b, is commonly used [7,11,12]. The benefit of this configuration is that M3, in this case, is of the same type of transistor as M1 and M2; hence, it can be properly matched for reducing technological process variations. Moreover, PMOS transistors allow dealing with the bulk-effect with the source-bulk terminals short-circuited on isolated devices. The drawback of this configuration is that the bias current I_b must go through M3 and then, it must be extracted from the P-R itself, affecting the current of this device.

An improvement for the level-shifter proposed in [6] and Figure 3a is presented in [8,9] and Figure 3c. The idea is to compensate for the technology parameter variations in M3 by using M5, i.e., a PMOS transistor as M1 and M2. Nevertheless, the idea must be implemented on double-well technologies to avoid the bulk-effect where isolated NMOS and PMOS are available.

The bias circuit proposed in Figure 3d uses a transconductance amplifier (OTA) with a transdiode configuration [10]. The high input resistance and gain of the OTA allow setting the V_a potential to the source of M4 accurately and is less sensitive to parameter variation due to the feedback. However, it needs to be clarified if M4 is considered on an isolated well to compensate for the bulk-effect.

The proposed P-R followed the topology from Figure 2b with the bulks connected to node “x”; the controlled bias voltage sources were implemented following the scheme in Figure 4a. This topology allows for controlling each PMOS transistor of the P-R setting V_SG potential independently. For the implementation of this controlled bias voltage source, we proposed the use of a compact voltage follower based on the differential flipped voltage follower (DFVF) [13,14], which is insensitive to the bulk-effect. The voltage follower schematic is depicted in Figure 4b; its output resistance is given by 1/g_m6(g_m4r_o), which is small enough to provide the bias current required by I_b current source (Figure 4a). This circuit presents a high input resistance for the P-R terminal V_a and allows PMOS transistors M1 and M2 (Figure 2b), and M3 (Figure 4a) to be properly matched to reduce process parameter variations. The transdiode configuration implemented by M3 is also considered for the implementation of V_SG; the bulk-source short-circuit avoids the unwanted bulk-effect in M3, offering a V_SG constant over the P-R dynamic range.

Due to the symmetry of the proposed P-R, as V_a or V_b rises, one of the transistors, M1 or M2, will be turned on with a fixed V_SG and V_BS < 0, since node “x” also rises; the V_SG of the other transistor will be increased turning “on” this transistor considerably. Therefore, since the first transistor has less current capability by its fixed V_SG potential, this transistor will provide a high resistance path. The PMOS drain current in weak inversion is modeled following this expression [15]:

$$I_{SD}=I_0·e^{\frac{V_G-V_{TO}}{\eta U_T}}\left(e^{\frac{-V_S}{U_T}}-e^{\frac{-V_D}{U_T}}\right)$$

(1)

where I₀ = 2ηµC_ox(W/L)U_T²; and U_T = kT/q is the thermal voltage; η is the subthreshold slope; µ is the carrier mobility; C_ox is the oxide capacitance per unit area, V_TO is the threshold voltage, and W/L is the transistor aspect ratio. Thus, the PMOS transistor channel current is controlled by voltage V_SG = V_S − V_G.

The bulk connection of M1 and M2 in Figure 2b play an important role in the P-R performance. In order to analyze the behavior, half of the P-R in Figure 2b can be considered for simplicity. Thus, M1a with bulk-drain connected as depicted in Figure 5a and M1b with bulk-source connected as in Figure 5b were analyzed. In both cases, V_a = V_S. For the first case (Figure 5a), V_BD = 0; V_BS = −V_S, and V_BG = V_SG − V_S; these conditions in Equation (1) bring the following expression:

$$I_{SD\left(M1a\right)}=I_0{e}^{\frac{V_{SG}-V_S-V_{TO}}{\eta U_T}}\left(e^{\frac{V_S}{U_T}}-1\right)$$

(2)

whose small-signal resistance evaluated in V_S = 0 as given in [12], is:

$$r_{eq}{|}_{V_S=0}=\frac{U_T}{I_0}{e}^{\frac{V_{TO}-V_{SG}}{\eta U_T}}$$

(3)

However, there are important differences in large-signal resistance if the bulk terminal is connected to the drain or source. For the second case (Figure 5b), V_BD = V_S; V_BS = 0, and V_BG = V_SG; therefore, the current expression is:

$$I_{SD\left(M1b\right)}=I_0{e}^{\frac{V_{SG}-V_{TO}}{\eta U_T}}\left(1-e^{\frac{-V_S}{U_T}}\right)$$

(4)

For Equation (2) with V_S > U_T, the product of both exponential functions compensates the other, bringing a super-linear behavior that provides a smooth transition close to the origin as stated in [12]. Unlike (4), the current follows an exponential decay function reaching a saturation value; this condition presents a current knee close to the origin, reducing the dynamic range considerably. Therefore, this topology is considered sub-linear [12].

3. Simulations and Measurements of the Proposed Pseudo-Resistor

As shown in Figure 6, a comparison of the simulated DC transfer curves of the different V_SG bias voltage sources is presented. All simulations were performed using CMOS 0.35 µm C35 parameters in TopSpice. The source-follower from Figure 3a is trace V(VO1). The transdiode with the source-bulk short circuit from Figure 3b is trace V(VO2), while the proposed voltage follower from Figure 4a is trace V(VO3). In all the cases, the transistor aspect ratio 50 µm/10 µm for NMOS and PMOS were considered and the bias currents were I_b = I_b1 = 10 µA and I_b2 = 2I_b1. As can be noticed, the slope of the source-follower output V(VO1) was different from the input V(VIN) due to the bulk-effect; this meant that, for this case, the V_SG potential was not constant and had a dependency on the input voltage V_a or V_b. As expected, the transdiode configuration and the proposed voltage follower did not present a different slope. However, an important fact of the proposed voltage follower is that when the bias currents are unbalanced, this is, I_b2 > 2I_b1; this causes a systematic positive offset V_of+ at the voltage follower’s output, trace V(VO4). This positive offset helps to obtain an even further reduced V_SG potential required for biasing the P-R PMOS M1 and M2 transistors in the deep subthreshold. Hence, the V_SG potential is reduced from V_SG = V_a − V_SG(M3) to V_SG = V_a + V_of+ − V_SG(M3) (Figure 4a) allowing the P-R to provide very high resistance values without requiring a shallow current at I_b.

Simulated drain current and the dynamic resistance ∂V_SD/∂I_SD of both half-circuits (Figure 5) are plotted in Figure 7; these resulted from a DC sweep of V_S from 0 to 0.2 V and V_SG = 0.3 V. As expected, both drain currents followed the behavior of Equations (2) and (3), where the drain current of M1a was more significant than M1b due to the bulk connection resulting in less resistance. However, the dynamic resistance of M1b changed much more in the V_S range than M1a; consequently, this configuration presented much less variability in its effective resistance.

Electrical simulations of the I-V curves of the proposed P-R are shown in Figure 8a. The simulation considered a primary DC sweep of V_a from −200 mV to 200 mV with V_b to ground. The pseudo-resistor resistance was adjusted through a secondary sweep, changing the current value of I_b, in this case, with steps of 1 µA from 2 µA to 9 µA. The following transistor sizes were considered: M1–M2 0.6 µm/1.2 µm; M3–M6 50 µm/10 µm, V_DD = −V_SS = 1 V and bias currents I_b1 = 10 µA, I_b2 = 50 µA. The fabricated P-R considering the same dimensions and electrical conditions was measured using the source-meter Keysight B2902A and the obtained I-V characteristic is depicted in Figure 8b. In this case, the current I_b was adjusted manually for a given P-R resistance value; as can be noticed, the measurement results were according to the simulation. The complete P-R schematic and microphotograph are depicted in Figure 8c,d.

A comparison of the simulated and measured Total Harmonic Distortion (THD) over the P-R drain current I_D of M1 is depicted in Figure 9. The THD was computed using an input voltage V_a of 100 mV_pp at 100 kHz and V_b to ground. The characterized resistance values went from MΩ to GΩ; however, in the range from 1 MΩ to 500 MΩ the linearity was THD ≤ 2%; for higher resistance values, the linearity was degraded. The measurement was performed using an op-amp-based trans-impedance amplifier and a spectrum analyzer. The relationship between the pseudo-resistor resistance and current bias I_b is depicted in Figure 10.

An example of the pseudo-resistor temperature dependence is depicted in Figure 11. The simulation was considered for a resistance value close to 1 GΩ in the −10–70 °C range with 10 °C steps. The resistance value changed from 1.47 GΩ to 1.11 GΩ, representing a change of 32% or 0.4%/°C.

4. Adjustable High-Pass Filter Based on OTA

A high-pass filter was designed based on a two-stage OTA in 0.35 µm CMOS technology. The filter followed a typical topology as considered in other works [2] with the P-R in the negative feedback path as depicted in Figure 12.

The transfer function of the filter is given by H(s) = (−C₁/C₂)sRC₂/(sRC₂ + 1) where R is the P-R resistance. The relationship between the capacitors establishes the gain, and f_o = 1/2πRC₂ gives the cutoff frequency. A single-stage OTA with local common mode feedback was considered [16]. The design is depicted in Figure 13. The power supply of the OTA was V_DD = −V_SS = 1.25 V and the transistor aspect ratio was 5µm/1µm for all PMOS and NMOS; R’ resistors were implemented by MOS transistors working in saturation with an effective resistance of 1 MΩ. The design presented A_ol = 70 dBs and a GBW product of 90 MHz with a phase lead compensation with R_S = 10 kΩ; C_L = 1 pF for a PM = 60° and SR = 80 V/µs.

The high-pass filter was simulated with C₁ = 10 pF and C₂ = 1 pF for a gain of 20 dBs. A parametric AC simulation sweeping I_b from 30 nA to 50 µA is shown in Figure 14; as can be noticed, the cutoff frequencies went from 17 Hz to 470 kHz. However, the source-bulk parasitic diode P⁺_diff/N⁻_well of M1 and M2 limited the P-R dynamic range. One of these two diodes acted in parallel to the transistor which provided the high resistance. As the diode obtained forward-biased due to the high voltage swings at the P-R, the effective resistance could be degraded by this parasitic diode. A ratio between the parasitic diode current and M1 drain current, I_diode(peak)/I_mosfet(peak) in percentage vs. the applied voltage amplitude to the P-R was simulated for a low resistance of 2.5 MΩ and a high resistance of 12 GΩ. The simulation results are depicted in Figure 15 and Figure 16, respectively. As expected, for high resistance values, the voltage swing must be limited, in this case, to 300 mV; this condition ensures that the parasitic diode current will be much less than the M1 drain current, preserving the resistance value provided by the P-R.

As the amplitude increased, the resistance value of the P-R was degraded since the current flowed through this parasitic junction. However, for lower P-R resistance values, the P-R dynamic range could be more extensive, up to 500 mV, as shown in Figure 15. Hence, the maximum allowable P-R input amplitude was limited by the DC resistance of the parasitic diode. Since this diode is forward-biased and assuming a minimum diode resistance of ten times the P-R resistance value, the following relationship was obtained:

$$\frac{V_p}{I_S e^{\frac{V_p}{V_t}}}=10R_{PR}$$

(5)

where R_PR is P-R resistance value, V_p is the peak input voltage applied to the parasitic diode, I_S the reverse saturation current, and V_t is the thermal voltage. Therefore, the solution of Equation (5) provides an approximation of the maximum allowable input amplitude for a given P-R resistance value. This is:

$$V_p=-V_t W\left(-\frac{10 I_S R_{PR}}{V_t}\right)$$

(6)

where W is the Lambert function in the −1 branch. Equation (6) is in accordance with Figure 15 and Figure 16.

The Total Harmonic Distortion (THD) of the filter was simulated for different resistance values, and the THD was computed on each case at a frequency of 10f_o. The simulation results in Figure 17 show that the THD was degraded with the action of the parasitic diodes, such distortion being more significant, as stated above, for high resistance values. However, it is crucial to notice that the THD remained close to 0.2% for the 0–0.3 V range. Finally, a Monte Carlo simulation was considered to analyze how the process variation can affect the P-R resistance. For the 1/√(WL) mismatch model, all the P-R transistor’s aspect ratios were 50 µm/10 µm in order to be almost insensitive to process fluctuations except M1 and M2 with 0.6 µm/1.2 µm. These two were considered with small dimensions since the parasitic P_dif/N_well junction must be as small as possible; consequently, M1 and M2 represent the most sensitive devices to mismatch. Following the 0.35 µm C35 CMOS matching parameters, the threshold voltage standard deviation for these transistors was σ(Δ_VTH) ≈ 10 mV, representing 1.5% of the threshold voltage. This threshold voltage variability in a Monte Carlo simulation of 50 runs following a Gaussian distribution represented a P-R high-value resistance of µ = 10 GΩ, a deviation of σ = 9.7%, and for small resistances a value µ = 2.5 MΩ, with σ = 8%.

5. Conclusions

Unfortunately, the channel conductivity of a MOSFET working in subthreshold was highly affected by systematic changes in the source-gate potential, V_SG. These changes caused the resistance of the tunable pseudo-resistor to vary drastically, affecting the device’s linearity. The MOSFET’s body effect represents an important cause for the deviation of the V_SG potential; therefore, this work presented a new compact bias circuit based on a novel voltage follower lacking body effect. The proposed pseudo-resistor was simulated, fabricated, and characterized, providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. The pseudo-resistor was incorporated into an OTA-based high-pass filter with simulated cutoff frequencies from 17 Hz to 470 kHz. These were obtained by adjusting the P-R resistance using fixed-valued capacitors in the pF range. Since the P-R was used in the OTA feedback, the filter THD was highly reduced when differential voltages were applied to the P-R when the filter gain was C₁/C₂ = 1. Therefore, the actual THD performance must be characterized by higher gains, in this case, C₁/C₂ = 10. The simulated THD results showed performance below 0.2% for applied voltages ≤ 0.3 V_p to the P-R. Different amplitudes activated the parasitic junction in M1 and M2 transistors affecting the P-R resistance and THD, as shown in Figure 17.