CMOS Tunable Pseudo-Resistor with Low Harmonic Distortion

Round 1

Reviewer 1 Report

The authors propose a new pseudo-resistor circuit, used maximize the value of resistance per unit area in integrated circuits, made in standard CMOS 0.35 µm technology and capable of minimizing distortion due to nonlinearities especially in the low-range resitances (above 300 megaohm ).

The paper has some minor errors that i will list above.

Line 21: I suppose that high-resistivity materials are maybe ZnO or other wide band gap semiconductors...I suggest to change the sentence with intrinsic silicon wells or polysilicon tracks.

 

Eq.2 and 4: it misses eta ideality factor of the intrinsic diode of MOS

 

Line 163: Vsg is reduced by offset not by its same value...no need of formula

 

Fig. 8 It misses a schematic of the circuit in the pic (c). Please add schematic as fig. 8d)

Also Insert Ib values used in fig. 8a-b) and correct Ib in the caption as subscript.

 

Fig. 13, please indicate Ib legend also here.

 

My best regards

 

 

 

English level is not really adequate according to me

Author Response

The authors propose a new pseudo-resistor circuit, used maximize the value of resistance per unit area in integrated circuits, made in standard CMOS 0.35 µm technology and capable of minimizing distortion due to nonlinearities especially in the low-range resistances (above 300 megaohm ).

The paper has some minor errors that i will list above.

Line 21: I suppose that high-resistivity materials are maybe ZnO or other wide band gap semiconductors...I suggest to change the sentence with intrinsic silicon wells or polysilicon tracks.

R. Well, in the text the sentence before: “integrated passive resistors” refers to any passive resistor made on any layer in a standard CMOS technology. In order to attend this comment, we are going to include “CMOS” in the text.

Eq.2 and 4: it misses eta ideality factor of the intrinsic diode of MOS

R. Yes, the subthreshold slope was omitted accidentally, now it is corrected.

 

Line 163: Vsg is reduced by offset not by its same value...no need of formula.

R. Done, “following Equation (1)” is omitted.

Fig. 8, It misses a schematic of the circuit in the pic (c). Please add schematic as fig. 8d)  

R. Done the complete schematic was included as figure (c).

Also Insert Ib values used in fig. 8a-b) and correct Ib in the caption as subscript.

R. Done, Ib values are inserted in the figure and the subscript corrected.

Fig. 13, please indicate Ib legend also here

R. Done, Ib values inserted.

Reviewer 2 Report

The article describes a source-follower-based biasing circuit for a CMOS tunable pseudo-resistor that aims to achieve high resistance values with low distortion (high linearity). The paper is well-organized and well-written. It presents a prototype in 0.35um CMOS process and measurement results of its characterization. The topic is of interest to MDPI Electronics and as such could be considered for publication if supplemented by some important information that is currently missing.

 

Namely, my major concern is the lack of characterization at different temperature conditions to demonstrate the temperature dependence and stability of the proposed biasing technique. Therefore I would request that the authors do an in-depth temperature analysis including the experimental results and to include it in the manuscript.

 

Supplement Fig. 10 curve with multiple ones on different temperatures in the foreseen operational range of the circuit.

 

Besides, abstract should be rewritten to reflect the main results and outcomes of the paper. In such an aspect, current paper's conclusion is more concise and informative and as such also more appropriate to serve as an abstract.

 

Perhaps the paper title should be changed too, to accurately and  precisely stress that the new biasing circuit is proposed, and not the novel type of a pseudo-resistor.

 

Please use independent figure for the fabricated chip microphotograph instead of placing it under Fig. 8c. Also, please include a photo of your measurement setup.

 

In Fig. 13, denote which Bode filter curves correspond to which Ib biasing currents and denote y-axis as filter magnitude or gain.

 

Please correct grammar mistakes such as "cutoff frequencies goes" (should be either "cutoff frequencies go" or "cutoff frequency goes") in line 222, page 10.

Author Response

The article describes a source-follower-based biasing circuit for a CMOS tunable pseudo-resistor that aims to achieve high resistance values with low distortion (high linearity). The paper is well-organized and well-written. It presents a prototype in 0.35um CMOS process and measurement results of its characterization. The topic is of interest to MDPI Electronics and as such could be considered for publication if supplemented by some important information that is currently missing. The paper has some minor errors that i will list above.

Namely, my major concern is the lack of characterization at different temperature conditions to demonstrate the temperature dependence and stability of the proposed biasing technique. Therefore I would request that the authors do an in-depth temperature analysis including the experimental results and to include it in the manuscript.

We understand the importance of temperature analysis, however, we regret that we do not have adequate equipment in the laboratory to do these temperature sweeps, at least for the moment. In fact we are now working on a pseudo-resistor idea with circuits that allow adequate stability for temperature changes with NMOS transistors biased at the ZTC point. If you are a specialist in the field, we could work on a new proposal.

Supplement Fig. 10 curve with multiple ones on different temperatures in the foreseen operational range of the circuit.

Temperature compensation schemes for pseudo-resistor, would be included in a next work, none of the used references include temperature analysis except [9], but we can include a spice temperature simulation.

Besides, abstract should be rewritten to reflect the main results and outcomes of the paper. In such an aspect, current paper's conclusion is more concise and informative and as such also more appropriate to serve as an abstract.

Abstract is now improved.

Perhaps the paper title should be changed too, to accurately and precisely stress that the new biasing circuit is proposed, and not the novel type of a pseudo-resistor.

Please use independent figure for the fabricated chip microphotograph instead of placing it under Fig. 8c. Also, please include a photo of your measurement setup.

Other reviewers suggested to include the complete P-R electrical scheme in the same figure 8 as (d). A photo of the measurement setup could be included but is not often used.

In Fig. 13, denote which Bode filter curves correspond to which Ib biasing currents and denote y-axis as filter magnitude or gain.

Done, the figure is now improved.

Reviewer 3 Report

This study presents a new, more efficient bias circuit based on a voltage follower, which eliminates the body effect in the tunable MOS pseudo-resistor. The pseudo-resistor was thoroughly evaluated through simulation, fabrication, and characterization. It achieved an impressive resistance range of 300kΩ to 10GΩ, with a total harmonic distortion (THD) lower than 2.5% up to 1GΩ. Additionally, an OTA-based high-pass filter was implemented using the pseudo-resistor, with simulated cutoff frequencies ranging from 17Hz to 470kHz. The simulated THD results indicated excellent performance, with values below 0.2% when applying voltages ≤0.3Vp to the pseudo-resistor.

However, there are several shortcomings in the manuscript that should be addressed. Firstly, the abstract is weak and does not adequately cover the background, methods, results, and main conclusions, which are customary sections in an article abstract. Secondly, the list of circuits in Figure 3 should include the Buffered-Input Trans-diode circuit (Figure 12(c)) published in the article [12]. This is because the proposed circuit can be obtained from the published one by eliminating the transistor MN and connecting the output of the operational amplifier to the inverting input.

Furthermore, in Figure 13, the parameter representing the family curves is missing, and the vertical axis needs to be labeled with the appropriate parameter name. Lastly, the caption for Figure 16 should be revised to provide more informative details.

Overall, this manuscript should be of particular interest to specialists in the field of electronics. However, addressing these shortcomings would significantly enhance the clarity and completeness of the article.

 

[12] E. Guglielmi et al. High-Value Tunable Pseudo-Resistors Design. IEEE Journal of Solid-State Circuits 2020, 55, 2094-2105. 317 doi: 10.1109/JSSC.2020.2973639.

Minor editing of the English language is required.

Author Response

This study presents a new, more efficient bias circuit based on a voltage follower, which eliminates the body effect in the tunable MOS pseudo-resistor. The pseudo-resistor was thoroughly evaluated through simulation, fabrication, and characterization. It achieved an impressive resistance range of 300kΩ to 10GΩ, with a total harmonic distortion (THD) lower than 2.5% up to 1GΩ. Additionally, an OTA-based high-pass filter was implemented using the pseudo-resistor, with simulated cutoff frequencies ranging from 17Hz to 470kHz. The simulated THD results indicated excellent performance, with values below 0.2% when applying voltages ≤0.3Vp to the pseudo-resistor.

However, there are several shortcomings in the manuscript that should be addressed. Firstly, the abstract is weak and does not adequately cover the background, methods, results, and main conclusions, which are customary sections in an article abstract. Secondly, the list of circuits in Figure 3 should include the Buffered-Input Trans-diode circuit (Figure 12(c)) published in the article [12]. This is because the proposed circuit can be obtained from the published one by eliminating the transistor MN and connecting the output of the operational amplifier to the inverting input.

Abstract is now improved following your suggestions.

The buffered-input transdiode circuit that you refer is proposed by Puddu et al, and appears in our paper in the Fig. 3(d). Puddu used a one stage single-ended OTA with high resistance at the output (voltage follower was not included).  The OTA that they proposes uses at least 10 transistors and probably a compensation scheme.

The voltage follower that we propose uses 6 transistors without compensation scheme, providing a very low output resistance. Additionally, unbalanced currents allow adding a controllable offset voltage at the output needed for high resistance values by the pseudo-resistor.

Furthermore, in Figure 13, the parameter representing the family curves is missing, and the vertical axis needs to be labeled with the appropriate parameter name. Lastly, the caption for Figure 16 should be revised to provide more informative details.

Done, the figure is now improved

Overall, this manuscript should be of particular interest to specialists in the field of electronics. However, addressing these shortcomings would significantly enhance the clarity and completeness of the article.

 

 

 

[12] E. Guglielmi et al. High-Value Tunable Pseudo-Resistors Design. IEEE Journal of Solid-State Circuits 2020, 55, 2094-2105. 317 doi: 10.1109/JSSC.2020.2973639.

Reviewer 4 Report

see attached file

Comments for author File: Comments.pdf

Author Response

Following your suggestion, Fig. 3 and its background is moved to section 2, instead section 1. Fig. 2 must be in section 1 since explains the basic topologies of tunable pseudo-resistors.

The topology that you mention “the one in parallel” we dont know if you refer to a transmission gate…if that is the case, this latter is used as a switch instead a high value resistor.

For optimal performance the slope must follow the trace V(Vin) exactly. This condition ensures that pseudo-resistor’s PMOS transistors M1 or M2 preserve its VGS potential to maintain a given resistance value. All this is included in the text.

For all pseudo-resistors, the dynamic range is reduced; -200mV to 200mv is a typical range. This condition as explained in the paper and is limited by the parasitic junction.

Your last comment is very valuable, at this moment following your suggestion, we are working with an analytical expression for a realtionship between resistance value (P-R) and a given amplitude. I hope we can include this expression in the next days. Until now we need to sent the paper version of round1.

Round 2

Reviewer 2 Report

The authors did not answer to my questions and concerns properly.

Please correct grammar mistakes.

Author Response

The article describes a source-follower-based biasing circuit for a CMOS tunable pseudo-resistor that aims to achieve high resistance values with low distortion (high linearity). The paper is well-organized and well-written. It presents a prototype in 0.35um CMOS process and measurement results of its characterization. The topic is of interest to MDPI Electronics and as such could be considered for publication if supplemented by some important information that is currently missing. The paper has some minor errors that i will list above.

Namely, my major concern is the lack of characterization at different temperature conditions to demonstrate the temperature dependence and stability of the proposed biasing technique. Therefore I would request that the authors do an in-depth temperature analysis including the experimental results and to include it in the manuscript.

R: We understand the importance of temperature analysis, however, we regret that we do not have adequate equipment in the laboratory to do these temperature sweeps, at least for the moment. In fact we are now working on a pseudo-resistor idea with circuits that allow adequate stability for temperature changes with NMOS transistors biased at the ZTC point. If you are a specialist in the field, we could work on a new proposal.

Supplement Fig. 10 curve with multiple ones on different temperatures in the foreseen operational range of the circuit.

R: Temperature compensation schemes for pseudo-resistor, would be included in a next work, none of the used references include temperature analysis except [9], but we can include a spice temperature simulation.

Besides, abstract should be rewritten to reflect the main results and outcomes of the paper. In such an aspect, current paper's conclusion is more concise and informative and as such also more appropriate to serve as an abstract.

R: Abstract was now improved.

Perhaps the paper title should be changed too, to accurately and precisely stress that the new biasing circuit is proposed, and not the novel type of a pseudo-resistor.

R: There are many types of pseudo-resistors with their own bias scheme. For us the paper title is in accordance to the work, since the new biasing scheme is clearly mentioned in the abstract.

Please use independent figure for the fabricated chip microphotograph instead of placing it under Fig. 8c. Also, please include a photo of your measurement setup.

R: Other reviewers suggested to include the complete P-R electrical scheme in the same figure 8 as (d). A photo of the measurement setup could be included but is not often used.

In Fig. 13, denote which Bode filter curves correspond to which Ib biasing currents and denote y-axis as filter magnitude or gain.

R: Done, the figure is now improved.

 

Reviewer 3 Report

The comments are in the attached file.

Comments for author File: Comments.pdf

 Minor editing of English language is required.

Author Response

Done figure 3(d) have been changed following your comments.

For your further concerns:

Firstly, the authors refer to the circuit depicted in Figure 1(c) of the
study [10, p. 763]. However, upon comparing it with the circuit
presented in the manuscript (Figure 3(d)), it becomes evident that the
latter is not an exact copy of the original circuit as presented in the
source. This discrepancy raises questions about the accuracy and
consistency of the representation.  

R. There is an important difference between an operational amplifier OPA and an operational transconductance amplifier OTA. As well known, this latter lacks a voltage follower in its last stage. The mentioned circuit in [10] ( Figure 1(c)) refers to the OTA as shown in figure 3 in the same work. That is the reason why the figure 3(d) of the manuscript was initially considered with an OTA symbol in the electrical diagram. However, as the reviewer suggested, the figure was now corrected as it appears in [10].  

Furthermore, in Figure 4(a) of the manuscript, the authors propose a
circuit that appears to be derived from the circuit provided in the
study [10]. However, the connection between this newly proposed circuit
and the circuit presented in Figure 3(d) of the manuscript is not so
clear. This lack of clarity in the interpretation of the circuit raises
some concerns, as it is unclear whether the authors' proposed circuit is
the special case of the original circuit described in [10].  

R. The compact voltage follower used by us (Fig. 4(b)) is totally different to the OTA in [10] (Fig. 3). The proposed circuit with less transistor count presents higher current capability at the output, this condition allows bias current Ib to work easily from 10nA to 100uA. Moreover, unbalanced bias currents allow an additional voltage offset at the output necessary to lead the pseudo-resistor to work in deep subthreshold bringing high resistance values.  

Reviewer 4 Report

No further comments

Author Response

Following your comments of the first round, we have included, equations 5 and 6.

They help to predict the joints in Figures 14 and 15 as can help to predict the limits of the amplitude-resistance relationship.

Round 3

Reviewer 2 Report

The authors have ignored my suggestions. 

The English is not major problem.

Author Response

The following suggestions were followed:

Besides, abstract should be rewritten to reflect the main results and outcomes of the paper. In such an aspect, current paper's conclusion is more concise and informative and as such also more appropriate to serve as an abstract.

R. Abstract was improved following some things mentioned in the conclusions as you suggest.

In Fig. 13, denote which Bode filter curves correspond to which Ib biasing currents and denote y-axis as filter magnitude or gain.

R. Done, the figure was improved following your comment. 

 

Reviewer 3 Report

As the authors have replaced Fig. 3(d) with Fig. 1(c) from the referenced article [10], I have no objection to the publication of the manuscript.

 Minor editing of the English language is required

Author Response

Following your comments, editing improvements were made.