A High FoM and Low Phase Noise Edge-Injection-Based Ring Oscillator in 350 nm CMOS for Sub-GHz ADPLL Applications

Abstract

This paper presents an injection locked digitally controlled ring oscillator (IL-DCRO). To reduce jitter variations, minimize oscillator spurious signals, and eliminate periodical phase error, a double edge-injection (window injection) scheme with synchronized edge directions is proposed. A combinational edge generator is utilized to substitute the sequential edge generators for injection timing requirements relaxation. By biasing devices in deep triode, digitally controlled delay cells currents are adopted for frequency tuning. This helps reducing the devices flicker (1/f) noise and minimize the DCRO overall phase noise. At 1 MHz offset of frequency, the proposed oscillator has a measured phase noise of −125.95 dBc/Hz and −115.6 dBc/Hz at oscillation frequencies of 913.4 MHz and 432.6 MHz, respectively. Fabricated in 350 nm CMOS process, with a maximum power consumption of 3.3 mW, and oscillating at 913.4 MHz, this DCRO achieves a tuned oscillator figure of merit (FoM) of −197.35 dBc/Hz. The core area of this edge-injection-based DRCO is only 0.08 mm².

1. Introduction

Complementary Metal-Oxide-Semiconductor (CMOS) technology’s rapid scaling is promoting all-digital and inductorless radio frequency (RF) blocks to replace their counterparts for improved performance, lower power consumption, and smaller die area. Thus, they attract the interest of nowadays analog and RF designers [1,2,3]. All digital phase locked loop (ADPLL) replaces the voltage controlled oscillator (VCO) by a digitally controlled oscillator (DCO) to digitally generate the controlled clock [1,2,3]. To enhance the ADPLL noise and jitter performance, a band-bang ADPLL with LC DCO which dissipates larger power and occupies a wider area was presented [1]. Another attempt was done considering injection locking ADPLLs [1]. Gated edge-injection was considered to implement a synthesizable ADPLL [2]. A sub sampling PLL could represent another trial for PLLs performance enhancement, but it adds to the PLL dissipated power as it requires extra loops [1,2].

Oscillators are playing critical roles in the recently proposed RF systems and high-speed digital VLSI circuits. In Phase-Looked Loops (PLLs), controlled oscillators’ jitter performance dominates [1,2]. Ring and LC oscillators are the two main candidates for digitally controlled oscillators (DCOs) implementations. The LC oscillator achieves higher clock frequency and lesser phase noise; however, its area is relatively large, and it consumes a larger amount of power [1]. DCO consumes lower power, occupies smaller die area, and provides a wider tunable range of frequency [1,2,3]. But its phase noise is not as good as LC oscillators phase noise [1,2,3].

Injection locking is being used for ring oscillators’ phase noise suppression while dissipating lower power [3]. Sub-harmonic injection resets the injection locked ring oscillators (ILROs) periodically and minimizes their root mean square (RMS) jitter [2,3]. This helps ILROs to have synthesizable architectures [2,4], which promotes ILROs for improved portability, scalability, and lesser cost of design and implementation [2]. ILROs can also achieve wide tuning and locking ranges of frequency. On the other hand, they suffer from periodical output signal disturbance and frequency shift from free-running oscillation frequency to n^th harmonic of injected reference due to injection locking. This adds to the ILRO output spectrum spurs [3,4,5].

The time-to-digital converter (TDC) of digital phase locked loops is used to compare the digitally controlled oscillator (DCO) output signal to the reference signal. TDC mainly uses the DCO output signal level and the digital phase locked loop (DPLL) input signal level during the frequency capture mode. TDC uses DCO output signal edges in comparison to the DPLL input signal edges during its phase tracking mode [1,2]. This implies the importance of conserving the DCO output levels and edges unchanged while injecting references for performance enhancement.

A sub-GHz ILRO is presented by this paper. For performance enhancement, a synchronized double edge-injection is firstly proposed. Considering ILRO output signal instantaneous level, the directions of the injected jitter-free edges are adjusted. For frequency switching, delay cells control through MOSFET devices operating in cut-off (OFF) or deep-triode (ON) regions is implemented.

The rest of this paper is organized as follows. Section 2 introduces the proposed injection locking technique. Section 3 describes the presented IL-DCRO circuit. Section 4 shows and discusses the obtained measurement results. The conclusion of the work is driven in Section 5.

2. Injection Locking

Ring oscillators are mainly formed through a feedback connection over an odd number of successive delay stages (current starved INVERTERs (CSIs) [5,6], output split INVERTERs (OSIs) [3], or NANDs [2]). The oscillation frequency of ring oscillators is given by (f_osc = 1/2nτ), where n is an odd number representing the number of delay stages and τ is the gate delay time of those delay cells. Improving oscillators phase noise performance requires the prevention of output phase error accumulation and the reduction of oscillator timing jitter. This can be done through a large power surge [7,8,9] or the employment of the injection locking technique [2,3,4,5]. For the design of injection locked oscillators (ILOs), pulse injection [3,5] and edge-injection [2] regimes were utilized.

Pulse injection (PI) is conventionally used, at which successive narrow pulses are applied to an NMOS modulator to turn the ILRO ON and OFF for averting the oscillator phase error accumulation [5,10]. Unluckily, pulse injection has strict timing requirements on the injected pulse width. Besides, turning the injection locked oscillator (ILO) ON and OFF induces strong disturbances to the oscillator output signal that results in significant increases in oscillator spur levels [2,3,10]. Pulse injection with adjustable pulse width would be the key for ILO performance improvement. This suppresses the ILO output disturbance; however, this causes a non-robust oscillator performance over process voltage temperature (PVT) variations [2,10]. Hence, additional circuits would be needed to cope with PVT variations. This adds to the ILO dissipated power and occupied area. Figure 1 shows the block diagram and transient signals of ILRO designed utilizing the pulse injection technique.

For edge-injection, a clean edge is inserted to the oscillator output. The clean edge is a jitter-free edge extracted from a reference signal using the edge generator circuit. This preserves phase noise at low levels and prevents phase error accumulation [2,11]. The block diagram and transient signals of an ILRO employing edge-injection are shown in Figure 2.

Edge generators proposed so far are sequential (enabled or clocked circuits). As shown in Figure 2, synchronization between the HIGH portions of enable and injection-window signals must be preserved for clean edge insertion and beneficial edge-injection indicated by the “T1” period in Figure 2. If the injected-edge is not completely enclosed by the enable and injection-window signals, the clean reference edge would be inserted partially to ILO output. This adds to the oscillator phase error, which is described by “T2” period in Figure 2. Complete misalignment of the enable and injection-window signals blocks the edge generator NAND and prevents the jitter-free edge insertion. This results in phase error accumulation and jitter performance degradation as illustrated by the “T3” period in Figure 2. This also disables circuit oscillation momentarily and boosts the oscillator’s output spurious power. Widening the HIGH portion of enable and injection-window signals unblocks the edge generator NAND and alters the ILO output signal. Shortening of these signals’ HIGH levels would lead to partial clean edge insertion, partial phase error reset, and output spurs boosting.

Both situations increase phase noise and oscillator spurs signal. Furthermore, if a clean edge (falling edge is assumed) was aligned and fully occupied by the enable and injection-window signals HIGH portions, and the oscillator output was momentarily HIGH, traditional edge-injection would succeed to reset the oscillator phase error and suppress oscillator phase noise. But if the oscillator output was temporarily LOW, clean edge could not be injected and phase error would not be reset or an additive transition -from LOW to HIGH- would be needed, then the clean edge could be injected. This would disturb the oscillator output signal and add to oscillator spur levels [12].

Edge-injection proposed so far has non-adaptive edge direction. Thus, ILO output might miss the unidirectional clean edge, which is also indicated by T3 in Figure 2. That fixed direction of the injected edge could not ensure periodic phase error reset and phase noise suppression. Hence, edge-injection with sequential edge generators still requires precise timing for an improved ILO performance.

There is no doubt there is some room for performance improvement of injection locked digitally controlled oscillators, which would imply further ADPLL performance enhancement. In this paper, a combinational (clockless) edge generator is designed to get ride-off timing requirements of sequential edge generators. This relaxes the timing requirements of edge generators and ensures a periodic phase error reset. The proposed edge generator considers the ILRO output signal level in preparing the clean (jitter-free) edges. The prepared clean edges would be injected to replace the ILRO noisy edge. This enhances the IL-DCRO noise performance and suppresses its phase noise, which is a vital requirement by all digital phase locked loop (ADPLL) applications. This helps avoiding the disadvantages of the tough pulse injection technique and its strict timing requirements. This free-running (combinational) edge generator ensures a pleasant ILRO performance by suppressing its phase noise and boosting its figure of merit (FoM).

3. Circuit Design and Description

In this manuscript, a double edge-injection (window injection) scheme with synchronized directions of injected edges is proposed. A combinational circuit has been designed for jitter-free successive dual edges preparation. The edge generator circuit is designed to have a speed transition and accurate threshold voltages for sustained performance over PVT variations. This is done by utilizing output split inverters to implement all delay stages employed. OSI has proven to have a lower mismatch effect, enhanced performance versus temperature variations, and accurately controllable adjustable gate delay [13] in comparison to its counterparts. Besides, redundant switches were also added to trim the switching thresholds of the used CMOS logic circuits to compensate PVT variations [14]. The block diagram of proposed tunable ILRO and its transient locking signals are shown in Figure 3.

The HIGH level of the reference signal is used for dual injected edges generation, as shown in Figure 3. Va is a delayed version of the reference signal with a delay time of (t1 + t2). Vb presents an inverted copy of the reference signal. Vc is an inverted version of the reference-signal with a “t1” delay time. Va and Vb via NOR gate detect the reference-signal rising edge.

When that rising edge exists, an injection-window pulse with a width of “t1+t2” is generated. The rising edge of the injection-window with a delay time of “t3” initiates the double injected edges preparation. The first edge is extracted from the injection-window delayed rising edge, while the second edge is extracted from the Vc inverted version falling edge. For oscillator optimized performance, the sizing of edge generator delay stages MOS devices has been tuned for the best settings of “t1” and “t3” in respect to “t2”. This ensures that the dual injected edges are fully enclosed by the injection window. Hence, jitter-free edges are successively injected to the oscillator output. This reduces the output signal disturbance experienced by the ILRO.

Figure 3 shows the injection-window HIGH pulse enabling the oscillator output phase detector circuit to define the oscillator output signal level (LOW or HIGH) at injection time. It also blocks the oscillator “(n − 1)-th” NAND and unblocks the oscillator “n-th” NAND for prepared dual edges (window) with adjustable direction injection. Through the exclusive-OR (X-OR) of the phase detector circuit, a falling edge followed by a rising edge would be injected to the ILO, if HIGH oscillator output level was detected. If LOW oscillator output level was detected, a rising edge followed by a falling edge would be injected to the ILO output. This ensures periodical substitution of oscillator noisy edges by clean edges having the same edge directions. This also retains the ILRO output signal level after injection. Upon clean edges insertion, the oscillator is released to continue oscillating. The injection window LOW level blocks the output phase detector circuit and unblocks the ILO “(n − 1)-th” and “n-th” NANDs for oscillation.

The proposed double edge-injection (window injection) uses the clean (jitter-free) prepared edges to replace the ILO prior noisy (jittered) edges while keeping output last edge direction (rising/falling). It also inserts the clean edges and retains the ILRO output level to its former level (LOW/HIGH). This edge-injection scheme ensures periodic clean edges insertion to prevent ILO phase error accumulation and minimize its timing jitter variations. This also keeps the ILO output signal’s disturbance minimized to reduce its spurious components level in respect to carrier.

Using the discrete time-domain analysis as in [2], considering N >> 1, the ILRO phase noise and the injection locking range of frequency can, respectively, be given by:

$${PN\left(f\right)}_{inj}\cong {PN\left(f\right)}_{free-running}.4{\mathsf{\pi }}^2.\frac{{f_m}^2}{{{3f}_{ref}}^2}.\frac{{f_{inj}}^2}{1+\left(\frac{{f_{inj}}^2}{{f_m}^2}\right)}$$

(1)

$$f_{inj}\cong 1.3 \left(\frac{f_{ref }}{\pi }\right)$$

(2)

where PN (f) is the oscillator phase noise measured at an offset frequency f_m, f_inj is the injection locking bandwidth, and f_ref is the reference-signal frequency. Equation (2) shows the availability of free-running oscillator phase noise suppression if it is measured at offset frequencies (f) lower than the injection locking bandwidth (f_inj) while employing edge-injection locking. For wide tuning range, CMOS tuning transistors should be kept into saturation [9]. This reduces the output signal voltage swing due to devices’ large over-drive voltages. In addition, CMOS devices in saturation add extra flicker noise to oscillators due to the trapping and releasing of current carriers under the tuning devices’ gate-oxides [9]. Digital control by switching devices ON and OFF helps suppressing oscillators flicker noise.

Devices are kept in the deep triode region while being ON to form thick and uniform conduction channels under devices’ gate-oxides. Such channels formulation can strongly lessen the chance to trap and de-trap the MOS devices’ current carriers. In the OFF condition, current carriers are released, and no channel is formed. This increases the signal swing and improves the tuned oscillator noise performance. In addition, digital frequency tuning lowers the oscillator impulse sensitivity function (ISF) comparable to analog frequency tuning [9,15]. As gate input capacitances have a low pass filtering effect on white thermal noise, larger input gates of ILROs NAND delay cells lower the thermal noise filtering cut-off frequency. Therefore, this shrinks the oscillator thermal noise bandwidth and reduces the oscillator-experienced white thermal noise, which enhances the ring oscillator phase noise [15].

A three stage DCRO has been designed (n = 3) to implement the proposed IL-DCRO. For an accurate coarse and fine oscillation frequency tunability, accurate selection of the NAND delay stages devices’ dimensions (channel width, channel length, and number of fingers) was done to precisely adjust their gate delay (τ). The schematic circuit of the NAND gate employed is shown in Figure 4. The frequency tuning block with a 10-bit digital input is designed to control the delay stage currents and adjust the DCRO oscillation frequency. MP_L is designed to maintain the ILRO oscillating at lowest frequency, i.e., 240 MHz in this DCRO. MP_C with large aspect ratios (W/L) and inputs “D0–D4” are responsible for frequency coarse tuning while MP_F with smaller aspect ratios (W/L) and inputs “D5–D9” are utilized for frequency fine-tuning. In general, lower LSB resolution of fine-tuning devices leads to lower spur levels in injection locked oscillators [16].

The frequency tuning devices are carefully sized. The channel lengths of those devices are selected larger than the minimum process channel length to overcome technology mismatch and fabrication variations. MP_C and MP_F devices are sized with binarily weighted frequency steps corresponding to the value of “D4–D0” and “D5–D9” digital control words, respectively. With a frequency coarse tuning step of 22 MHz and a fine-tuning step of 500 kHz, the proposed DCRO oscillation frequency can be tuned from 240 MHz to 937.5 MHz.

4. Measurement Results and Discussion

The injection locked digitally controlled ring oscillator has been designed and fabricated in 1P4M 350 nm CMOS process. The presented ILRO die photo including PADs is shown in Figure 5. That edge-injection-based ILRO die has an area of 900 µm × 900 µm, while its core excluding PADs has an area of 310 µm × 250 µm. The prototype (PCB mounted) measurement testbench is shown in Figure 6. The reference injected signal was provided by the Keysight 33500B waveform generator. The ILRO output spectrum and total-harmonic distortion (THD) were measured by the Keysight N9010B-503 EXA signal analyzer. The ILRO phase noise was measured by the R&SFSWP50 Phase Noise Analyzer and VCO Tester. The DCRO was tuned to 432.6 MHz and 913.4 MHz for functionality verification (f_o = N × f_ref). A square reference signal with f_ref = 4.006 MHz was injected. This reference frequency was selected to test the functionality of the frequency tuning block considering coarse tuning and fine-tuning devices.

The proposed injection locked oscillator phase noise obtained across its tuning range of frequency at 1 MHz offset is reported by Figure 7. The ILRO obtained output spectrum and the THD at 432.6 MHz (N = 108) are shown in Figure 8. The oscillator output spectrum and THD measured at 913.4 MHz (N = 228) are shown in Figure 9. The adopted dual edge-injection (window injection) in addition to the implemented digital control scheme helped keep spurs signal levels lower than −38 dBc and −40 dBc while having oscillation frequencies of 432.6 MHz and 913.4 MHz, respectively.

The proposed injection scheme pushed the oscillators THDs to 0.14% (−57.2 dBc @ 432.6 MHz) and 0.08% (−62.32 dBc @ 913.4 MHz) only. When the DCRO is tuned to 913.4 MHz, only three harmonics are displayed because the measurement device bandwidth is limited to 3.6 GHz. Enhanced spectrum and low spurs level represent important challenges of the IL-DCRO design [2]. To evaluate the spectral performance of the ILRO, the 2nd harmonic level in respect to the 1st harmonic should be reported. The second harmonic is measured to have −80 dBm (−70.44 dBc) while the DCRO is tuned to 432.6 MHz, as reported by Figure 8b. While the ILRO is tuned to 913.4 MHz, the second harmonic measurement indicates a power level of −77 dBm (−69.21 dBc), as shown in Figure 9b.

The simulated and measured phase noise of the proposed injection locked DCRO in comparison to its free-running phase noise are shown in Figure 10. With an enhanced measured phase noise of −20 dBc/Hz in comparison to its free-running circuit, the measured phase noised of the ILRO is −125.95 dBc/Hz, while having an oscillation frequency of 913.4 MHz. It also has a measured phase noise of −115.86 dBc/Hz, while oscillating at 432.6 MHz. The proposed DCRO achieves a wide tuning range of frequency, keeps spurious signals at a low level, and strongly suppresses the oscillator phase noise by periodically resetting the oscillator phase error.

Table 1. Proposed IL-DCRO performance summary and comparison.

	[2], 2015	[3], 2016	[4], 2017	[5], 2019	[6], 2020	[7], 2019	[8], 2020	[17], 2016	[18], 2022	[19], 2018	[20], 2017	This Work
Tech. (nm)	65	180	65	65	180	180	65	65	350	65	180	350
Osc. Freq (GHz)	0.9	4.923	1.62	5	0.216	2	2.5	13.69	0.00937	1.7	1.03	0.9134
PN * (dBc/Hz)	−114	−126	−130	−116	−96	−103.3	−101.1	−99	−147.5	−128	−105.5	−125.95
Diss. Pwr (mW)	0.78	4.8	7.15	3	1.3	12.6	20	16.5	0.903	11.77	2.5	3.3
TR ** (%)	72.3	9.7	44.4	56.5	95	79.4	78	15.1	99.8	47.3	50	74
Area (mm2)	0.0066	-	0.004	0.09	0.284	0.0016	-	-	0.005	0.017	0.032	0.08
FoM1 (dBc/Hz)	−174.99	−193	−185.6	−185.2	−141.5	−158.3	−156	−173.1	−167.5	−181.2	−161.7	−179.98
FoM2 (dBc/Hz)	−192.17	−192.73	−198.54	−199.8	−161.1	−176.3	−182	−176.67	−187.48	−194.69	−175.68	−197.35

* Phase Noise @1MHz offset ** Tuning Range (%).

summarizes the proposed injection locked DCRO measured results and compares them to recently published injection locked and tunable oscillators using FoM1 [3,9] and FoM2 [17,18], which can be expressed as:

$$FoM1=Phase Noise@f_m(dBc/Hz)-20\log (f_{osc}/f_m)+10\log (P_{diss}/1mW)$$

(3)

$$FoM2=FoM1-20\log \left(TR \left(\%\right)/10 \left(\%\right)\right)$$

(4)

where f_m represents the offset frequency at which the phase noise is measured. TR (%) is the percentage value of the oscillator tuning range. FoM2 is used for tunable oscillators performance comparison.

Table 2. Measurement results of ten different chips of the proposed IL-DCRO.

Chip No.	Osc. Freq. (MHz)	PN (dBc/Hz) @ 1 MHz
1	432.6/913.4	−115.86/−125.95
2	432.5/913.6	−109.10/−126.02
3	433.0/912.0	−111.07/−121.76
4	430.0/914.0	−113.28/−121.09
5	432.6/913.2	−110.51/−123.40
6	431.3/912.5	−105.68/−113.07
7	432.2/913.4	−111.20/−123.40
8	432.6/913.5	−110.52/−113.50
9	433.3/913.4	−111.72/−111.68
10	432.6/912.7	−105.65/−112.18

lists the measured oscillation frequencies and phase noises of ten different ILRO chips tuned to 432 MHz and 913 MHz.

PLLs with low frequency reference utilizing injection locking is widely used nowadays, as they show a better spectral performance in respect to simple PLLs. Those injection locked-based all digital phase locked loops (ADPLLs) are representing high quality factor filters which unblock the Nth harmonic of the reference signal frequency while blocking other (lower and higher) harmonics. A higher multiplication factor (N) and lower phase noise reference push the ADPLL to have an enhanced phase noise performance. The ILRO locking range is mainly defined considering the injected power of the desired harmonic; higher power leads to a wider locking range. The PVT analysis of the ILRO also diverges from the reference signal PVT. These two consequences raise the need for a frequency calibration technique in ADPLL for better performance. This would add to the DPLL consumed power and occupied area.

Considering this ILRO application (sub-GHz ADPLL), the jitter and power-based FoM given by 10log[(jitterrms/1s)² (Pdiss/1mW)] [2] can be considered. The proposed ILRO has an integrated jitter RMS value of 870 fs @ 913.4 MHz, while it dissipates only 3.3 mW. This leads to an FOM of −236 dB. This ILRO also has a 10% phase noise enhancement compared to recently reported ring oscillators, while having a noticeable reduction in the RO DC dissipated power.

5. Conclusions

A sub-GHz injection locked digitally controlled ring oscillator with an adaptive dual edge-injection (window injection) for ADPLLs applications has been proposed. The ILO has a tuning range from 240 MHz to 937.5 MHz. This tunability was achieved by controlling the tuned oscillator delay cells currents. The presented IL-DCRO was tuned through keeping devices in deep triode or in OFF regions. This ILRO has a −125.95 dBc/Hz measured phase noise at a 1 MHz frequency offset, while oscillating at 913.4 MHz and consuming a maximum power of 3.3 mW only. It also has a phase noise of −115.86 dBc/Hz at a 1 MHz frequency offset while tuned to 432.6 MHz. Spectrum and THD measurements showed suppression of injection locking spurs and harmonics. Thanks to the periodic synchronized dual edge-injection and utilized digital control scheme, an FoM1 of −179.98 dBc/Hz and FoM2 of −197.35 dBc/Hz have been achieved.