41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology

Round 1

Reviewer 1 Report

Review Report

Journal: Electronics (ISSN 2079-9292)

Manuscript ID: electronics-2585827

Article Type: Article

Title: 41.6Gb/s High-depth Pre-interleaver for DFE Error Propagation in 65nm CMOS Technology

Authors: Yongzheng Zhan, Tuo Li, Xiaofeng Zou, Qingsheng Hu, Lianming Li and Lu Zhang

 

Summary:

 

This work deals with the implementation of a high-speed, high-depth pre-interleaver in the proposed symbol pre-interleaving Bit MUX (PBM) system. The primary objective is to address DFE error propagation challenges within a 400G Ethernet SerDes interface. Through simulations based on a SerDes interface architecture featuring a 5-tap DFE, the performance of the PBM system is theoretically evaluated, showcasing an achievable interleaving gain of 0.35dB. To achieve enhanced transmission rates while maintaining a larger interleaving depth, the pre-interleaver design incorporates techniques such as characteristic polynomial parallelization, logic expansion, and register-based memory with interleaving technology. The resulting pre-interleaver is realized using 65nm CMOS technology and occupies an area of 0.615mm², inclusive of I/O pads. Experimental measurements highlight the system's capability to achieve a horizontal opening degree of 0.925UI at a data rate of 41.6Gb/s. Additionally, the system demonstrates a total power consumption of 38.52mW, operating at a supply voltage of 1.2V and a frequency of 1.3GHz.

 

However, this work in the present form needs a major revision due to the following reasons:

 

1.     Introduction: While the introduction provides valuable information about the context and the problem being addressed, there are a few drawbacks or areas that must be improved:

·       The introduction is quite dense and contains a lot of technical information in a single paragraph. Breaking it down into smaller, well-organized sections with clear subheadings can make it easier for readers to understand and follow the content.

·       Some sentences are quite long and complex, which can make the content harder to grasp. Simplifying sentence structure and using concise language can enhance readability.

·       The introduction contains several technical terms and acronyms (e.g., DFE, FEC, PRBS) that might be unfamiliar to readers who are not experts in the field. It's a good practice to briefly explain these terms the first time they're introduced or provide a glossary of terms.

·       Some sentences appear disjointed, making it challenging to follow the logical flow of the argument. Using transition words and phrases can help to connect ideas and improve the overall coherence.

·       While the introduction mentions the increase in data rates and the signal integrity problem, it could benefit from a clearer explanation of why this problem is significant and how it impacts practical applications. Providing a brief background and motivation can help readers understand the importance of the research.

·       It would be helpful to explicitly state the research gap or problem that the paper aims to address. Additionally, outlining the specific contribution of the paper in addressing this gap can provide readers with a clear sense of what to expect from the study.

·       The introduction discusses technical concepts related to signal integrity and transmission technology. Incorporating relevant diagrams or figures could visually enhance the understanding of these concepts.

·       The introduction should ideally conclude with a concise summary of the challenges being addressed, the proposed approach, and the potential benefits of the research.

 

 

2.     DFE Error Propagation: The section provides a clear explanation of DFE (Decision Feedback Equalizer) error propagation, but there are a few aspects that must be considered drawbacks or areas for improvement:

 

·       The section uses technical terms and acronyms (e.g., ISI, DFE, brl) without clear explanations. This might make it difficult for readers who are not experts in the field to understand the content fully. Providing brief explanations or a glossary could help alleviate this issue.

·       Equation without Explanation: Equation (1) is introduced without a detailed explanation. Providing a brief description of the equation and its components would help readers follow the mathematical aspect of the discussion.

·       The transition between explaining DFE error propagation and introducing Figures 1 and 2 is somewhat abrupt. Adding a smoother transition or a brief summary before introducing the figures could improve the flow.

·       While the section focuses on DFE error propagation, it might benefit from a brief contextualization explaining why DFE error propagation is a significant concern. Providing a sentence or two on the implications of error propagation on overall system performance could help engage readers.

·       When referring to Figures 1 and 2, it's a good practice to include a citation to indicate their source. For example, "Figure 1 shows the DFE error propagation process [source]."

·       The section ends quite abruptly after introducing Figures 1 and 2. It could be helpful to conclude the section by summarizing the significance of DFE error propagation and linking it back to the broader topic of the paper.

 

 

3.     Pre-interleaving Technology: While the provided section contains valuable information about the results of the pre-interleaving technology, there are a few potential drawbacks or areas that must be considered for improvement:

·       The section primarily focuses on the positive aspects and results of the pre-interleaving technology. It's important to also include a balanced discussion of any potential drawbacks, limitations, or challenges associated with the proposed solution.

·       While the section discusses the implementation and performance of the pre-interleaving technology, it could strengthen its impact by explicitly connecting these results to the research questions or objectives mentioned earlier in the paper.

·       Including more visual aids, such as diagrams, graphs, or tables, could help in better understand the described architectures, processes, and performance metrics.

·       It could be useful to elaborate on how the achieved results relate to practical implications. For instance, how does the improvement in performance translate to real-world scenarios or applications?

·       The section could benefit from a more detailed comparison with existing or similar solutions in the literature. This could provide context for readers to understand how the proposed pre-interleaving technology compares to other approaches.

·       Mentioning the limitations or potential areas for improvement in the current design could add depth to the discussion. Additionally, discussing potential directions for future research based on the findings could be insightful.

Comments for author File: Comments.pdf

Extensive editing of English language required.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

The paper has some contributions. However, I have some concerns. My comments are as follows.

Add contributions in bullet points at the end of the introduction section.

Reference equations that do not belong to you.

Could you elaborate on the specific techniques used to mitigate DFE error propagation in the proposed symbol pre-interleaving Bit 13 MUX (PBM)?

Can you explain how the interleaving gain of 0.35dB was theoretically obtained in the context of the 5-tap DFE architecture?

Could you provide more information about the parallelization, logic expansion, and register-based memory techniques employed in the pre-interleaver?

The literature review is very limited; you need to add a literature review section to the paper.

It is not clear what the problem or limitations are in the existing work, and what your contribution or proposed solution is for that problem.

Could you provide more details about the specific improvements achieved through the characteristic polynomial parallelization and logic expansion methods? How did these methods contribute to the significant enhancement in performance?

Can you elaborate on the challenges or limitations you encountered during the design and fabrication of the pre-interleaver? How were these challenges addressed or mitigated?

Considering the suitability of the circuit for mitigating DFE error propagation in a 400Gb/s Ethernet link system, what specific scenarios or conditions were tested to validate this suitability? Were there any scenarios where the circuit's performance faced limitations?

Please add the flowchart depicting the proposed methodology in the paper to assist the reader.

Include the pseudocode for the proposed method as well, and discuss its complexity.

A simulation and results section should be added before the conclusion section (Update the heading and settings), in which you discuss the tools used and parameter values for your experiments.

Please elaborate a bit more on the conclusion.

Please review and revise the manuscript as a few sentences are complex and not easy to go with.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 3 Report

In this manuscript, the author investigated a high-depth pre-interleaver for DFE error propagation and comprehensively demonstrated with experimental results. The results are well presented and the manuscript is well organized. Therefore, I don't have concerns and comments about the technical information of this paper. However, many typos inside and must be revised before publication. Points below:

1) Figure 4 should be revised for better explanation. For example, prbsout_inte and dataout_valid overlap.

2) There are two Figure 9 and two Table 1 in the manuscript, please revise.

3) For the second Figure 9 (should be Figure 10), resolution is too low. It seems directly screenshot from the oscilloscope. Please improve.

4) Some typos inside, for example, page 3 line 112. Should be "We have given"

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 4 Report

Your paper entitled, “41.6Gb/s High-depth Pre-interleaver for DFE Error Propagation in 65nm CMOS Technology,” is well written.  The electronics circuits design community can benefit from an advanced circuit that mitigates decision feedback equalizer (DFE) error propagation in 400Gb/s Ethernet SerDes interface. Your high-speed, 41.6Gb/s, pre-interleaver with parallel PRBS generator in 65nm LP CMOS technology reduces the transmission latency to meet the high data rate requirement.  The advanced technique has advantages over conventional techniques that have speed limitation.

 My comments/recommendations are provided below.

·         PBM is defined in the Abstract. Recommend that PBM be defined in the Introduction also.

·         Recommend that DFE be defined in the Abstract and the Introduction.

·         Recommend that PRBS be defined in the Introduction.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 5 Report

The work presented is of great relevance and presents very interesting and useful results. However, the manuscript is very limited in the presentation of the methodology and the mathematical bases used. In general, the theoretical basis of the research is based on limited assumptions and suppositions that have not been verified by the authors, or in their case, with few scientific references.

It is recommended to explain in detail the proposed formulation of error propagation in the optimization model, since it is the basis of the contribution proposed by the authors. The paper can be published once the authors consider the following recommendations:

It is only necessary to further detail the procedure of presenting the form of the series used. It is not clear how a Markovian process is formed. Explain.

Line 87-89. Strictly with a Monte Carlo process, if you start with a random number correctly, there should be no errors. The errors would be the product of the model, not of the initial random number. In such a case generate the random numbers with the Box-Muller method which is widely known in the literature.

Line 92-93. Another important aspect is why the authors can claim that the error propagation is temporarily interrupted? The authors at this point in their manuscript have not defined how they calculate this error. Only Figure 1 is used to "schematize" the error. In stochastic models of the ARMA (p,q) type, the Monte Carlo model is a particular case. In these cases the modeling error is not trivial. For example, the Akaike's Criterion (AIC) is used to select the best model. Therefore, it is difficult to verify what the authors claim if the error has not been previously defined.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

The manuscript can be published in its current form

Reviewer 2 Report

I have no further comments.

I have no further comments.

Reviewer 3 Report

In this revised version, the author has resolved all my concerns and questions. Therefore, I do recommend this paper to be published in this journal. 

Reviewer 5 Report

The authors responded scrupulously to each of the observations I made.

The authors restructured the manuscript very properly.

The restructuring of section 3.3 is very clear and correct. Besides the inclusion of two appendices, very good, excellent.

The paper should be accepted.

Very good work.