Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors

Abstract

Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latches’ output to the input of the memristor-based NOR two-stage inverse-phase memristor-based master–slave DFF. Then, a 3-bit flash ADC was designed using the new DFF and simulated to demonstrate its feasibility and correctness. Additionally, a 4-bit flash ADC was implemented and utilized to sample an analog signal, resulting in a correct digital signal. Herein, the 50 nm BSIM4 models were applied. The 3- and 4-bit flash ADCs, respectively, consumed 1.33 mw and 5.84 mw power at a 1 V supply with delay times of 17.8 ns and 70 ns. Compared with previous work, the new 4-bit flash ADC has fewer transistors and smaller power consumption, with about a 25.57% reduction according to the 90 nm process.

1. Introduction

According to the symmetry of the relationship between each pair in current i, voltage v, charge q, and flux $\phi$, there should be a fourth fundamental circuit element to describe the relation between q and $\phi$. Thus, the fourth passive circuit component after resistance, capacitance, and inductance, namely the memristor, was predicted theoretically by Prof. Chua in 1971 [1]. This prediction was confirmed by the successful preparation of the Hewlett-Packard (HP) memristor in 2008 [2], which, for the first time, correlated the theoretical concept of memristors to the actual physical device implementation.

Memristors can be dynamically programmed by applying bias, and their state is not lost even after removing the power supply. This functionality of memristors cannot be replicated by the fundamental circuit elements. As the devices scale down, memristors provide a new approach to continue Moore’s law and overcome the bottlenecks of a conventional computer with a von Neumann architecture. Memristors have many advantages, such as nanoscale size, simple structure, extremely fast working speed, low power dissipation compared to traditional devices, and compatibility with traditional CMOS processes [3,4,5]. Applications of memristors include non-volatile memories [6], artificial neural networks [7,8,9,10,11], digital logic operations [12], chaotic circuits, and other fields [13,14,15]. The future development and applications of memristors are reviewed in [16].

The speed, accuracy, and power consumption of an Analog-to-Digital Converter (ADC) directly influence the performance of Digital Signal Processing (DSP). The ADC design is a vital part of many applications such as Ultra-Wide-Band (UWB) communication circuits, radar systems, optical data recording systems, optical communication systems, and disk drives. There are various ADC architectures, such as Successive Approximation Register (SAR) ADC [17], pipeline ADC [18,19], double-ramp ADC, and flash ADC [20,21], among which flash ADC stands out for its notable speed, and it is particularly advantageous in low-resolution and high-speed applications owing to its straightforward design and superior throughput. However, compared to other ADCs, flash ADC exhibits a significant drawback, where the scale of the circuit expands rapidly with the improvement in accuracy. Consequently, a high power-supply voltage and a large chip area are needed due to the high power consumption of the numerous components that are used [21,22]. Thus, a comprehensive innovative ADC design from the aspects of the process, device, and structure should be proposed to reduce the chip area and power consumption. Researchers have made various efforts in recent years, such as applying 65 nm CMOS technology to design an ADC that only dissipates 15.5 mW when working at 20 GSps with a 1V supply [23], proposing recoil noise suppression technology to decrease the power consumption of comparators [24], using Tunnel Field Effect Transistors (TFET) to reduce the power consumption of ADCs [25], and proposing an ADC with high performance in power-supply voltage, power consumption, and frequency based on a novel Block-Driven Quasi-Floating Gate (BD-QFG) Current Mirror (CM) structure [26].

So far, there is limited research on building ADCs based on the logic circuit of memristor design, specifically, a novel technique (memristor-based logic circuits) applied to 3-bit flash ADCs to reduce the supply voltage, power consumption, and area. The rest of this paper is organized as follows. Section 2 introduces the memristor model. Section 3 introduces the logic circuit, composed of the memristor and CMOS transistor, and the flip-flop circuit. In Section 4, the proposed mode flash ADC structure is described. Section 5 presents the conclusions.

2. Memristor Model

The mathematical expression of a memristor is

$$v\left(t\right)=M\left(q\right(t\left)\right)i\left(t\right)$$

(1)

where, v, q, and i represent the voltage, charge, and current, respectively. $M\left(q\right)$ represents the resistor value of the memristor. The expression of the memristor is characterized by its memristance function, which describes the charge-dependent rate of change of flux with charge. Also, the flux is defined as the time integral of the voltage, and the charge is defined as the time integral of the current. It can be expressed as

$$d\phi =Mdq$$

(2)

The first physical memristor device fabricated using titanium dioxide [2] by the research team at the HP laboratory is shown in Figure 1,

$W_1$ and $W_2$ are the widths of the doped region and the undoped region, respectively, and D = $W_1$+ $W_2$ denotes the total length. Positive-charged oxygen vacancies within the doped region of this device can be diffused to the undoped region under a forward bias, resulting in a low resistance state, denoted as $R_{ON}$ [27]. On the contrary, the memristor resistance becomes highly noted as $R_{OFF}$ when an inverse bias is added. The inset in Figure 1 is the circuit symbol of a memristor. To simulate various published memristors more accurately, a general memristor SPICE model was proposed in [28]. This model was tested in large circuits with up to 256 memristors. It is less prone to convergence errors compared to other models, and the current and voltage relationship of the metal–insulation–metal memristor can be properly simulated. Additionally, a threshold voltage function is constructed based on the motion-of-state variables, and a nonlinear rate function is constructed based on the hole and ion drift. The memristor model is denoted as

$$I\left(t\right)=\left\{\begin{array}{c}{a}_{1}x\left(t\right)sinh\left(bV\left(t\right)\right),V\left(t\right)\ge 0\\ a_{2}x\left(t\right)sinh\left(bV\left(t\right)\right),V\left(t\right)<0\end{array}\right.$$

(3)

where $I\left(t\right)$ and $V\left(t\right)$ represent the current and voltage, respectively, and $a_1$, $a_2$, and b are real numbers.

3. Memristor-Based Basic Logic Gate and D-Flip-Flop

3.1. Logical OR/NOR and AND/NAND Gates

Kvatinsky first proposed logic circuits constructed using memristor CMOS hybrids in [3]. The AND and OR gates are composed of two serial memristors with identical and opposite polarity, respectively. The positive ends of the two memristors in the AND gate are connected to the input voltage signals, whereas the negative ends in the OR gate are connected to the input. Logic NAND and NOR gates are constructed by connecting a CMOS inverter to the output ends of the AND and OR gates, respectively.

The simulation results are shown in Figure 2. The delay times for the OR/NOR and AND/NAND gates are 0.183 ns and 0.176 ns.

3.2. Memristor-Based Edge-Triggered D-Flip-Flop

Flip-flops are basic logic components with memory functions, which are widely used to store initial data and calculated results in digital signal processing systems. A traditional CMOS-based NOR-constructed master–slave DFF consists of two identical latches. Each latch has a two-stage inverse-phase structure. If a memristor-based NOR is used instead, it is easy to combine memristors and feed back the master latches’ output to the input. Therefore, the proposed negative edge-triggered DFF’s structure can be simplified, as depicted in Figure 3, resulting in enhanced area and energy efficiency.

The simulation results demonstrate that the output changes to the input D at the clock’s falling edge and remains unaffected at other times, as shown in Figure 4. The simulation results conform to the DFF’s truth table described in

Table 1. Truth table for the edge-triggered DFF.

CLK	D	Q
*	•	maintain
↓	1	1
	0	0
	•	maintain

The symbol */•/↓ is interpreted as the state of the trigger at the falling edge.

and verify the feasibility of the new DFF. In addition, The delay time of D-flip-flop is 0.497 ns. Then, the proposed DFF is used to design the subsequent flash ADC circuit.

4. Design of N-Bit Flash ADC

4.1. Traditional N-Bit Flash ADC

A traditional N-bit Flash ADC is composed of an N resistor ladder, $2^N$ − 1 comparators, $2^N$ − 1 flip-flops, and a priority encoder, as shown in Figure 5. The output of the comparator is a logic 1 when its input voltage exceeds the corresponding input reference voltage, whereas it is a logic 0 when the input voltage is less than the reference voltage. Each comparator’s reference voltage is increased by 1 least significant bit (LSB), from the lowest value to the highest, until it reaches the most significant bit (MSB). The outputs of all $2^N$ − 1 comparators are stored in latches and transmitted to the priority encoder to generate digital outputs. Although the flash ADC operates very quickly because the analog input is fed to all the comparators simultaneously, the presence of a large number of DFFs and the combined logic gates of the encoder lead to an increase in area, power consumption, and cost. Therefore, memristors are mainly used in the design of DFFs and encoders, leading to improvements in area, energy efficiency, and cost-effectiveness.

4.2. New 3-Bit Flash ADC

A 3-bit flash ADC with the architecture shown in Figure 5 requires seven latches to store the output data of the comparators. If the priority encoder is designed to receive the comparators’ output data and provide input to registers, four latches will be saved. The register module demonstrated here is composed of the DFFs designed in the third section, as depicted in Figure 6.

If the analog voltage is less than $\frac{1}{14}$$V_{REF}$, all comparators’ outputs are low levels. If the analog voltage is larger than or equal to $\frac{13}{14}$$V_{REF}$, all comparators’ outputs are high levels; otherwise, if the analog voltage is larger than $\frac{2i-1}{14}$$V_{REF}$ and less than $\frac{2i+1}{14}$$V_{REF}$, only the comparator whose subscript is less than or equal to i outputs a high level. The input range of the analog voltage is between 0 and $\frac{15}{14}$$V_{REF}$. All the states of the comparators are listed for different input analog voltages, as shown in

Table 2. Code conversion table for the circuit shown in Figure 6.

Input Analog Voltage ${\mathit{V}}_1$	State of the Comparator Output							Output of ADC
	${\mathbf{V}}_{\mathbf{C}\mathbf{7}}$	${\mathbf{V}}_{\mathbf{C}\mathbf{6}}$	${\mathbf{V}}_{\mathbf{C}\mathbf{5}}$	${\mathbf{V}}_{\mathbf{C}\mathbf{4}}$	${\mathbf{V}}_{\mathbf{C}\mathbf{3}}$	${\mathbf{V}}_{\mathbf{C}\mathbf{2}}$	${\mathbf{V}}_{\mathbf{C}\mathbf{1}}$	${\mathbf{d}}_{\mathbf{2}}$	${\mathbf{d}}_{\mathbf{1}}$	${\mathbf{d}}_{\mathbf{0}}$
(0∼$\frac{1}{15}$)$V_{REF}$	0	0	0	0	0	0	0	0	0	0
($\frac{1}{15}$∼$\frac{3}{15}$)$V_{REF}$	0	0	0	0	0	0	1	0	0	1
($\frac{3}{15}$∼$\frac{5}{15}$)$V_{REF}$	0	0	0	0	0	1	1	0	1	0
($\frac{5}{15}$∼$\frac{7}{15}$)$V_{REF}$	0	0	0	0	1	1	1	0	1	1
($\frac{7}{15}$∼$\frac{9}{15}$)$V_{REF}$	0	0	0	1	1	1	1	1	0	0
($\frac{9}{15}$∼$\frac{11}{15}$)$V_{REF}$	0	0	1	1	1	1	1	1	0	1
($\frac{11}{15}$∼$\frac{13}{15}$)$V_{REF}$	0	1	1	1	1	1	1	1	1	0
($\frac{13}{15}$∼1)$V_{REF}$	1	1	1	1	1	1	1	1	1	1

. Only one comparator is output for each analog input, so the output of all seven comparators can be encoded as a 3-bit code, as depicted in Table 2. The logic function expression of the priority encoder can be simplified as

$$\left\{\begin{array}{c}{d}_0=C_1+C_3+C_5+C_7\\ d_1=C_2+C_3+C_6+C_7\\ d_2=C_4+C_5+C_6+C_7\end{array}\right.$$

(4)

The priority encoder is shown in the middle of Figure 6. When the input analog voltage range is different, the digital output corresponds to that in Table 2, which verifies the correctness of the circuit designed in this paper.

The outputs of the comparators and digital codes corresponding to the different input analog voltage ranges are listed in Table 2. Accordingly, the simulation results for the new memristor-based 3-bit flash ADC are shown in Figure 7. It is clear that the simulation results are consistent with the ADC’s output, which verifies the correctness of the circuit designed in this paper.

4.3. New 4-Bit Flash ADC

Based on the above 3-bit design, a memristor-based 4-bit flash ADC was designed. According to the functionality of the 4-bit flash ADC, the logical relationship between the input and output of the code conversion circuit can be written as:

$$\left\{\begin{array}{c}{d}_3=C_8\hfill \\ d_2=C_{12}+{\overline{C}}_8{C}_4\hfill \\ d_1=C_{14}+{\overline{C}}_{12}{C}_{10}+{\overline{C}}_8{C}_6+{\overline{C}}_4{C}_2\hfill \\ d_0=C_{15}+{\overline{C}}_{14}{C}_{13}+{\overline{C}}_{12}{C}_{11}+{\overline{C}}_{10}{C}_9+{\overline{C}}_8{C}_7\hfill \\ +{\overline{C}}_6{C}_5+{\overline{C}}_4{C}_3+{\overline{C}}_2{C}_1\hfill \end{array}\right.$$

(5)

Then, a new code converter was designed using memristors, as shown in Figure 8. A new 4-bit flash ADC was implemented by applying the new code converter, and the simulation was executed to sample an analog signal, as shown in Figure 9. The simulation results demonstrate the functionality of the memristor-based 4-bit flash ADC, which had a delay time of 70 ns and power consumption of 5.84 mw.

A detailed comparison of existing flash ADCs [23,24,25,26] and the one proposed in this work is shown in

Table 3. Comparison of this work and recent reports on flash ADCs.

Item	Ref. [23]	Ref. [24]	Ref. [25]	Ref. [26]	This Work	This Work
Resolution (bits)	4	4	4	4	3	4
Technology	65 nm	90 nm	-	0.18 nm	50 nm	50 nm
Input signal (V)	0.6–0.9	0.1–1	0.1–1	0–0.8	0–1	0–1
Voltage (V)	1	1.8	1	0.8	1	1
Delay (ns)	-	100	11	0.16	17.8	70
Power (mw)	15.5	7.846	0.75	118.24	1.33	5.84
Transistors	180	165	82	266	36	62
Memristors	0	0	0	0	51	88

, showing that the one proposed in this work improves the power efficiency, delay time, and transistor number.

5. Conclusions

Due to their many advantages compared to traditional devices, memristors have been utilized to construct master–slave DFFs. It is easy to combine memristors and feed back the master latches’ output to the input. A new edge-triggered DFF was proposed, utilizing a memristor-based NOR two-stage inverse-phase DFF structure. Then, new memristor-based N-bit flash ADCs were implemented. To verify the feasibility of the new flash ADCs, a 3-bit flash ADC was designed and the results of the simulation for each sample demonstrated its correctness, as shown in Figure 7. A new 4-bit flash ADC was also designed and verified to sample an analog signal. The proposed 3-bit flash ADC consumed 1.33 mw power with a supply voltage of 1 V and a delay time of 17.8 ns, and the 4-bit flash ADC consumed 5.84 mw power with a delay time of 70 ns. Compared to existing flash ADCs, the transistors were also clearly reduced. However, the compatibility of the memristor was only verified for 3-bit and 4-bit flash ADC circuits. In large-scale integrated circuits, the crosstalk, temperature, and other factors can cause device drift or even failure, which impacts the stability of the circuit, so it needs further research and a fault-tolerant design. In addition, the nonlinearity of the memristor model will inevitably affect the subsequent circuit design. Later, we will focus on the effect of the variability of memristor devices on the nonlinearity of the circuit design.