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Article
Peer-Review Record

A Fast-Lock Variable-Gain TDC-Based N/M-Ratio MDLL Clock Multiplier

Electronics 2023, 12(19), 4136; https://doi.org/10.3390/electronics12194136
by Chaeyoung Jang and Jongsun Kim *
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Electronics 2023, 12(19), 4136; https://doi.org/10.3390/electronics12194136
Submission received: 29 August 2023 / Revised: 28 September 2023 / Accepted: 3 October 2023 / Published: 4 October 2023
(This article belongs to the Special Issue Mixed Signal Circuit Design, Volume II)

Round 1

Reviewer 1 Report

I have some comments.

1. The originality is not clear. Please describe the major difference between the related designs by the fixed gain TDC approach.

2. DCO is an important circuit block. The authors should give the details such as circuit design and simulation results of this block.

3. The high speed divider circuit is also very important. This block should be shown and discussed.

4. Post-layout simulation results are very limited.

5. No histogram results of this complete MDLL output.

6. The analysis of the lock time should be demonstrated.

Author Response

Thank you for allowing a resubmission of our manuscript, with an opportunity to address the reviewers’ comments.

We are uploading

(a) our point-by-point response to the comments (response to reviewers),

(b) a clean updated manuscript without highlights (Main Manuscript).

Author Response File: Author Response.pdf

Reviewer 2 Report

This manuscript presents a variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier. The logic of the proposed control strategy is clear. Sufficient examples show the effectiveness of the proposed method. All in all, this paper is well presented and easy to follow. Some minor revisions are necessary, and my suggestions are as follows:

(1) The literature review part could be improved, since the Part 1 Introdiction of the manuscript is not enough the research status of the introduction is insufficient, and there is no comprehensive summary of the current important research in this field, especially more literature on variable-gain clock multipfier should be added.

(2) All the results and comparison have proved the feasibility of the proposed method. But it is suggested that the limitations and shortcomings of this proposed method should be mentioned in this paper, so as to give the future research prospects.

Author Response

Thank you for allowing a resubmission of our manuscript, with an opportunity to address the reviewers’ comments.

We are uploading

(a) our point-by-point response to the comments (response to reviewers),

(b) a clean updated manuscript without highlights (Main Manuscript).

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

The quality has been improved. I think this revised paper is suitable for publication in this Journal.

Author Response

We'd like to thank the reviewer for their valuable and generous reviews.

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