1. Introduction
There is a wide variety of natural phenomena in science and engineering applications that exhibit chaotic behavior, whose main property is a high sensitivity to initial conditions. Such phenomena can be modeled by integer or fractional-order chaotic systems, and their randomness can be exploited to develop engineering applications. In particular, the electronic design of chaotic systems is generally performed using embedded systems, such as field-programmable gate arrays (FPGAs), due to its popularity for fast prototyping. It has also been shown that the mathematical models of either integer or fractional-order chaotic systems can be optimized to generate better chaotic behavior, as shown in [
1], where the authors show how the optimized models can be implemented using commercially available amplifiers, field-programmable analog arrays (FPAA), FPGAs, micro-controllers, and nanometer technology of integrated circuits (ICs). The big challenge is the development of an electronic design automation (EDA) tool with the capabilities of optimizing the mathematical model, macro-modeling of the chaotic system, and designing of the blocks using complementary metal–oxide–semiconductor (CMOS) IC technology. In this manner, this paper summarizes recent advances on the development of EDA tools for analog design of chaotic systems that require the design of filters, adders, subtractors, multipliers, and comparators. A case study is given to show the optimization, block description, and CMOS design of a fractional-order chaotic system.
Recently developed EDA tools perform the design of electronic systems in a hierarchical fashion, as shown in [
2], where the authors cover the device, circuit, and system levels for radio-frequency ICs. This is a big problem known as physical design that requires a massive amount of computer resources in order to meet the tape-out schedule [
3] and to mainly accomplish target specifications that support process variations, for instance. Some works introduce systematic and multilevel approaches [
4], and others pay special attention to the placement of the circuit blocks [
5,
6]. Modern EDA tools include optimization [
7,
8] and machine learning [
9]. These combinations of design methods allow one to guarantee the layout generation [
10], which sometimes requires one to have the lowest silicon area [
11,
12,
13]. The authors of [
14] introduced the automated design of analog circuits, whose algorithm not only successfully reaches unique, valid, and practical performances, but also does so in state-of-the-art run time, achieving target specifications post-layout for the folded cascode amplifier. Such a task was also performed by some authors applying multi-objective optimization algorithms [
15,
16,
17], and recently by applying many-objective algorithms [
18]. Those EDA tools include process variations and statistical analyses to guarantee robust design. Others put emphasis on the layout generation [
19] and yield-aware optimization in nanometer-scale technologies [
20]. These EDA tools inspired this work to use three levels of abstraction to design fractional-order chaotic systems: The first one is devoted to showing the application of metaheuristics to find the coefficients and the fractional-orders of the derivatives that generate better chaotic behavior from a mathematical model. The second level is the block description of the mathematical model, in which the fractional-order derivatives are approximated in the Laplace domain. The third level shows the IC design using CMOS technology of 180 nm.
Researchers involved in real applications of chaotic systems, such as the design and synchronization of random number generators (RNGs) [
21], generally use FPGAs to verify the generation of a chaotic attractor, as already shown in [
1,
22,
23,
24]. However, for low power consumption and wireless applications, the design of CMOS ICs is recommended, as they can be fabricated in a very-low silicon environment. The CMOS design of chaotic systems is not new; it was done three decades ago for the introduction of the IC chip of Chua’s circuit [
25], using 2
m technology, occupying a silicon area of 2.5 mm × 2.8 mm, and biased with a single 9V battery. The authors highlighted that the CMOS IC can be employed as a basic component in the design of complex circuits making use of chaotic signals, including a class of cellular neural networks and secure communication systems. By the same time, the authors of [
26], introduced a CMOS IC design of a chaotic discrete-time system for the generation of broadband white noise using 3
m technology. From recent times, one can find CMOS designs of chaotic systems using CMOS technology of 180 nm, provided from different fabrication companies [
27,
28,
29,
30,
31,
32]. These IC designs can be improved by performing variation analyses of the process (voltage and temperature) and Monte Carlo simulations [
33]. Further, those robust designs can be used to design random number generators [
34,
35], which have shown real engineering applications, such as for the design of a CMOS high-data-rate true random bit generator through delta sigma modulation [
36]. Other applications of CMOS chaotic systems are the design of high-precision analog-to-digital converter (ADC) calibration systems [
37], a 1 Gbps chaos-based stream cipher [
38], and a chaos-key based data encryption system, in which the data secrecy is compared to the advanced encryption standard (AES) [
39]. Regarding fractional-order chaotic systems, there have been very few trials generating CMOS designs, as shown in [
18,
40,
41].
The organization of the paper is as follows:
Section 2 shows the adaptation of an optimization algorithm to fractional-order chaotic systems,
Section 3 shows the approximation of the fractional-order derivatives in the Laplace domain,
Section 4 shows the CMOS design of a fractional-order chaotic system, and
Section 5 summarizes the results and shows the suitability for the development of an EDA tool for the design of CMOS fractional-order chaotic systems. Finally, the conclusions are given in
Section 6.
4. CMOS Design of a Fractional-Order Chaotic System
This section shows the CMOS design of the fractional-order integrators to implement Chen system given in (
10) that was proposed by [
32]. As shown above, in order to design a CMOS IC, the coefficients are set to:
,
, and
to reduce the amplitudes of the state variables to be within ±1 or lower. As observed in
Figure 5, the portraits show amplitudes of around ±0.5, good enough to design the fractional-order Chen system using CMOS technology of 180nm from UMC. The first step of the design process is the synthesis of the fractional-order integrators that have been proposed in [
47] and given in (
11) and (
12). Both fractional-order integrators can now be approximated by using bi-quadratic and low-pass filters, which are shown in
Figure 6a and
Figure 6b, respectively, and the topologies use operational transconductance amplifiers (OTAs). These OTA-based filters are taken from [
48], which have the transfer functions given in (
13) for the bi-quadratic filter, and (
14) for the low-pass filter.
The transfer function given in (
11) approximates the fractional-order integrator
. As the denominator is of order five, it can be separated into two functions of second-order, and one of first-order. In this manner, (
11) can be decomposed by the functions given in the right-hand sides of (
15)–(
17), which are synthesized by the OTA-based active filters as follows.
In (
13), one can set
and
, so that the resulting transfer function of the circuit shown in
Figure 6a can be described by (
15), which is associated with the first second order transfer function taken from (
11). If
A/V, then
F and
A/V. Additionally,
mF and
mA/V.
The second quadratic function given in (
16) is solved by also setting
A/V, but now the circuit elements are evaluated as:
nF and
A/V. Additionally,
F and
mA/V.
The first-order low-pass filter shown in
Figure 6b, is used to synthesize (
17). If
A/V, the capacitor value will be
F, and therefore,
K
.
To carry out the design of the fractional-order integrator described in (
12), in which
, the transfer function can be split into two functions, one of second-order and one of first-order, as given in (
18) and (
19), respectively.
From (
18) and (
13) and by setting again
and
, one gets (
20). If
A/V, the capacitor and transconductance values are obtained as:
F and
A/V; and
F and
mA/V. In a similar way, the low-pass filter shown in
Figure 6b is synthesized by the circuit element values evaluated as: if
A/V, the capacitor value will be
F, and therefore,
K
.
Figure 7 shows the gain and phase behaviors of the approximated fractional order integrators of orders 0.8 and 0.9, and the responses are compared with MatLab simulations of (
11) and (
12), which show very low error, so that the OTA-based designs are suitable to perform the CMOS design of the fractional-order system given in (
10).
To complete the CMOS design of (
10), the need for designing two two-input adders and one three-input adder can be inferred; these are shown in
Figure 8 using OTAs. To explain how these adders work, let us consider the adder in
Figure 8a: the output of this adder must be equal to
, so that
y is connected to the positive input of the OTA
gm and the variable
x to the negative input of the OTA
. However, these OTAs must scale the values of the variables
y and
x by
. Therefore: if
gm is equal to 500
A/V, then
gm and
gm should be equal to 175
A/V. A similar analysis should be performed for the other adders. It is important to mention that one of the most important characteristics of an OTA to design these adders and active filters is its transconductance (
) value. In this work, the designed OTA is shown in
Figure 9. This topology allows controlling the value of the transconductance through the resistances in the sources of the MOS transistors, i.e., those forming the differential pair. The Rs can be designed with MOS transistors, as detailed in [
33].
Table 5 shows the electrical characteristics for different
values of the OTA that is used for the design of the CMOS fractional-order chaotic system.
Figure 10 shows the layout of the OTA providing
A/V, and
Figure 11 shows the layout of the fractional-order integrator of 0.9.
The convolutions given in (
10) (
and
) were implemented using a four-quadrant multiplier, as the one already given in [
49]. As a result, the attractors of the CMOS design of the fractional-order chaotic system given in (
10), and using CMOS technology of 180 nm are shown in
Figure 12.
5. Discussion of Results
As shown in the previous sections, the IC design of fractional-order chaotic systems by using CMOS technology can be performed through the optimization of the mathematical model by metaheuristics. The design process can then be performed considering three major levels of abstraction; each one can be considered as a challenge to develop EDA tools. The highest level has been highlighted in
Section 2, describing the adaptation of an optimization algorithm to optimize fractional-order chaotic systems from the mathematical model, in order to maximize dynamical characteristics, such as Lyapunov spectrum and Kaplan–Yorke dimensions. It has been appreciated that in this level of abstraction, the amplitudes of the state variables of a mathematical model can have large values, higher than those supported by a CMOS design, which in this case the CMOS technology of 180 nm leads us to scale the mathematical model to provide amplitudes within ±1 or lower.
Optimizing the mathematical model of a fractional-order system, as for the ones given in (
3) and (
4), includes varying the values of the orders of the derivatives, which are higher than zero but lower than one. More case studies are already given in recent works and in the book [
1], where one can find a summary on the single, multi, and many-objective optimization algorithms applied to chaotic systems of integer and fractional-order. One can also associate this optimization process with the system level when considering the design of electronic systems, as described in [
2].
The second level of abstraction proposed in this work is described in
Section 3, which highlights the block description of a mathematical model, and the particular interest is the approximation of the fractional-order derivatives in the Laplace domain. This is not a trivial task, so several authors have been introduced different methods to perform the rational approximations of arbitrary order, as recently done in [
50], where the authors summarize several rational approximations of arbitrary order for differentiators and integrators in the frequency domain. Basically, similar works that introduce methods to approximate and arbitrary order, use the basic definitions already given by Riemann–Liouville, Grünwald–Letnikov and Caputo. One can think on the exactness of each method along with their advantages and disadvantages, since each method approximates the arbitrary order with polynomials of high order, thereby generating different errors. Some authors also introduce methods to reduce the polynomial orders; those methods are known as model-order-reduction (MOR) ones and are quite suitable in the design of very large scale integration (VLSI) systems, as shown in [
51]. In fact, MOR techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. In this paper, the fractional-orders of the derivatives, i.e., 0.8 and 0.9, were approximated by applying Charef’s method [
46]. Those transfer functions are different from the ones that can be obtained applying other methods to approximate an arbitrary order, as detailed in [
50]. In the case of approximating an arbitrary order in the Laplace domain, higher-order polynomials can be reduced to have third or even second order, by allowing an increase in the error. This is still a challenge focused on the reduction of the polynomial order and generating low error in the band of interest.
The third level of abstraction described herein is oriented to the design of a fractional-order chaotic system using CMOS technology. In this manner, the transfer functions approximating the fractional-order derivatives are implemented using topologies of active filters, and due to the exactness and reduced numbers of transistors, filters, adders, and subtractors, were designed using OTAs, as detailed in
Section 4. The first design step consists of scaling the amplitudes of the state variable to be within ±1 Volt or lower, as required by the CMOS IC technology of 180 nm. The next step is identifying the operations such as addition, subtraction, and multiplication, which can be designed using CMOS technology, and in some cases OTAs. The rational approximations of arbitrary order can then be designed using active filters, but the challenge is for the decomposition of higher-order polynomials to have second-order and first-order polynomials that can be associated with bi-quadratic and single pole/zero filters. The task of dealing with high-order polynomials can be solved by performing a partial fraction expansion, as shown in [
52]. The transfer functions can also be implemented using FPAAs, as shown in [
53].
Once a CMOS design is verified at the transistor level of abstraction, one can proceed to generate the layout [
10,
12], for which another problem in VLSI design is the placement and routing of the designed blocks [
5,
6,
13]. Recall that the first integrated chaotic system was introduced three decades ago [
25], so that the layout was not as complex as for VLSI circuits. Therefore, the authors conclude that working with these three levels of abstraction makes possible the design of CMOS ICs for fractional-order chaotic systems.
6. Conclusions
The electronic implementation of fractional-order chaotic systems can be performed by using commercially available devices, FPAAs, FPGAs, and microcontrollers. However, for low power and wireless applications, they are not as suitable as a CMOS IC, the design of which is not a trivial task. In this manner, this work proposed the design of CMOS fractional-order chaotic systems performing three main tasks, associated with three levels of abstraction. The first one, the high-level, was oriented to optimizing the mathematical model to guarantee chaotic behavior, which was verified evaluating the Fourier transform of the chaotic time series. In this level of abstraction, the coefficients and orders of the derivatives were varied to maximize the dynamical characteristics . As one can infer, this task can be performed using other metaheuristics to optimize a mathematical model.
The second level of abstraction was focused on the block description of a mathematical model, in which the arbitrary order of each of the derivatives was approximated in the Laplace domain. The challenge is still guaranteeing chaotic behavior during the approximation of the fractional-orders, since a slight error may mitigate chaotic behavior, and this influences the CMOS design of the chaotic system. Another important issue is the scaling process of the mathematical model to have amplitudes of the state variables within ranges that can be suitable for CMOS design. In this work, the amplitudes of the state variables of Chen and Liu systems were scaled to have values in the range lower than .
From the block description and Laplace approximation of the arbitrary orders, one can go to the third level proposed herein, the CMOS design, and layout generation. The case study was designed using OTAs, but one can think of using other active devices and also other active filter topologies. These could lead to designing robust CMOS chaotic systems that can support process and temperature variations. Finally, it was discussed that the layout generation is a challenge for sensitive systems, as for the chaotic ones.
The phase portraits of the CMOS fractional-order Chen system shown in
Figure 12 are in good agreement with the theoretical results. One can also perform variation analyses as already done in [
33]. Finally, from the results of the CMOS design, one can conclude on the suitability of performing the three levels of abstraction, which can lead to the development of EDA tools for chaotic systems.