Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits

Maljar, David; Sovcik, Michal; Potocny, Miroslav; Ondica, Robert; Arbet, Daniel; Stopjakova, Viera

doi:10.3390/electronics12224615

Open AccessArticle

Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits

by

David Maljar

,

Michal Sovcik

,

Miroslav Potocny

,

Robert Ondica

,

Daniel Arbet

and

Viera Stopjakova

^*

Department of IC Design and Test, Institute of Electronics and Photonics, Faculty of Electrical Engineering and Information Technology, Slovak University of Technology, Ilkovicova 3, 841 04 Bratislava, Slovakia

^*

Author to whom correspondence should be addressed.

Electronics 2023, 12(22), 4615; https://doi.org/10.3390/electronics12224615

Submission received: 12 October 2023 / Revised: 23 October 2023 / Accepted: 27 October 2023 / Published: 11 November 2023

(This article belongs to the Special Issue Advances in RF, Analog, and Mixed Signal Circuits)

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Abstract

This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC’s parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage

V_{I N_O F F}

of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the

V_{I N_O F F}

of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage

V_{D D}

= 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations.

Keywords: digital calibration; technology fluctuation; on-chip calibration techniques; FDDA; experimental verification; silicon-proved results; IC design; CMOS

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MDPI and ACS Style

Maljar, D.; Sovcik, M.; Potocny, M.; Ondica, R.; Arbet, D.; Stopjakova, V. Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits. Electronics 2023, 12, 4615. https://doi.org/10.3390/electronics12224615

AMA Style

Maljar D, Sovcik M, Potocny M, Ondica R, Arbet D, Stopjakova V. Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits. Electronics. 2023; 12(22):4615. https://doi.org/10.3390/electronics12224615

Chicago/Turabian Style

Maljar, David, Michal Sovcik, Miroslav Potocny, Robert Ondica, Daniel Arbet, and Viera Stopjakova. 2023. "Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits" Electronics 12, no. 22: 4615. https://doi.org/10.3390/electronics12224615

APA Style

Maljar, D., Sovcik, M., Potocny, M., Ondica, R., Arbet, D., & Stopjakova, V. (2023). Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits. Electronics, 12(22), 4615. https://doi.org/10.3390/electronics12224615

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

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Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits

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