Mitigating the Effects of Design for Manufacturability on Design Iteration Cycles in Advanced Integrated Circuit Design

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The article examines the problem of integrated circuit (IC) design. Iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuit. The authors proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM (design for manufacturability) parameters of all components in a circuit prior to the routing process. These parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components.

Proposed algorithm enables the generation of netlists that describe the internal connections and interconnections of each component, enabling designers to carefully evaluate and modify DFM parameters during a pre-postsimulation step. Once the layout and physical verification processes are complete, the designer can focus on parasitism induced by metal routing. The effectiveness of the proposed design process for reducing design iteration cycles was validated.

The choice of the select research papers is justified. The choice of proposed methods and mathematical models is justified. This approach is relevant. The research is of practical importance.

The conclusions correspond to the presented evidence and arguments, and they correspond to the basic question. The references appropriately. The tables, pictures and formulas meet the requirements.

1. In 2, 4, 6, 11 page - Error! Reference source not found.

2. There is no review of existing software implementations to of integrated circuit design.

Author Response

Response to Reviewers’ Comments

        We thank the Associate Editor for letting us revise this paper for resubmission. We also thank reviewers for thoughtful comments to enhance the paper quality. We have carefully addressed all reviewers’ comments and revised the manuscript accordingly.

Review report #1

The article examines the problem of integrated circuit (IC) design. Iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuit. The authors proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM (design for manufacturability) parameters of all components in a circuit prior to the routing process. These parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components.

Proposed algorithm enables the generation of netlists that describe the internal connections and interconnections of each component, enabling designers to carefully evaluate and modify DFM parameters during a pre-postsimulation step. Once the layout and physical verification processes are complete, the designer can focus on parasitism induced by metal routing. The effectiveness of the proposed design process for reducing design iteration cycles was validated.

The choice of the select research papers is justified. The choice of proposed methods and mathematical models is justified. This approach is relevant. The research is of practical importance.

The conclusions correspond to the presented evidence and arguments, and they correspond to the basic question. The references appropriately. The tables, pictures and formulas meet the requirements.

Response: thanks

1. In 2, 4, 6, 11 page - Error! Reference source not found.

Response:

Page 2: WPE and LOD effects are two factors that are often considered in DFM [2].

In [2], Implications of Proximity Effects for Analog Design, the importance of WPE and LOD effect was explained.

[2] https://ieeexplore.ieee.org/document/4114933

Although the PDK setting in [3] included the WPE and LOD, this illustrates that Cadence's ic layout tools can automatically generate a single device, even if the foundry has to consider the WPE/LDE is only a single device effect, rather than a whole group of IC Layout under the influence of each other's WPE/LDE effect.

[3] https://www.mics.ece.vt.edu/content/dam/mics_ece_vt_edu/ICDesign/Tutorials/tsmc180/n05_Layout%20Component%20Placement%20and%20Routing.pdf

 

Page 4:

The equations in the BSIM4.6.1 MOSFET Model User’s Manual [5].

[4] https://global.oup.com/us/companion.websites/9780195170153/pdf/proximityeffectmodels.pdf

[5] http://www.srware.com/xictools/docs/model_docs/bsim4.6.1/BSIM461_Manual.pdf

 

Page6 / Page11: This part is my own exposition so I have not quoted from other documents.

 

2. There is no review of existing software implementations to of integrated circuit design.

Response: The text marked in blue I added in the second paragraph "2. Approach to the new design process" (lines 198-222, 238-245)

 

Between lines 199 and 212, References [1] and [7] (new references number) are used to illustrate the limitations of the existing software from well-known EDA companies such as Siemens EDA and Cadence. According to these references, these software tools cannot perform the functions outlined in this paper.

 

Furthermore, Reference [9] (new reference number) is cited in lines 214 through 222 to illustrate the continuous downsizing of CMOS technology. Advances in lithography continue to shrink in size, exacerbating the interactions between neighboring patterns. However, it is worth noting that the methodology adopted in this paper is particularly applicable to APR flows in digital circuits, which is different from our proposed methodology for fully customized design flows.

 

Furthermore, I use References [10] and [11] (lines 238 to 245) to emphasize that the proposed flow is fully consistent with the most recent approach proposed by contemporary 2023 EDA companies. This reiterates that in today's EDA world, methods similar to the new approach proposed in this paper do not exist in the standard flow of using EDA tools. Our innovation is not available in the industry today. This is a new approach.

 

Reviewer 2 Report

Comments and Suggestions for Authors

 

The article titled: Mitigating the Effects of DFM on Design Iteration Cycles in 2

Advanced IC Design, includes a very few number of references as 9, but 2 of them can be called in a footnote as the ones given in

1. Williams N, Miller J. PDKs for Analog/Mixed-Signal (AMS) Design and Verification. Mentor Graphics [Internet]. [place un- 346

known]: Mentor Graphics; 2020 [cited 2023-06-04] 347

3. Wang J. Layout Component Placement and Routing [Internet]. [place unknown]: Virginia Tech; [date unknown] [cited 2023-06- 350

04]. Available from: https://www.mics.ece.vt.edu/content/dam/mics_ece_vt_edu/ICDesign/Tutorials/tsmc180/n05_Lay- 351

out%20Component%20Placement%20and%20Routing.pdf 352

 

Among the 9 references only one is from the current year, as the one given in:

 

6. Harahap RK, Prasetyo E, Heruseto B, Afandi H. Design Analog Layout Using Schematic-Driven EDA Tools. Journal of Electrical 357

Engineering. 2023; 10(2): 45-56.

 

Searching recent Works will help a reader to know the real state of the art and to apprecite the contribution of this manuscript.

 

Other mistakes must be cleaned as the ones in lines 180 and 299 in the sentences:

As shown in Error! Reference source not found.(B), a self-developed algorithm is 180

As shown in Error! Reference source not found., in the conventional design process, 299

 

The 13 figures are not useful to see a kind of guidelines, and they must be updated, shortened and include other that could help the reader to duplicate an experiment. In the same sense, three tables are included by neither show a comparison with related Works, nor show evidence of the results to be much better than the state of the art or to infer how the experiment can be duplicated and find these results in tables.

 

Figures 1 to 4 looks like they were cut and paste from a well known simulator, and they are not representative of the main goal of the manuscript. These figures must be merged or changed to appreciate the problem being solved, they are:

 

Figure 1. MOS transistor in a simple rectangular well. 109

Figure 2. Four MOS transistors generated from a single PDK library to test the DFM effect.

Figure 3. Diagram depicting the lengths SA and SB in relation to the LOD effect. Sourced from 125

[4],[5].

Figure 4. MOS layout obtained with DFM+Analog options enabled and using the PDK Library.

 

The paragraph in section 2 must be revised as it did not describes the contribution, only shows figure 5:

 

2. Methods of a New Design Process 173

The previous section reveals that the DFM parameters of IC layouts designed in full 174 compliance with PDK libraries may still exhibit variations due to the LDE; this is attribut- 175 able to differences in IC layout environments. Therefore, this study proposed a novel IC 176 design process for detecting and addressing DFM problems prior to routing. Figure 5. 177 Flowchart of the novel IC design method for the early detection of DFM issuespresents a 178 flowchart of the proposed process… The first sentence needs references as IC layouts are well documented. The novel IC design process must be justified including recent Works to appreciate the amin advantage, so that figure 5 must be detailed and justified.

 

The sentences in the following paragraph are well-known and documented in several simulation programs and must be justified including references and detailing the problem: IC design and layouts in advanced manufacturing processes must comply with rele- 196

vant procedures in PDK libraries. In the current era in which PDKs and interoperable PDK 197

tools are often used in IC design, various layout approaches have been proposed, such as 198

the use of schematic-driven electronic design automation tools [6] and schematic-driven 199

layout (SDL) flowcharts. Regarding commercially available design tools, the LakerOA 200

 

Figure 6. Flowchart of the proposed IC design algorithm… this algorithm requires more justification including related Works and detailing similar software companies. Authors should also mention what modern technologies mean in this manuscript.

 

If possible, authors can just print some text in the figures like: Figure 11. SPICE netlist with parasitic effects output by LPE for the design. … the text will be more readable.

 

In line 327: This study developed a novel design process 327 that integrates IC design, layout, physical verification, and LPE. … this must be documented to appreciate the real contribution on the problema formulation.

 

 

Comments on the Quality of English Language

moderate english revision is required

Author Response

Response to Reviewers’ Comments

        We thank the Associate Editor for letting us revise this paper for resubmission. We also thank reviewers for thoughtful comments to enhance the paper quality. We have carefully addressed all reviewers’ comments and revised the manuscript accordingly.

Review report #2

The article titled: Mitigating the Effects of DFM on Design Iteration Cycles in 2

Advanced IC Design, includes a very few number of references as 9, but 2 of them can be called in a footnote as the ones given in

1. Williams N, Miller J. PDKs for Analog/Mixed-Signal (AMS) Design and Verification. Mentor Graphics [Internet]. [place un- 346

known]: Mentor Graphics; 2020 [cited 2023-06-04] 347

3. Wang J. Layout Component Placement and Routing [Internet]. [place unknown]: Virginia Tech; [date unknown] [cited 2023-06- 350

04]. Available from: https://www.mics.ece.vt.edu/content/dam/mics_ece_vt_edu/ICDesign/Tutorials/tsmc180/n05_Lay- 351

out%20Component%20Placement%20and%20Routing.pdf 352

 Among the 9 references only one is from the current year, as the one given in:

6. Harahap RK, Prasetyo E, Heruseto B, Afandi H. Design Analog Layout Using Schematic-Driven EDA Tools. Journal of Electrical 357

Engineering. 2023; 10(2): 45-56.

 Searching recent Works will help a reader to know the real state of the art and to apprecite the contribution of this manuscript.

Response: Thank you sincerely for your insightful suggestions. Over the recent years, there has been a noticeable dearth of academic discourse regarding DFM issues within the realm of fully customized IC design processes. The predominant focus tends to be on discussions related to Cell-based flows. Consequently, in the introduction section of my work, I initially utilized experimental evidence to demonstrate how the current design processes and methodologies provided by foundries continue to yield DFM challenges in real-world applications of fully customized IC designs.

Moreover, in the concluding part of the introduction, I recently incorporated insights and perspectives from reference [6] (new reference ordering) in blue text(Lines 179 to 187), highlighting learning experiences and viewpoints. The approach outlined in that referenced article diverges from the methodology proposed in my work.

I added References [8][10] (new reference number), these 2023 Synopsys and Cadence, the two mainstream EDA companies on their official websites, the latest design flow is the same as the flow mentioned in the paper, and there is no EDA company that has developed the arguments presented in this paper (Lines 238 to 245). IC design flow in the discussion of DFM in Fully custom design literature is very little, so I by the EDA company's latest official website information to understand the development of today's design flow.

In lines 263 to 266, I cited [11] (new reference number) to illustrate the standard DRC/LVS flow in the same way as the conventional flow mentioned in Figure 5(A) of our paper, and the DFM mentioned in [11] (new reference number) is only an enhancement of the DRC tool rather than a change in the design flow.

In line 305, a new Reference [14] (new reference number) was added to emphasize the reference to Schematic-Driven Design Methodology.

And in lines 325 to 338, we cite reference [13] to the Manual of Calibre SVRF to illustrate how we can utilize the options parameter in the calibre syntax in our new flow to accomplish the desired settings of our program results.

While In lines 214 to 222 [9] is used to illustrate the problem of recent DFM, but it can only be solved in the digital logic of the CELL, and we are not limited to which circuits, and is even more helpful for analog circuits.

Other mistakes must be cleaned as the ones in lines 180 and 299 in the sentences:

As shown in Error! Reference source not found.(B), a self-developed algorithm is 180

As shown in Error! Reference source not found., in the conventional design process, 299

Response: The problem you suggested in the previous version of line 180. => I will add a paragraph to the section 2. Methods of a New Design Process that describes the traditional process and cites [8][10] to illustrate it. (line238-256)

The problem you suggested in the previous version of line 299. =>, this describes the experiments for the TEST CASE in this paper. Step0 involves only Presimulation in CDL without any DFM effects and results from RC Loading of Metal routing. Step1 involves DFM, where I extract DFM parameters for devices but exclude RC from Metal routing to obtain results. Step2 comprises DFM+Routing RC, using a complete IC Layout to extract DFM and RC (addressing DFM issues while accounting for the remaining impact of METAL parasitic RC). Therefore, there is no intention here to cite other references.

 

The 13 figures are not useful to see a kind of guidelines, and they must be updated, shortened and include other that could help the reader to duplicate an experiment. In the same sense, three tables are included by neither show a comparison with related Works, nor show evidence of the results to be much better than the state of the art or to infer how the experiment can be duplicated and find these results in tables.

Response: Thank you for the reminder. Indeed, Figure 13 is redundant. Figure 12 adequately illustrates the three-stage simulation results of the entire new design flow. Therefore, I have removed Figure 13.( I have deleted lines 418-420.)

I'll report back to you on Figure 12：

Step0: CDL involves only Presimulation without any DFM effects and RC loading due to Metal routing.

Step1-1 reveals the impact of Layout-Dependent Effects (LDE) generated by various mask layers like NW, OD, Poly, N-implant, P-implant, etc., on the circuit characteristics of the IC Layout floor-plan. At this stage, before routing begins, we can extract all Device DFM parasitic effects. However, the simulation results show that the Gain does not meet specifications.

Step1-2: Modifications to the floor-plan did not yield the expected simulation results.

Step1-3: Further modifications to the floor-plan achieve the desired circuit specifications.

Hence, we proceed to Step2 to begin metal routing and officially engage in the post-simulation process. Any issues encountered in this process are attributable to Metal parasitic RC effects rather than the impact of Device placement.

To assess the benefits of the new process compared to the traditional one, I've used Table 3 for comparison. Quantifying the time savings of this design process is challenging. However, from a process perspective, for circuits sensitive to mis-matching and DFM effects in high-frequency and low-voltage scenarios, the new process undoubtedly reduces the required iteration time compared to the old process. This is because we allow circuit designers to address issues generated by Device floor-planning before initiating metal routing.

Figures 1 to 4 looks like they were cut and paste from a well known simulator, and they are not representative of the main goal of the manuscript. These figures must be merged or changed to appreciate the problem being solved, they are:

 Figure 1. MOS transistor in a simple rectangular well. 109

Figure 2. Four MOS transistors generated from a single PDK library to test the DFM effect.

Figure 3. Diagram depicting the lengths SA and SB in relation to the LOD effect. Sourced from 125

[4],[5].

Figure 4. MOS layout obtained with DFM+Analog options enabled and using the PDK Library.

Response: This part expresses the experiments on the WPE/LOD effect of one or several MOS. Figures 1 and 3 are the schematic diagrams to illustrate the relevant parameters of Eqs. 1~9, while Figures 2 and 4 are the experiments of our actual IC layout.

The paragraph in section 2 must be revised as it did not describes the contribution, only shows figure 5:

Response: I have revised the blue part in 2. Methods of a New Design Process. I have added lines 198 through 277 to restate this section, where lines 238 through 256 illustrate the problems with Figure 5(A) Traditional Processes.

2. Methods of a New Design Process 173

The previous section reveals that the DFM parameters of IC layouts designed in full 174 compliance with PDK libraries may still exhibit variations due to the LDE; this is attribut- 175 able to differences in IC layout environments. Therefore, this study proposed a novel IC 176 design process for detecting and addressing DFM problems prior to routing. Figure 5. 177 Flowchart of the novel IC design method for the early detection of DFM issuespresents a 178 flowchart of the proposed process… The first sentence needs references as IC layouts are well documented. The novel IC design process must be justified including recent Works to appreciate the amin advantage, so that figure 5 must be detailed and justified.

Response: Thank you for reminding me of the importance of Figure 5 in the blue section of 2. Methods of a New Design Process.

I have deleted lines 233-236 from the new version and added lines 224-231 to supplement the old version of this sentence (DFM parameters of IC layouts designed in full compliance with PDK libraries may still exhibit variations due to the LDE)。 Because there is no research in this area in academic papers, the physical phenomena derived from this kind of regional layout structure on IC Layout are defined in the technical data of each foundry, and we can only utilize EDA tools to experiment this effect.

added=>(line224-231)In the Introduction, the experimental outcomes depicted in Figures 2 and 4 indicate that despite utilizing the PDK Cell provided by the foundry, differences persist in the DFM effects (such as WPE and LOD) across various layout styles and structures. These findings reveal that the DFM parameters within integrated circuit layouts designed in the PDK library may still exhibit variations attributed to Layout-Dependent Effects (LDE) stemming from diverse IC layout environments. Consequently, this study introduces a novel integrated circuit design process aimed at proactively detecting and resolving DFM issues prior to the routing phase.

The sentences in the following paragraph are well-known and documented in several simulation programs and must be justified including references and detailing the problem: IC design and layouts in advanced manufacturing processes must comply with rele- 196

vant procedures in PDK libraries. In the current era in which PDKs and interoperable PDK 197

tools are often used in IC design, various layout approaches have been proposed, such as 198

the use of schematic-driven electronic design automation tools [6] and schematic-driven 199

layout (SDL) flowcharts. Regarding commercially available design tools, the LakerOA 200

Response: We have added to this section the blue part of the description such as Algorithm and Automation. (Line 313-338)

Figure 6. Flowchart of the proposed IC design algorithm… this algorithm requires more justification including related Works and detailing similar software companies. Authors should also mention what modern technologies mean in this manuscript.

Response: We have added a blue section (lines 313-338) to the "Algorithm and Automation" chapter to illustrate the methodology of the current technology and to explain how we can utilize the features of the existing EDA Tools to create our new process.

If possible, authors can just print some text in the figures like: Figure 11. SPICE netlist with parasitic effects output by LPE for the design. … the text will be more readable.

Response: I modified Figure 11 to illustrate the parameters extracted by the RC-Extraction tools.

In line 327: This study developed a novel design process 327 that integrates IC design, layout, physical verification, and LPE. … this must be documented to appreciate the real contribution on the problema formulation.

Response: Thanks for the reminder that the blue part I added in the Algorithm and Automation chapter echoes this paragraph. (Line 313-338)

 

Reviewer 3 Report

Comments and Suggestions for Authors

The paper presents an algorithm based design process to mitigate layout dependent effects on ID design which can efficiently improve the IC design. The methodology and the results are sound and well presented, and the results clearly discussed and the content itself is appropriate for submission to the Industrial Electronics Section of the Electronics Journal.  However, the paper in its current state cannot be published in this journal until the following major issues are addressed by the authors:

The Introduction part is too perfunctory and insufficient. It lacks the references that deals with the development of the field/topic by other authors, as well as similar works by other researchers so as to put the paper in the proper context of the state of the research. The Introduction section only presents one paragraph of background.  It should be rewritten to have a substantial amount of background material as well as comparisons by papers that deal with the similar work and how the current state of the research has been reached.

The entire paper is only based on nine references and three of them are by the authors.  This is not a good representative of an informative paper. The authors need to add more references to cite most of the claims they present in the paper.

After the authors consider addressing these issues the paper can be published in Electronics Journal under the Industrial Electronics Section.

Comments on the Quality of English Language

The paper only needs some spelling check. The language usage is good and the exposition is clear.

Author Response

Response to Reviewers’ Comments

        We thank the Associate Editor for letting us revise this paper for resubmission. We also thank reviewers for thoughtful comments to enhance the paper quality. We have carefully addressed all reviewers’ comments and revised the manuscript accordingly.

Review report #3

The paper presents an algorithm based design process to mitigate layout dependent effects on ID design which can efficiently improve the IC design. The methodology and the results are sound and well presented, and the results clearly discussed and the content itself is appropriate for submission to the Industrial Electronics Section of the Electronics Journal.  However, the paper in its current state cannot be published in this journal until the following major issues are addressed by the authors:

The Introduction part is too perfunctory and insufficient. It lacks the references that deals with the development of the field/topic by other authors, as well as similar works by other researchers so as to put the paper in the proper context of the state of the research. The Introduction section only presents one paragraph of background.  It should be rewritten to have a substantial amount of background material as well as comparisons by papers that deal with the similar work and how the current state of the research has been reached.

The entire paper is only based on nine references and three of them are by the authors.  This is not a good representative of an informative paper. The authors need to add more references to cite most of the claims they present in the paper.

After the authors consider addressing these issues the paper can be published in Electronics Journal under the Industrial Electronics Section.

 

Comments on the Quality of English Language

The paper only needs some spelling check. The language usage is good and the exposition is clear.

Response: I appreciate your insights. In recent years, there has been a scarcity of academic discussions on DFM issues within the entire IC design process, with most emphasis placed on Cell-based flows. Therefore, in the introduction section, I initially used experiments to demonstrate that the current design process and methods provided by foundries still encounter DFM issues in real-world IC design practices. Towards the end of the introduction, I added insights and perspectives from reference [6] (new reference number) in blue text (Lines 179 to 187), highlighting the differences between the approaches taken in that article and the method proposed in my paper.

 

Moreover, I have extensively reworked the section titled "2. Methods of a New Design Process". (Lines 238 to 245) The initial parts delve into a detailed description of the issues in the conventional process, supplemented by references [8][10] (new reference ordering), elucidating that the latest design processes on the official websites of Synopsys and Cadence in 2023 align with the traditional processes mentioned in this paper. Additionally, there are no tools developed by EDA companies directly related to the new arguments proposed in this paper. Literature discussing DFM within fully customized IC design processes is rare. Therefore, I resorted to utilizing the latest information from EDA company official websites to comprehend the occurrences in today's design processes.

 

In lines 263 to 266, I cited [11] (new reference ordering) to illustrate the standard DRC/LVS flow in the same way as the conventional flow mentioned in Figure 5(A) of our paper, and the DFM mentioned in [11] (new reference ordering)is only an enhancement of the DRC tool rather than a change in the design flow.

In line 305, a new reference [12] (new reference number) was added to emphasize the reference to Schematic-Driven Design Methodology.

And in lines 325 to 338, we cite reference [13] (new reference ordering)to the Manual of Calibre SVRF to illustrate how we can utilize the options parameter in the calibre syntax in our new flow to accomplish the desired settings of our program results.

While In lines 214 to 222 [9] (new reference number) was used to illustrate the problem of recent DFM, but it can only be solved in the digital logic of the CELL, and we are not limited to which circuits, and is even more helpful for analog circuits.

 

Reviewer 4 Report

Comments and Suggestions for Authors

The work proposes an improvement on IC design process by taking into account component placement in the pre-final layout parasitic extraction in order to reduce the simulation/change/spec. evaluation iteration count.

The comments and suggestions are listed below:
- Table 1 - units must be included in L, W, SA... row. Identical values for L, W, SA and SB could be merged in a single column value to make it easier to read
- Figure 4 has two pictures, but they are not named. I'm suggesting that the right one is the zoomed version of the left one, but in the left one - the transistors are placed in a well with a guardring. So, more info describing what we see should be included in the text and in the Figure info
- Comments for Table 1 should be applied to Table 2 as well.
- Line 178 - "issuespresents" space required;
- "Error! Reference source not found." is present in the text;
- Is the created tool applied to Cadence Virtuoso and written using SKILL language?
- If I understood the whole process of how your method and software works, the designer inputs the initial schematic netlist and receives an output SPICE netlist which is shown in Figure 11. Who then interprets the new SA, SB and other parameters, the designer while doing layout, or the netlist is used during simulation (tran, SP, AC, etc.)? If it is the second variant (the new netlist is used for simulation), how does the simulator take into account the new parameters, which are not standard in device SPICE model? You could elaborate that in the text a bit more.

The reason for the question is that I'm familiar with Cadence Virtuoso SKILL language, where you can't address how the simulator compiles and runs calculations based on the internal parameters of a device SPICE netlist.

- Line 280 "Consequently, the device placement and metal routing processes had to be repeated, and the problems were resolved after five iteration cycles, which took 1340 minutes." - what had to be changed to meet the requirements, was the problem in the placement or routing and interconnect?

- Line 298 figure - I'd suggest adding pictures of how the layout changed for all iteration (maybe in the appendix). Because currently, the placement step number is hard to interpret - one step can be "moving a transistor a bit to the rigth" and at the same time, one step can count as "the current mirror moved from the right side to the left side". In both cases, the end-result might differ. There is a line "unit:mims" in the figure - was it meant to be minutes? I'd suggest dropping abbreviations in this case, as the table itself is not standar, as you have to analyze it to understand what is happening.

- The conclusions might be improved by adding the time, iteration differences with the standard and proposed flow, what software you've tested. More specific details which are the result of this work.

All in all, an interesting work with good formatting, which I'd suggest accepting after major changes, which include the listed above suggestions.

Author Response

Response to Reviewers’ Comments

        We thank the Associate Editor for letting us revise this paper for resubmission. We also thank reviewers for thoughtful comments to enhance the paper quality. We have carefully addressed all reviewers’ comments and revised the manuscript accordingly.

 

Review report #4

The work proposes an improvement on IC design process by taking into account component placement in the pre-final layout parasitic extraction in order to reduce the simulation/change/spec. evaluation iteration count.

The comments and suggestions are listed below:
- Table 1 - units must be included in L, W, SA... row. Identical values for L, W, SA and SB could be merged in a single column value to make it easier to read

Response: I have modified the table according to your suggestion and added units to W/L, but SA/SB/SCA/SCB/SCC has no units, it is just a value for the program to calculate.

- Figure 4 has two pictures, but they are not named. I'm suggesting that the right one is the zoomed version of the left one, but in the left one - the transistors are placed in a well with a guardring. So, more info describing what we see should be included in the text and in the Figure info

Response: Thanks for the reminder. I've changed the markings on the diagram.

- Comments for Table 1 should be applied to Table 2 as well.

Response: Thanks for the reminder, I've already combined the parts that can be combined and added the W/L units.

- Line 178 - "issuespresents" space required;
- "Error! Reference source not found." is present in the text;

Response: I have modified the blue text in this chapter as shown in 2. Methods of a New Design Process. (line 198-278)

- Is the created tool applied to Cadence Virtuoso and written using SKILL language?

Response: I'm using Synopsys Laker OA with TCL, but of course Virtuoso also has this feature and requires Skill.
- If I understood the whole process of how your method and software works, the designer inputs the initial schematic netlist and receives an output SPICE netlist which is shown in Figure 11. Who then interprets the new SA, SB and other parameters, the designer while doing layout, or the netlist is used during simulation (tran, SP, AC, etc.)? If it is the second variant (the new netlist is used for simulation), how does the simulator take into account the new parameters, which are not standard in device SPICE model? You could elaborate that in the text a bit more.

The reason for the question is that I'm familiar with Cadence Virtuoso SKILL language, where you can't address how the simulator compiles and runs calculations based on the internal parameters of a device SPICE netlist.

Response: SA/SB These parameters are not for human reading, it is by the Simulation tool to match the values in the SPICE Model and the impact will be displayed in the simulation results, this process is just to extract these values in advance, so that the designer can run simulation in advance to know the impact of these parameters on the Vth/Id of the component first!

- Line 280 "Consequently, the device placement and metal routing processes had to be repeated, and the problems were resolved after five iteration cycles, which took 1340 minutes." - what had to be changed to meet the requirements, was the problem in the placement or routing and interconnect?
Response: The fifth time is to redesign all the device of the floor-plan and therefore the entire metal routing has to be redone.

- Line 298 figure - I'd suggest adding pictures of how the layout changed for all iteration (maybe in the appendix). Because currently, the placement step number is hard to interpret - one step can be "moving a transistor a bit to the rigth" and at the same time, one step can count as "the current mirror moved from the right side to the left side". In both cases, the end-result might differ. There is a line "unit:mims" in the figure - was it meant to be minutes? I'd suggest dropping abbreviations in this case, as the table itself is not standar, as you have to analyze it to understand what is happening.
Response: I modified the abbreviation in the table, IC Layout's floor-plan variation diagram, which I show at the bottom of Figure 12

- The conclusions might be improved by adding the time, iteration differences with the standard and proposed flow, what software you've tested. More specific details which are the result of this work.
Response:Since this concept is available in Synopsys and Cadence's tools, and Calibre also has some functionality that can be utilized, I used the program to link these functions together to make Calibre think the wires were already connected, and then perform RC-extraction, so this new process does not require binding to a specific EDA tool.

All in all, an interesting work with good formatting, which I'd suggest accepting after major changes, which include the listed above suggestions.

Response: Thank you very much for your review and advice!

 

Round 2

Reviewer 2 Report

Comments and Suggestions for Authors

the updated version of this manuscript can be accepted as it is

Comments on the Quality of English Language

very minor revision

Reviewer 4 Report

Comments and Suggestions for Authors

Thank you for addressing the suggestions.