An Improved Carrier-Based PWM Strategy with Reduced Common-Mode Voltage for a Three-Level NPC Inverter

Abstract

Double modulation wave carrier-based pulse width modulation (CBPWM) is a solution for eliminating the deviations of the neutral-point voltage (NPV) in three-level neutral-point clamped inverters. In this paper, a new hybrid CBPWM strategy is proposed that not only eliminates the neutral-point voltage oscillations but also reduces the common-mode voltage (CMV) by half. Furthermore, the harmonic content is also reduced compared with the available reduced CMV modulation by adjusting the modulation waves based on the location of the reference vector in the space vector diagram. An active neutral-point voltage controller is also realized in order to maintain the performance of the modulation strategy under the NPV perturbations. The performance of the proposed algorithm is compared to the available CBPWM-based techniques in the literature. The effectiveness of the proposed method is also verified by experimental results.

1. Introduction

A three-level neutral-point clamped inverter is among the most common multilevel inverters used in medium voltage industrial applications. Compared with the two-level inverter, the main benefits are a lower harmonic content and reduced voltage stress across semiconductor devices [1]. Various modulation techniques have been proposed in the literature that are generally categorized as either carrier-based pulse width modulation (CBPWM) or space vector PWM (SVPWM).

Despite the simple implementation, conventional CBPWM leads to low frequency fluctuation of the neutral-point voltage (NPV). NPV deviations lead to the distortion of output voltage and current and induce larger voltage stress across switches, which may cause permanent damage. In order to compensate for the NPV fluctuations, bigger DC-link capacitors can be used, however, this is an unfavorable solution, especially in drive applications due to the negative effect on power density. As another solution, two separate DC sources, or split batteries, can be used to stabilize the voltage of the neutral point (NP) [2]. To minimize the NP fluctuations, feedback control can be implemented where the NPV is detected and controlled. All these solutions demand additional hardware costs. As a more cost-effective solution, improved CBPWM or SVPWM strategies are proposed in the literature.

Busquets et al. adopted a nearest three virtual space vector PWM (VSVPWM) approach to balance the NP voltage [3]. The idea is to maintain a zero average neutral-point current in a switching period. This is achieved by combining small vectors and medium vectors to create virtual medium vectors. Although zero average neutral-point current can be achieved in all operating points, harmonic content and the effective switching frequency are increased. Moreover, in practical applications, balanced neutral-point voltage cannot be maintained due to non-ideal operating conditions such as the leakage current flowing into the ground, unequal DC-link capacitors, and the differences in the switching behavior of the devices [4]. Therefore, an active NPV controller is required. In [4], the authors achieve a closed loop controller, and in [5], an optimization is performed to lower the harmonic content of the output voltage. The effect of unbalanced capacitors can be taken into account by repartitioning the virtual vector diagram [6,7,8].

A CBPWM based on the concept of virtual vectors has also been proposed, which is simple and easy to implement [9,10]. An active neutral-point controller for this strategy is developed in [11]. In all of the previous research studies, the main objective was to maintain a low NPV oscillation through zero average neutral-point current while the generated common-mode voltage is disregarded.

High common-mode voltage (CMV) induces more leakage current and increases electromagnetic interference (EMI) emissions. In motor drive applications, CMV results in shaft voltage and bearing current that may damage the motor insulation [12,13]. Hence, CMV suppression is a critical matter that needs to be addressed.

In the space vector diagram (SVD), each switching state will generate a specific CMV. By properly selecting the space vectors, CMV can be either eliminated or reduced significantly [13,14]. Keeping that in mind, an efficient solution is to use the vectors that would generate lower CMV to build the virtual vectors [15,16]. Although the CMV virtual space vector PWM (RCMV_VSVPWM) strategy in [15] effectively reduces the CMV, the ability to self-balance is lost, and an active NPV controller is required at all times. In another RCMV_VSVPWM approach, self-balance capability is maintained at the expense of increased harmonic content [17]. An improved version of VSVPWM is introduced in [18] to reduce the NPV oscillation and CMV simultaneously. However, an active NPV controller is not realized, the CMV suppression is not achievable for all operating points, and the algorithm is not easy to implement.

A double modulation wave CBPWM with reduced CMV is introduced in [19], which is easy to implement. The authors have reduced the CMV by half by inverting the switching sequence in one of the phases. The major issues of this strategy are high harmonic content in two phases and that the incompetent NPV controller fails to maintain CMV suppression at all operating points. Furthermore, the effectiveness of this modulation deteriorates in lower power factors.

In this paper, some improvements have been made to the technique in [19] to propose a hybrid CBPWM technique, which is introduced alongside an active NPV controller that ensures effective CMV suppression and the elimination of NPV fluctuations at all operating points. Furthermore, this modulation is easy to implement and the harmonic content of the output current is reduced compared to other available RCMV CBPWM modulations.

The rest of the paper is organized as follows. The operation of the three-level active neutral-point inverter is briefly explained in Section 2, along with the analysis of CMV generation and neutral-point current under conventional modulation schemes. Section 3 presents the principle of the proposed hybrid CBPWM. An active NPV controller is developed in Section 4. Simulation and experimental results for different operating points are presented in Section 5. Section 6 concludes the paper.

2. Neutral-Point Current and CMV of the Three-Level NPC

A three-level active neutral-point clamped (ANPC) inverter is shown in Figure 1a. In comparison with the NPC inverter, the diodes are replaced with two fully controlled switches, $S_5$ and $S_6$. This feature can be used to evenly distribute the power loss among the switching devices. Note that the space vector diagram remains the same as depicted in Figure 1b. The corresponding switching states of phase A are listed in Table 1. The positive, negative, and zero switching states are represented by ‘P’, ‘N’, and ‘O’, respectively.

Figure 1. (a) Topology of the ANPC and its (b) space vector diagram.

Table 1. Switching states of a three-level ANPC.

Switching State		Device Switching Status						Output Phase Voltage
		${\mathit{S}}_{\mathbf{1}}$	${\mathit{S}}_{\mathbf{2}}$	${\mathit{S}}_{\mathbf{3}}$	${\mathit{S}}_{\mathbf{4}}$	${\mathit{S}}_{\mathbf{5}}$	${\mathit{S}}_{\mathbf{6}}$
[P]		1	1	0	0	0	1	$V_{dc}/2$
[O]	OU1 1	0	1	0	0	1	0	0
	OU2 1	0	1	0	1	1	0
	OL1 2	1	0	1	0	0	1
	OL2 2	0	0	1	0	0	1
[N]		0	0	1	1	1	0	$-V_{dc}/2$

¹ OU1 and OU2 indicate the zero switching state when S₅ is on. ² OL1 and OL2 indicate the zero switching state when S₆ is on.

2.1. Neutral-Point Current

Two DC-link capacitors, $C_1$ and $C_2$, ideally have equal voltages ($V_{dc}/2$). The neutral-point voltage balance is essential for the decent performance of the ANPC. Each switching state affects the neutral-point voltage depending on whether a phase current flows through the NP or not. Large vectors contain no ‘O’ state, i.e., do not connect any phases to the NP. Therefore, they have no effect on the NPV. Likewise, zero vectors have no effect on the NPV. On the other hand, medium and small vectors each have a specific effect on the neutral-point current. Table 2 shows the neutral-point current for the medium and small vectors. It is assumed that the three-phase load is balanced:

$$i_a+i_b+i_c=0$$

(1)

Table 2. The effect of medium and small vectors on the NP.

Mediums Vectors		Small Vectors
$V_7$	$i_b$	$V_{1P}$	$-i_a$	$V_{4P}$	$i_a$
$V_{10}$		$V_{1N}$	$i_a$	$V_{4N}$	$-i_a$
$V_8$	$i_a$	$V_{2P}$	$i_c$	$V_{5P}$	$-i_c$
$V_{11}$		$V_{2N}$	$-i_c$	$V_{5N}$	$i_c$
$V_9$	$i_c$	$V_{3P}$	$-i_b$	$V_{6P}$	$i_b$
$V_{12}$		$V_{3N}$	$i_b$	$V_{6N}$	$-i_b$

As an example, $V_7=$ PON and $V_{10}=$ NOP, both connect only phase B to the neutral point, therefore $i_b$ flows through the neutral. Similarly, $V_{1P}=$ POO connects phase B and phase C to the NP. Hence, the current flowing through the neutral would be $i_b+i_c=-i_a$.

In order to avoid the NPV fluctuations, one solution is to keep the average of the neutral-point current in one switching period at zero. It can be mathematically described as:

$$i_{NP}=i_a{d}_{a,0}+i_b{d}_{b,0}+i_c{d}_{c,0}=0,$$

(2)

where $d_{x,0}$ denotes the duty ratio of the zero state for phase x, and likewise, the duty ratio of the other states is represented by $d_{x,1}$ and $d_{x,-1}$. By comparing (1) and (2), one can conclude that as long as the zero state ratio of all phases are equal, the neutral-point current is kept at zero, such that:

$$d_{a,0}=d_{b,0}=d_{c,0}$$

(3)

2.2. Common-Mode Voltage

As discussed in Section 1, CMV induces CM current in the parasitic capacitors resulting in EMI emissions. Moreover, higher CMV leads to higher leakage current that may damage the bearings and the motor insulation. Therefore, the CMV needs to be analyzed and considered in the design stage.

Common-mode voltage in a three-level inverter is defined as:

$$V_{CM}=\frac{V_{AN}+V_{BN}+V_{CN}}{3}$$

(4)

Table 3 summarizes the generated CMV by different space vectors.

Table 3. Generated CMV by different space vectors.

Vectors		CMV
zero vector	$V_0$(OOO)	0
zero vector	$V_0$((PPP), $V_0$(NNN)	$\pm V_{dc}/2$
small vectors1	$V_{1P}$(POO), $V_{2N}$(OON), $V_{3P}$(OPO)	$\pm V_{dc}/6$
	$V_{4N}$(NOO), $V_{5P}$(OOP), $V_{6N}$(ONO)
small vectors2	$V_{1N}$(ONN), $V_{2P}$(PPO), $V_{3N}$(NON)	$\pm V_{dc}/3$
	$V_{4P}$(OPP), $V_{5N}$(NNO), $V_{6P}$(POP)
medium vectors	$V_7$(PON), $V_8$(OPN), $V_9$(NPO)	0
	$V_{10}$(NOP), $V_{11}$(ONP), $V_{12}$(PNO)
large vectors	$V_{13}$(PNN), $V_{14}$(PPN), $V_{15}$(NPN)	$\pm V_{dc}/6$
	$V_{16}$(NPP), $V_{17}$(NNP), $V_{18}$(PNP)

2.3. Virtual Vectors

Virtual vectors are a linear combination of medium and small vectors that balance out their effect on the neutral-point current. In Figure 2a, the conventional virtual vectors in sector I are depicted [3]. In the new space vector diagram, large and zero vectors are the same as in the conventional SVD, while $V_{VS1}$, $V_{VS2}$, and $V_{VM1}$ are the new small (two) and medium virtual vectors. The small virtual vector $V_{VS1}$ is obtained by an equal combination of $V_{1P}$(POO) and $V_{1N}$(ONN). When $V_{VS1}$ is applied for a specific period of time, $t_1$, each of the constitutive vectors, POO and ONN, are active for $t_1/2$. The average neutral-point current can be calculated using Table 2:

$$i_{NP}=\frac{t_1/2·i_a+t_1/2·-i_a}{t_1}=0.$$

(5)

Figure 2. (a) Virtual space vector diagram in sector I, (b) switching sequence of $V_{ref}$, resultant neutral-point current, NPV variations, and the generated $V_{CM}$. (Green: phase a; Red: phase b; Blue: phase c).

The average neutral point generated by the other small virtual vector, $V_{VS2}$, is similarly zero. $V_{VM1}$ is an equal share of the medium space vector, $V_7$(PON), and the small vectors $V_{1N}$(ONN) and $V_{2P}$(PPO). Notice that the generated neutral-point current of the constitutive vectors is $i_b$, $i_a$, and $i_c$, respectively. Therefore, the resultant neutral current will be $(i_a+i_b+i_c)/3=0$.

As an example, the switching sequence, the neutral-point current, and the neutral-point voltage deviations are graphically shown in Figure 2b for the reference voltage shown in Figure 2a. In this case, the nearest three virtual vectors are $V_{14}$, $V_{VM1}$, and $V_{VS2}$. Hence, five different space vectors are applied: $V_{1N}$, $V_{2P}$, $V_{2N}$, $V_7$, and $V_{14}$. The switching sequences are arranged to minimize the switching power loss. Please note that it is assumed $i_c<0$, $i_b>i_a>0$, and $|i_c|>|i_b|$.

The generated CMV of the sample switching sequence of the VSVPWM is depicted in Figure 2b. We can reduce the CMV to $V_{dc}/3$ if only ‘OOO’ is used as a zero vector. In the same manner, CMV can be reduced to $V_{dc}/6$ when the type 2 small vectors are eliminated. The CMV can be theoretically kept at zero by only using the medium vectors and zero state (’OOO’). However, this strategy is not applied in practical applications since we lose the major benefits of a three-level inverter.

In the new virtual space vector diagram, all the vectors have an average neutral-point current of zero. Although various versions of an SVD have been proposed in the literature, all of them are based on the concept of a zero average neutral-point current.

3. Derivation of the Proposed Hybrid CBPWM

Compared to SVPWM, carrier-based PWM is simpler to implement, especially for multilevel inverters where the number of available voltage vectors in the SVD increases considerably. A conventional CBPWM where two carrier waves are compared with the three-phase modulation waves is shown in Figure 3. Modulation waves can be written as:

$$\begin{array}{cc}\hfill u_a& =m·cos\left(2\pi f_{o}t\right)\hfill \\ \hfill u_b& =m·cos(2\pi f_{o}t-2\pi /3)\hfill \\ \hfill u_c& =m·cos(2\pi f_{o}t+2\pi /3),\hfill \end{array}$$

(6)

where m and $f_o$ are the modulation index and the output fundamental frequency, respectively. The main disadvantage of this modulation is that there are large NPV deviations.

Figure 3. Conventional CBPWM with two carriers.

A double modulation CBPWM which includes the elimination of NPV fluctuations was first developed in [20]. This strategy is practically equivalent to the conventional VSVPWM studied in Section 2. Two modulation waves, known as positive and negative modulations, are compared with the carrier for each phase. The positive modulation wave $u_{xp}$ ($x=a,b,c$) is used to control $S_{x1}$ and $S_{x3}$ and toggle the switching state of the phase leg between the ‘O’ and ‘P’ states. At the same time, the negative modulation wave $u_{xn}$ is used to control $S_{x2}$ and $S_{x4}$ and toggle the switching state of the corresponding phase leg between the ‘N’ and ‘O’ states. The final switching state of the phase leg is obtained by combining the corresponding positive and negative switching states, as depicted in Figure 4.

Figure 4. Construction of the phase leg state using positive and negative modulation waves. (Green: negative modulation wave switching; Blue: positive modulation wave switching).

3.1. Principle of the Operation

The positive and negative modulation waves are obtained from the three phase modulation waves in (6). Based on [19], in order to derive the positive and negative modulation waves, the main reference voltages are rearranged as follows:

$$\begin{array}{c}\hfill u_{max}=max(u_a,u_b,u_c),\\ \hfill u_{min}=min(u_a,u_b,u_c),\\ \hfill u_{mid}=mid(u_a,u_b,u_c);\end{array}$$

(7)

where $u_{max}$ is the maximum of the three modulation waves, $u_{min}$ is the minimum, and $u_{mid}$ is the median modulation wave. Based on the volts-seconds product, the following can be written for the line voltages:

$$\begin{array}{c}\hfill \sum _{k=-1,0,1}(k{d}_{max,k}-k{d}_{mid,k})=u_{max}-u_{mid},\\ \hfill \sum _{k=-1,0,1}(k{d}_{mid,k}-k{d}_{min,k})=u_{mid}-u_{min},\\ \hfill \sum _{k=-1,0,1}(k{d}_{max,k}-k{d}_{min,k})=u_{max}-u_{min};\end{array}$$

(8)

where $k=-1,0,1$ are the switching states corresponding to ‘N’, ‘O’, ‘P’, respectively, and $d_{x,k}$ denotes the duty ratio of the state k and phase x. In other forms:

$$\left\{\begin{array}{c}\hfill (-d_{max,-1}+d_{max,1})-(-d_{mid,-1}+d_{mid,1})=u_{max}-u_{mid}\\ \hfill (-d_{mid,-1}+d_{mid,1})-(-d_{min,-1}+d_{min,1})=u_{mid}-u_{min}\\ \hfill (-d_{max,-1}+d_{max,1})-(-d_{min,-1}+d_{min,1})=u_{max}-u_{min}\end{array}\right.$$

(9)

Since the sum of the duty ratios of the three states for each phase is equal to one, we also have the following:

$$d_{l,-1}+d_{l,0}+d_{l,1}=1,l=min,mid,max$$

(10)

The third equation in (9) can be achieved by adding up the first two. Therefore, in total there are five equations with nine unknowns in (9) and (10). Hence, more information is needed to solve the equations. First, we know that in order to achieve a zero average neutral-point current, the zero state ratio of all the phases should be the same, thus two more equations can be written as: ($d_{max,0}$ = $d_{mid,0}$ = $d_{min,0}$).

Two more restrictive conditions are required to uniquely solve the equations. Considering the space diagram (see Figure 1), in any Sector, the maximum voltage ($u_{max}$) switches between states ‘P’ and ‘O’. Similarly, the minimum voltage ($u_{min}$) only switches between ‘O’ and ‘N’, while the median voltage ($u_{mid}$) is capable of all three states in every switching period. This can be seen for Sector I in Figure 2. In other words:

$$d_{max,-1}=d_{min,1}=0.$$

(11)

This limitation helps us to lower the switching power loss by reducing the total number of switching transients. It is worth mentioning that different restrictions can be applied to achieve other design objectives. The resultant duty ratios are obtained as follows:

$$\begin{array}{cc}\hfill d_{max,1}& =\frac{u_{max}-u_{min}}{2},d_{max,-1}=0,d_{max,0}=1-\frac{u_{max}-u_{min}}{2}\hfill \\ \hfill d_{mid,1}& =\frac{u_{mid}-u_{min}}{2},d_{mid,-1}=\frac{u_{max}-u_{mid}}{2},d_{mid,0}=1-\frac{u_{max}-u_{min}}{2}\hfill \\ \hfill d_{min,1}& =0,d_{min,-1}=\frac{u_{max}-u_{min}}{2},d_{min,0}=1-\frac{u_{max}-u_{min}}{2}\hfill \end{array}$$

(12)

By comparing (12) and Figure 4, the positive and negative modulation waves can be obtained:

$$\begin{array}{cc}\hfill u_{max,p}& =\frac{u_{max}-u_{min}}{2},u_{max,n}=1\hfill \\ \hfill u_{mid,p}& =\frac{u_{mid}-u_{min}}{2},u_{mid,n}=1-\frac{u_{max}-u_{mid}}{2}\hfill \\ \hfill u_{min,p}& =0,u_{min,n}=1-\frac{u_{max}-u_{min}}{2}\hfill \end{array}$$

(13)

Thus, in general, the modulation waves of phase x can be expressed as:

$$\begin{array}{cc}\hfill u_{x,p}& =\frac{u_x-u_{min}}{2}\hfill \\ \hfill u_{x,n}& =1-\frac{u_{max}-u_x}{2}\hfill \end{array}$$

(14)

The positive and negative modulation waves for phase A, when $m=0.8$, is shown in Figure 5.

Figure 5. Positive and negative modulation waves of phase A, $m=0.8$.

3.2. CMV Reduction

The generated common voltage of the double modulation wave PWM is similar to the conventional VSVPWM shown in Figure 2, as long as the switching sequences are similar. The CMV can be reduced by rearranging the switching sequences. However, the calculated duty ratios in (13) must be satisfied in order to eliminate the NPV deviations.

In Figure 4, each switching state follows the {high, low, high} pattern. The resultant switching state would be ‘PONOP’ for $u_{mid}$, ‘POP’ for $u_{max}$, and ‘ONO’ for the $u_{min}$. Another switching pattern is also possible when a carrier with opposite phase is implemented. As shown in Figure 6, with the {low, high, low} pattern, the resultant switching sequence, $S_x^{{}^{\prime }}$, is reversed in comparison with the previous case, $S_x$, while the duty ratio of each state remains the same.

Figure 6. Reversed switching patterns using two carriers with opposite phases.

In the case where only one of the carriers is used, the generated CMV can have an amplitude of up to $\pm V_{dc}/3$. In order to eliminate the vectors with higher CMVs and limit their amplitudes to $\pm V_{dc}/6$, both carriers should be used. With three phases and two carriers, six different combinations can be expected: two of the phases are compared to carrier wave 1 and the remaining phase is compared with carrier wave 2 (three combinations), or only one phase is compared with carrier wave 1 and the other two phases are compared with carrier wave 2 (three combinations). All six combinations are depicted in Figure 7 along with the generated $V_{CM}$ in each case. Notice that all six cases have effectively reduced the CMV to $\pm V_{dc}/6$ as a result of using both carrier waves.

Figure 7. Different combinations of switching sequences to reduce the CMV when the switching pattern is different for only (a) $u_{mid}$, (b) $u_{max}$, and (c) $u_{min}$, respectively.

Since each of the six possible combinations can ideally eliminate the NPV fluctuations and reduce the CMV, other aspects should be considered to compose the most efficient modulation scheme. In Figure 7, it is notable that the CMV has two levels when $u_{mid}$ is reversed. On the other hand, the CMV changes between three levels when $u_{min}$ or $u_{max}$ are reversed. Therefore, the average CMV in one switching cycle is higher when $u_{mid}$ is reversed. Higher average CMV results in higher leakage current leads to additional NPV deviations. In terms of the switching loss point, the sum of the switching transitions in one switching period is equivalent in all cases. Another factor is the harmonic content of the output voltage, which is studied next. It is worth mentioning that all three phases (a,b,c) should be reversed equally in a fundamental cycle in order to have balanced line-to-line voltages.

3.3. Harmonic Content

One of the most intuitive analytical approaches to evaluate the harmonic content is the harmonic flux trajectory (HFT), which uses the space vectors [21]. The harmonic flux in a switching period with a modulation index m is calculated as follows [22]:

$$\lambda (m,\theta )={\int }_0^{T_s}(V_k-V_{ref})dt$$

(15)

where $V_{ref}$ is the reference voltage vector with an angle of $\theta$, and $V_k$ are the space vectors that are used to build the reference voltage. The RMS value of the flux in each switching cycle is a measure of the harmonic distortion and can be calculated as follows:

$${\lambda }_{rms}^2(m,\theta )=\frac{1}{T_s}{\int }_0^{T_s}(\Re {(V_k-V_{ref})}^2+\Im {(V_k-V_{ref})}^2)dt$$

(16)

The HFT of the conventional CBPWM is shown in Figure 8a in Sector I for different modulation indices. In Figure 8b, the HFT of the RCMV-CBPWM is depicted with only reversed switching of $u_{min}$. Contrary to the conventional CBPWM, it can be seen that the HFT of the second case does not follow the same pattern in all Sectors. Therefore, the RMS value of the HFT in a fundamental cycle, as calculated in (17), is used as a more intuitive parameter.

$${\lambda }_{rms}^2\left(m\right)=\frac{1}{2\pi }{\int }_0^{2\pi }{\lambda }_{rms}^2(m,\theta )d\theta$$

(17)

Figure 8. Harmonic flux trajectories of (a) conventional CBPWM in Sector I, (b) double modulation RCMV-CBPWM when $u_{min}$ is reversed in all Sectors.

Four different reversed switching combinations are compared for different modulation indices in Figure 9: in one case, one phase is reversed at all times, and in the three other cases only one of the reference voltages (i.e., $u_{mid}$, $u_{min}$, or $u_{max}$) is reversed at all times, which means all three phases are reversed equally in a fundamental cycle. It can be seen that the lowest harmonic content is achieved when either $u_{min}$ or $u_{max}$ is reversed.

Figure 9. RMS value of the HFT in a fundamental cycle for four different reversed switching combinations.

3.4. Neutral Point Voltage Deviation

Thus far we have learned that the best results are achieved when either $u_{min}$ or $u_{max}$ is reversed, as shown in Figure 7b,c. Additional criteria are required to devise the best combination of reversed switching. Therefore, the variations of the neutral-point current are taken into account. Although the average of the neutral-point current in a switching cycle is equal to zero in all cases, the lower the RMS value the lower the NPV fluctuations within a switching cycle would be. The instantaneous neutral-point current is expressed as [23]:

$$i_{NP}=-\left(\right|S_a|i_a+|S_b|i_b+|S_c\left|i_c\right)$$

(18)

where $S_x$ is the switching state of phase x. The RMS value of the neutral-point current in each switching cycle is chosen as a performance criterion. For unity power factor, the neutral-point current deviation in the first Sector is shown in Figure 10 when either $u_{max}$ or $u_{min}$ is used at all times for the reversed switching. The asymmetric pattern of the neutral-point current is notable in both figures. It is assumed that the maximum output current is equal to one.

Figure 10. Neutral-point current (rms) in the first Sector for unity power factor when (a) $u_{max}$ is reversed, (b) $u_{min}$ is reversed.

Based on the discussion above, in this paper, a new hybrid modulation is applied by combining the two mentioned cases, where both $u_{max}$ and $u_{min}$ are utilized for reversed switching. Using the SVD to divide each sector into two subsectors, in the first half of Sector I, $u_{max}$ is used for the reversed switching, while $u_{min}$ is used for the reverse switching in the second half. By using this strategy, the total neutral-point current variation is minimized. The resultant neutral-point current in the first Sector is depicted in Figure 11. The SVD of the proposed hybrid modulation is shown in Figure 12.

Figure 11. Neutral-point current (rms) of the proposed hybrid modulation for unity power factor in the first Sector.

Figure 12. Space vector diagram of the proposed hybrid CBPWM with reduced CMV.

4. Active NPV Controller

In ideal conditions, the average NPV is zero and the voltages of the DC-link capacitors are equal. However, in practice $V_{C1}$ and $V_{C2}$ would drift from $V_{dc}/2$ due to various disturbances. Some of the influencing factors are the leakage current flowing through the ground wire and unequal DC-link capacitors. Therefore, an active controller is required to reduce the fluctuations of the neutral-point voltage.

The method proposed in [15] is used here for NPV balancing. since the neutral-point current is influenced by level 0 of each phase, the NPV deviations can be controlled by adjusting the level 0 of one or more phases. Notice that the line-to-line voltage should not be affected. In this paper, only the median phase $u_{mid}$ is used for level 0 adjustment. The reason is that the line voltage can be kept the same since $u_{mid}$ contains all three levels and hence there is no need to update the other phases.

In Figure 13, the adjustment of the duty ratio of $u_{mid}$ is depicted. Assuming level 0 should be changed by $\mathsf{\Delta }{d}_{mid,0}$, the duty ratio of level 1 and level −1 should likewise be updated since $\mathsf{\Delta }{d}_{mid,0}=\mathsf{\Delta }{d}_{mid,1}+\mathsf{\Delta }{d}_{mid,-1}$. In order to keep the line-to-line voltage the same, the voltage changes of $V_{mid}$ should be zero:

$$\mathsf{\Delta }{V}_{mid}=\mathsf{\Delta }{d}_{mid,1}{V}_{C1}-\mathsf{\Delta }{d}_{mid,-1}{V}_{C2}=0\Rightarrow \frac{\mathsf{\Delta }{d}_{mid,1}}{\mathsf{\Delta }{d}_{mid,-1}}=\frac{V_{C2}}{V_{C1}}$$

(19)

where $V_{C1}$ and $V_{C2}$ are the DC-link capacitor voltages. Hence, duty ratio adjustment of different levels of $u_{mid}$ can be calculated as follows:

$$\mathsf{\Delta }{d}_{mid,1}=\frac{\mathsf{\Delta }{d}_{mid,0}}{1+K_{dc}},\mathsf{\Delta }{d}_{mid,-1}=\frac{K_{dc}\mathsf{\Delta }{d}_{mid,0}}{1+K_{dc}}$$

(20)

$K_{dc}=V_{C1}/V_{C2}$.

Figure 13. Adjusting the duty ratio of the median phase, $u_{mid}$, for NPV control.

Figure 13. Adjusting the duty ratio of the median phase, $u_{mid}$, for NPV control.

Assuming that the voltage difference between the DC-link capacitors is $\mathsf{\Delta }{V}_{dc}=V_{C1}-V_{C2}$, the required compensating current for NPV adjustment is obtained by the following equation:

$$i_{cmp}=\frac{\mathsf{\Delta }{V}_{dc}(C_1+C_2)}{T_s}$$

(21)

Because only $u_{mid}$ is used for level 0 adjustment, the compensated current after adjustment is equal to $i_{cmp}=\mathsf{\Delta }{d}_{mid,0}·i_{mid}$. Therefore,

$$\mathsf{\Delta }{d}_{mid,0}=\frac{\mathsf{\Delta }{V}_{dc}(C_1+C_2)}{T_s{i}_{mid}}$$

(22)

Thus, the duty ratio adjustments can be obtained from (22) and (20). It should be mentioned that the duty ratio adjustment is limited to the initial values. For example, when $\mathsf{\Delta }{d}_{mid,0}>0$ (the case shown in Figure 13), it is limited by $d_{mid,1}$ and $d_{mid,-1}$. This limitation can be mathematically expressed as:

$$0<\mathsf{\Delta }{d}_{mid,0}<min\{d_{mid,1}(1+K_{dc}),\frac{d_{mid,-1}(1+K_{dc})}{K_{dc}}\}$$

(23)

When $\mathsf{\Delta }{d}_{mid,0}<0$, it is limited by $d_{mid,0}$:

$$-d_{mid,0}<\mathsf{\Delta }{d}_{mid,0}<0$$

(24)

From (22), one can conclude that the compensating capacity is a function of the adjusted phase current, the DC-link capacitors, and the imbalance level of the capacitors. Furthermore, the compensating capability is not symmetric about zero according to (23) and (24). In Figure 14, positive and negative compensating currents are shown for different modulation indices and for two different power factors.

Figure 14. Positive and negative compensating currents in Sector I when (a) $\varphi =0$, (b) $\varphi =\pi /4$.

It is noticeable that the positive and negative compensating currents are not symmetric in Sector I. Therefore, the average current is calculated in a fundamental cycle using (25) and depicted in Figure 15 for various power factors and modulation indices. From Figure 15, one can conclude that the compensating current value is always non-zero, meaning that the controller is capable of balancing the neutral-point voltage in all operating conditions. However, the recovery speed is dependent on the power factor and modulation index. The controller can balance the NPV more quickly in low power factors and lower modulation indices.

$$i_{cmp\pm ,avg}=\frac{1}{2\pi }{\int }_0^{2\pi }{i}_{cmp\pm }\left(\omega t\right)d\omega t$$

(25)

Figure 15. Average positive and negative compensating currents under different power factors and modulation indices.

5. Experimental Results

In this section, experimental results are presented to verify the performance of the proposed modulation. The experimental setup of the ANPC is shown in Figure 16 and the experimental parameters are listed in Table 4. Three modulation schemes are implemented in a TMS320f28379D microcontroller. The first case we examine is the conventional carrier-based modulation. The second case is the double modulation wave CBPWM with CMV reduction implemented in [19]. Lastly, the proposed hybrid CBPWM is applied to the inverter.

Figure 16. The experimental setup of the 3-L ANPC.

Table 4. Experimental parameters.

Symbol	Description	Value
$V_{dc}$	input DC voltage	200 V
$f_{sw}$	switching frequency	50 kHz
$f_o$	fundamental frequency	833 Hz
$C_1,C_2$	DC-link capacitors	72 $\mathsf{\mu }$F
m	modulation index	0.75
L	load inductance	200 $\mathsf{\mu }$H
R	load resistance	1 $\mathsf{\Omega }$

The experimental results are repeated for two cases: Case I considers using only an inductance load and a power factor ($\mathsf{\Phi }$) $=0$, whereas in Case II a series $RL$ load is used and a power factor ($\mathsf{\Phi }$) $=0.7$. Measured line-to-line voltage, DC-link capacitor voltages, and generated common-mode voltages for all three modulations are shown in Figure 17 and Figure 18.

Figure 17. Measured line-to-line voltage, DC-link capacitor voltages, output current $i_a$, common-mode voltage $U_{cm}$, and harmonic content for Case I; (a) conventional CBPWM, (b) RCMV-CBPWM where only phase a is reversed, (c) proposed RCMV-CBPWM.

Figure 18. Measured line-to-line voltage, DC-link capacitor voltages, output current $i_a$, common-mode voltage $U_{cm}$, and harmonic content for Case II; (a) conventional CBPWM, (b) RCMV-CBPWM where only phase a is reversed, (c) proposed RCMV-CBPWM.

It can be seen that RMCV-CBPWM methods can suppress the CMV compared to the conventional CBPWM. The proposed method has lower harmonic content compared to the second method, however the conventional method results in the lowest harmonic. The main harmonics of the common-mode voltage are listed in Table 5 and Table 6, demonstrating that the proposed method produces the smallest harmonics. The performance of the active neutral-point controller is shown in Figure 19. A voltage perturbation is enforced to assess the NPV controller. The initial voltage error is 14 V and the controller recovers the voltage balance within 7 fundamental cycles.

Table 5. Harmonic content of CMV for case I.

	${\mathit{h}}_1$	${\mathit{h}}_3$	${\mathit{h}}_5$
conventional CBPWM	31.2	1	2.04
RCMV-CBPWM	11.37	1.17	0.08
proposed RCMV-CBPWM	6.6	0.83	0.05

Table 6. Harmonic content of CMV for case II.

	${\mathit{h}}_1$	${\mathit{h}}_3$	${\mathit{h}}_5$
conventional CBPWM	32.6	0.68	2
RCMV-CBPWM	15.9	1.37	0.6
proposed RCMV-CBPWM	12.8	1.2	0.24

Figure 19. Experimental results of voltage balancing control with the proposed method.

Conventional CBPWM provides the lowest THD at the expense of high common-mode voltage and NPV oscillations. In comparison with the available RCMV-CBPWM, the proposed modulation can effectively reduce the harmonic distortion, as well as the NPV oscillation. Furthermore, the generated CMV has lower harmonics.

6. Conclusions

In order to reduce the common-mode voltage and eliminate the neutral point oscillations in a three-level active NPC inverter, a new hybrid carrier-based PWM is proposed in this paper. This modulation is derived based on the theoretical analysis of the common-mode voltage and the neutral-point current ripples. Space vectors are selected to minimize the neutral-point current ripple. Furthermore, the proposed method limits the common-mode voltage and lowers the harmonics. A new space vector diagram is also provided.

Experimental results show that the proposed hybrid modulation effectively reduces the common-mode voltage and neutral-point voltage oscillations in comparison with the conventional CBPWM. This modulation is an improved RCMV-CBPWM that produces lower harmonic content and lower CMV harmonics.