A Tile-Based, Adaptable Boost Converter with Fast Transient Response and Small Voltage Ripples in 40 nm CMOS Technology

Round 1

Reviewer 1 Report

The manuscript is interesting, but the text needs a lot of improvement, as pointed below. Also, a review of written English should be accomplished. Some parts are hard to follow and understand.

1) The subscript letters need to be bigger and more readable (Cfly, Vin, etc.). Use subscripts, not small letters.

2) Figure 1 is too large. It would be helpful to mark the timing phases directly into the schematic. E.g. using the Greek symbol phi, i.e. phase 1 (phi1), phase 2 phi2).

3) Stray capacitance's impact will be negligible compared with the parasitic capacitances of CMOS switches. For example, high and nonlinear ron, charge injection, etc., significantly affect SC circuits. The post-layout simulation should show this effect.

4) Using dots to indicate connections in the schematics would be best. Sometimes it takes work to recognize if two lines are crossing each other or they are connected. Moreover, you draw knots somewhere (Fig. 3 and 5). It is misleading.

5) All components in the schematics should be labeled. For example, you write ", a sense resistor to..."; however, there are two resistors in the schematic. You probably mean the resistor divider.

7) Figure 3 is quite large; however, the capacitors are small with unreadable captions.

8) Figure 8 shows output voltages for several load currents. Load regulation factor in %/mA would be good to define the system performance.

9) When the mentioned literature does not provide FOM, the efficiency factor should be a good way to compare your design.

Author Response

Please check the attachment

Author Response File: Author Response.pdf

Reviewer 2 Report

I have the following comments and suggestions. 

1.     This work uses multiple charge pump tiles to adapt to different output loads? It claims a fast transient response. Why is it faster than conventional frequency and pulse width modulation methods? A system-level simulation is suggested.

2.     The current bleeder circuit in Fig. 6 has an enable pin and many configuration switches? How are they ensured to be in the right condition when powering up? For example, is it possible that the enable pin is high initially, which effectively shorts the output and prevents powering up.

3.     Why is the output capacitor designed to be small?

4.     Single Inductor Multiple Output (SIMO) regulators are gaining popularity. How would you compare this work to SIMOs? With what kind of modifications, can it support multiple outputs?

Author Response

please check attached document 

Author Response File: Author Response.pdf

Reviewer 3 Report

The authors present a boost converter based on adaptable tiles, turned on/off depending on the value of the output voltage. The proposed solution is not very original and does not seem to introduce higher benefits compared to other works (for example, the area consumption seems not so competitive). I suggest the authors to better emphasizes the novelties of their work and to provide more convincing simulation results.

Here there is a list of the major concerns that in my opinion need to be addressed:

- Please correct the caption of Figure 12 (load changes from 6 mA to 0 mA).

- It is not clear why the output settles on a higher value in case of zero load. From simulations in Figure 11-12, the differences between the cases of zero and non-zero load is on the order of the output variations shown in Fig.8 (so not so critical, I assume). Moreover, it is not clear if the current bleeder is always enabled in those simulations. I suggest to include a graph to show the difference with and without the current bleeder. 

- What about the 2-bits of programmability of the current bleeder to control the amount of bleeded current? How are they set?

- I suggest to add a graph with the output ripple vs load current, instead of all the different graphs of Figure 8, which do not add much.

- Is the load present during the startup shown in Figure 10? It would be interesting to add a comparison in the startup behavior with and without OK circuit in presence of the load. Moreover, the authors claim that disabling the OK circuit settles 50 mV higher than the regulated value: is this difference really critical? I suggest to consider also PVT variations in the simulation results to ensure that they don't add variations larger than 50 mV on the output voltage.

- More details about the design criteria for the tiles, considering the trade-offs among current capability, ripple and area would be and added value. In particular, the authors could add some considerations about the design of the feedback loop in terms of stability and oscillation of the number of the engaged charge pumps in steady-state conditions.

- Please update the bibliography (also for the state-of-art comparison table). Cite the paper about the StrongARM comparator.

Author Response

please check attached document

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

All my comments have been addressed. I have the last minor comment. Please, add dots to indicate connections in Fig. 1 and Fig. 6.

Author Response

Thank you so much for your replies

It really enriched the quality of the manuscript

I have updated the two pictures mentioned

Reviewer 2 Report

My concerns have been mostly addressed. 

Author Response

Thank you so much for your replies

It really enriched the quality of the manuscript

Reviewer 3 Report

The authors improved the paper accordingly to the comments of the previous revision round. 

Author Response

Thank you so much for your replies

It really enriched the quality of the manuscript