Fully Integrated 1.8 V Output 300 mA Load LDO with Fast Transient Response

Abstract

Based on an 0.18 μm process, this paper proposes a fully integrated 1.8 V output 300 mA load low-dropout linear regulator (LDO) with a fast transient response. By inserting a transient-enhanced biased Class AB super source follower at the gate of the output power transistor, this LDO can quickly adjust the gate voltage of the power transistor without additional power consumption. By adding an active capacitor circuit composed of a fast comparator with offset voltage at the output point, this LDO can quickly charge/discharge the transient current and accelerate the transient response without reducing the circuit stability. Simulation results show that the proposed LDO has an output voltage of 1.8 V, when the input voltage is 2 V to 5 V while consuming 66.4 μA of quiescent current. The proposed capless LDO has a 1.94 µV/mA load regulation, a 0.55 mV/V linear regulation, and a −60 dB@1 kHz power supply rejection. When the load current steps from 3 mA to 300 mA in 300 ns, the LDO settles in 400 ns with an overshoot and undershoot of 67 mV and 86 mV, respectively.

1. Introduction

Power management integrated circuits (PMICs) provide highly integrated, high-performance power management solutions for a wide range of applications including automotive, consumer, and telecom electronics [1,2,3,4]. The low-dropout linear regulator (LDO) is one of the important branches of PMICs, which can generate stable, low noise, and accurate output voltage from the battery [5,6,7,8]. To prolong battery life and improve power efficiency and stability, LDOs need to minimize quiescent current and voltage drop while maintaining good regulation, load capability, and fast transient response, which are major concerns in LDO design [9,10,11,12].

Traditional LDO regulators use large off-chip capacitors to obtain good transient performance, but this kind of LDO has the disadvantages of large chip area, high cost, and is not conducive to realizing fully integrated chips [13,14,15,16]. However, in fully integrated LDOs, the transient response and stability are significantly reduced due to the absence of the off-chip capacitor, thus becoming the major design challenge [17,18,19,20,21].

In order to solve the above problems, many solutions have been proposed. For example, [22] proposed an adaptive transient current distribution technique to accelerate the transient response of LDO without off-chip capacitors. However, the threshold of the inverter used to detect the overshoot/undershoot voltage was easily affected by the power supply voltage and process fluctuations, and the load capacity of this design was only 10 mA. The authors in [23] used a digital circuit to realize the transient enhancement of LDO, but the quiescent current of 495 μA was too high, which was not suitable for short-life battery-powered equipment. The authors of [24] inserted a transient enhancement circuit from the drain to the gate of the power output transistor to make it AC-coupled and performed frequency compensation on the high slew rate error amplifier to achieve the stability of LDO and improve the load capacity without an off-chip capacitor. However, the overshoot and undershoot voltages were 170 mV and 234 mV, which needed further optimization. In other solutions, such as those found in [25,26], the transient response was improved by using adaptive biasing, but circuit complexity and power consumption were increased. Additionally, some LDOs required a minimum load current to be stable, as in [27,28], resulting in increased power consumption and light-load stability issues. The authors of [29] propose an LDO based entirely on on-chip FVF. Double buffers were inserted into the cascode flipped voltage follower (FVF) topology for better power supply rejection (PSR) and reduced voltage variation during load transients. However, the maximum load current of this design is 10 mA, while the quiescent current is 100 μA, and the load regulation rate is 1.21 mV/mA, which needs further optimization. In addition to performing transient compensation on the gate of the power transistor, the authors of [30,31] propose a current mirror-based active capacitor structure for transient enhancement at the LDO output, but this structure lacks large current and capacitive load capacity. In short, designing a fully integrated LDO with a strong load capacity and good transient performance requires a trade-off between power consumption, load capacity, transient characteristics, and stability [32,33,34,35].

In this paper, a 300 mA load, fully integrated, low-dropout regulator with a fast transient response is presented. A transient enhanced biased Class AB super source follower structure is proposed to dynamically increase the slew rate and improve stability. Additionally, an active capacitor circuit composed of a fast comparator with offset voltage is proposed, which can inject/sink current to/from the output point to further enhance the transient response. Additionally, this design incorporates a temperature and voltage-independent reference voltage source to realize truly integrated devices. This paper is organized as follows: Section 2 presents the proposed transient enhancement technique and the design of the proposed LDO. Section 3 reports simulation results and comparisons with other LDO. Finally, Section 4 draws conclusions.

2. Proposed Transient Enhancement Technology and Fully Integrated LDO

The structure of the proposed LDO is shown in Figure 1. The input power $V_{in}$ from the battery is regulated by a multi-loop regulator to output a stable voltage $V_{out}$. The main regulation loop consists of the feedback resistor, bandgap reference, error amplifier, source follower, and pass transistor. The function of the feedback resistor is to sense the variations over $V_{out}$ due to the variations of the supply voltage/load current. The error amplifier is responsible for comparing the feedback voltage $V_{fb}$ with the reference voltage $V_{ref}$ and controlling the pass transistor to make necessary modifications to the output voltage to maintain it at the desired voltage.

Based on the main regulation loop described above, a transient-enhanced biased Class AB super source follower (TEB Class AB SSF) is proposed in this design. Compared with traditional source followers, this structure has a higher slew rate and a transient-enhanced bias current to achieve a faster transient response at the gate of the power transistor. Additionally, this paper proposes an active capacitor structure for transient enhancement of the output point by using a fast comparator with offset voltage and higher bandwidth to quickly drive the control element to sink/source current to/from the output during transients without affecting the operation of the circuit under static conditions. This structure can further accelerate transient performance without compromising circuit stability.

2.1. Transient-Enhanced Biased Class AB Super Source Follower

In order to provide a load current of 300 mA, the size of the pass transistor of the LDO needs to be large so that the gate-source parasitic capacitance will also be large. In order to make the load regulation and linear regulation meet the design requirements, the error amplifier is required to have a higher gain, thus increasing the output resistance. If the output of the error amplifier were connected directly to the gate of the pass transistor, a very low-frequency pole would be created, affecting the stability of the circuit at light loads. In addition, the charge and discharge slew rate of the gate-source parasitic capacitance of the pass transistor is limited by the tail current source of the error amplifier. Therefore, a source follower should be inserted between the output of the error amplifier and the gate of the pass transistor to lower the resistance and separate the pole into high frequencies while increasing the slew rate [36]. The commonly used source follower is the single-transistor source follower and the super source follower is shown in Figure 2.

The PMOS source follower in Figure 2a is a widely used Class A voltage buffer. Although this structure can quickly absorb the current from the gate-source parasitic capacitance and has a simple structure, the maximum current it can provide is limited by the bias current $I_B$. The maximum positive slew rate (SR) is $I_B/C_{PASS}$, where $C_{PASS}$ is the gate capacitance of the pass transistor. In addition, as shown in the following expression, the output resistance $R_{OUT1}$ is still large.

$$A_{V1}=\frac{1}{1+g_{mb1}/g_{m1}+1/g_{m1}{r}_{o1}}$$

(1)

$$R_{OUT1}=\frac{1}{g_{m1}+g_{mb1}}$$

(2)

The super source follower in Figure 2b can reduce the output resistance due to the addition of ${\mathrm{M}}_3$, while ensuring that the transfer function is almost unchanged. However, this structure is still a Class A working mode, and the positive slew rate is still limited by the bias current.

$$A_{V2}=\frac{1}{1+g_{mb2}/g_{m2}+1/g_{m2}{r}_{o2}+1/g_{m2}{r}_{o2}{g}_{m3}{r}_{o3}}$$

(3)

$$R_{OUT2}=\frac{1}{(g_{m2}+g_{mb2})g_{m3}\left(r_{o2}//r_{o2I_B}\right)}$$

(4)

Based on quasi-floating gate technology [36,37,38], this paper proposes a Class AB super source follower with a transient-enhanced bias to solve the problem of positive slew rate limitation and improve transient response. The circuit diagram is shown in Figure 3a, where $V_I$ is connected to the output of the error amplifier, and $V_O$ is connected to the gate of the pass transistor.

It works as follows, a high-pass filter composed of a large impedance ${\mathrm{M}}_{\mathrm{T}1}$, pseudo-resistor, and ${\mathrm{C}}_1$ is inserted into the super source follower. Thus, node A becomes a quasi-floating gate (QFG) node [39,40]. Without increasing the quiescent current, ${\mathrm{C}}_1$ couples the AC variations of node C to node A with an attenuation equivalent to $\alpha =C_1/(C_{GS6}+C_1)$, where $C_{GS6}$ is the parasitic capacitance at the gate of ${\mathrm{M}}_{\mathrm{S}6}$. The minimum frequency of the AC signal that can be coupled to node A is the cut-off frequency $1/\left(2\pi R_{T1}{C}_1\right)$ of the high-pass filter, where ${\mathrm{R}}_{\mathrm{T}1}$ is the equivalent impedance of the diode-connected MOS transistor operating at the cut-off region, which is on the order of giga-ohms. So that the cut-off frequency is usually lower than 1 Hz, only the DC voltage is not transmitted. This structure enables the ${\mathrm{M}}_{\mathrm{S}6}$ and ${\mathrm{M}}_{\mathrm{S}8}$ to behave as Class AB push–pull output stages during dynamic operation, addressing the positive slew rate limitation of the traditional structures. For example, when $V_I$ is a positive input swing, $V_O$ is a positive swing, and the drain of ${\mathrm{M}}_{\mathrm{S}7}$ is a negative swing. ${\mathrm{C}}_1$ couples the change at the drain of ${\mathrm{M}}_{\mathrm{S}7}$ to the gate of ${\mathrm{M}}_{\mathrm{S}6}$, and the current of ${\mathrm{M}}_{\mathrm{S}6}$ is transiently increased, thereby increasing the positive slew rate. The DC transfer function and output resistance expressions of this structure are as follows:

$$A_{V3}=\frac{1}{1+g_{mbs7}/g_{ms7}+1/g_{ms7}{r}_{os7}+1/g_{ms7}\left(r_{os3}//r_{os7}\right)\left(g_{ms8}+\alpha g_{ms6}+\beta g_{ms3})(r_{os6}//r_{os8}\right)}$$

(5)

$$R_{OUT3}=\frac{1}{(g_{ms7}+g_{mbs7})\left(g_{ms8}+\alpha g_{ms6}+\beta g_{ms3}\right)\left(r_{os7}//r_{os6}\right)}$$

(6)

where $\beta =C_2/(C_{GS3}+C_2)$, and $C_{GS3}$ is the parasitic capacitance at the gate of ${\mathrm{M}}_{\mathrm{S}3}$. Figure 3b shows the slew rate simulation results. It can be seen that the positive (SR+) and negative (SR−) slew rates of the proposed TEB Class AB SSF are 43.61 V/μs and 88.26 V/μs, respectively. Compared with the traditional structure, the slew rate of this design is significantly improved, which solves the Class A working mode of the traditional source follower.

Apart from using quasi-floating gate technology to implement the Class AB operating mode [36], this design inserts ${\mathrm{M}}_{\mathrm{T}2}$ and ${\mathrm{C}}_2$ between the node B and the output ($V_{OUT}$) of the LDO. In this way, a short transmission path from $V_{OUT}$ to node C via ${\mathrm{M}}_{\mathrm{S}3}$ is added to form a transient enhancement bias circuit. Without increasing the quiescent current, ${\mathrm{C}}_2$ detects the change of LDO output voltage $V_{OUT}$ and couples it to the gate of ${\mathrm{M}}_{\mathrm{S}3}$ with an attenuation equivalent to β, which further accelerates the transient response. For example, when the load jumps from light load to heavy load, an undershoot voltage occurs, and ${\mathrm{C}}_2$ couples the undershoot voltage to the node B, so that the drain voltage of ${\mathrm{M}}_{\mathrm{S}3}$ rises rapidly, instantly increasing the discharge current of the gate capacitance of the pass transistor. At the same time, the variation at the gate of ${\mathrm{M}}_{\mathrm{S}8}$ is coupled to the gate of ${\mathrm{M}}_{\mathrm{S}6}$ by ${\mathrm{C}}_1$ and quickly turns off ${\mathrm{M}}_{\mathrm{S}6}$, thereby accelerating the transient response.

2.2. Proposed Active Capacitor Circuit

In addition to the above transient enhancement structure, this paper also proposes an active capacitor circuit as shown in Figure 4. The active capacitor functions like a large-value passive capacitor at the LDO output. It instantly detects the output voltage variation and provides a transient source/sink current to suppress it under load-step changes [30,31]. Different from the active capacitor in the main loop of the LDO in [30], the active capacitor proposed in this design is only an auxiliary transient enhancement structure. This circuit consists of 12 transistors ${\mathrm{M}}_{\mathrm{C}1}$–${\mathrm{M}}_{\mathrm{C}2}$. When the load current jumps from heavy load to light load, the fast comparator composed of ${\mathrm{M}}_{\mathrm{C}1}$–${\mathrm{M}}_{\mathrm{C}5}$ detects the overshoot voltage and turns on ${\mathrm{M}}_{\mathrm{C}6}$ for transient discharging. When the load jumps from light load to heavy load, the fast comparator composed of ${\mathrm{M}}_{\mathrm{C}7}$–${\mathrm{M}}_{\mathrm{C}11}$ detects the undershoot voltage and turns on ${\mathrm{M}}_{\mathrm{C}12}$ for transient charging. Because the sizes of ${\mathrm{M}}_{\mathrm{C}6}$ and ${\mathrm{M}}_{\mathrm{C}12}$ are much smaller than the pass transistor ${\mathrm{M}}_{\mathrm{P}}$, the bandwidth of the two fast comparators is greater than that of the main error amplifier, so the response speed is faster than the main loop.

By setting the input offset voltage of the fast comparator, the active capacitor circuit only operates when overshoot/undershoot occurs to avoid reducing system stability. Under dynamic conditions, when $V_{fb}\ge V_{ref}+V_{os,in}$, ${\mathrm{M}}_{\mathrm{C}6}$ is turned on to source current from $V_{out}$. Conversely, when $V_{fb}\le V_{ref}-V_{os,in}$, ${\mathrm{M}}_{\mathrm{C}12}$ is turned on to sink current into $V_{out}$. Taking the fast comparator composed of ${\mathrm{M}}_{\mathrm{C}1}$–${\mathrm{M}}_{\mathrm{C}5}$ as an example, the input offset voltage expression is:

$$V_{OS,in}=\frac{{(V_{GS}-V_{TH})}_{mc2,3}}{2}{\left[\frac{\mathsf{\Delta }\left(W/L\right)}{W/L}\right]}_{mc2,3}-\mathsf{\Delta }{V}_{TH,mc2,3}+\left\{\frac{{(V_{GS}-V_{TH})}_{mc4,5}}{2}{\left[\frac{\mathsf{\Delta }\left(W/L\right)}{W/L}\right]}_{mc4,5}-\mathsf{\Delta }{V}_{TH,mc4,5}\right\}\frac{g_{mc4,5}}{g_{mc2,3}}$$

(7)

It can be seen that the input offset voltage is determined by setting the W/L of the input transistor. This structure acts as an active capacitor at $V_{OUT}$, which can transiently source/sink current from/to $V_{OUT}$.

2.3. Proposed Fully Integrated Low Dropout Linear Regulator with Fast Transient Response

The fully integrated LDO with a fast transient response proposed in this paper is shown in Figure 5, including the bandgap reference, the error amplifier, the class AB super source follower with transient enhanced bias, and the active capacitor circuit. Additionally, there is an enable circuit (not shown in Figure 5) for turning on/off the LDO. Bandgap references generate bias and reference voltages that are independent of power supply and temperature and provide them to other circuits. The error amplifier detects the difference between the feedback voltage $V_{fb}$ and the reference voltage $V_{ref}$ and transmits it to the transient enhanced biased Class AB super source follower (TEB Class AB SSF). The Class AB super source follower increases the slew rate at the gate of the pass transistor and improves the transient response while reducing the impedance at this point to enhance circuit stability. The active capacitor circuit provides a fast source/sink current from/to the output point during load transients.

In order to verify the impact of the proposed transient enhancement circuits on load transient behavior, a comparative simulation is carried out in this paper, and the results are shown in Figure 6. From the simulation results, it can be seen that the proposed active capacitive circuit (A–C) and transient-enhanced biased Class AB super source follower (TEB SSF) can significantly enhance the load transient response.

To analyze the stability of the proposed LDO, the small-signal analysis model is shown in Figure 7. The active capacitor circuit is not included in the small-signal analysis because it has an offset voltage and therefore has no effect on the stability of the small-signal system. Without frequency compensation, this structure may have stability problems caused by the low frequency of the LDO output pole under light load. To solve this problem, this design adopts the nested Miller compensation technology composed of the gate parasitic capacitance $C_{\mathrm{gd}}$ of the power transistor and the Miller capacitance $C_{\mathrm{C}}$ to stabilize the system. The transfer function of the proposed LDO is derived as follows:

$$\frac{V_{OUT}}{V_{IN}}=\frac{-g_{mE}{R}_1{g}_{mB}{R}_2{g}_{mP}{R}_L\left(1-s{C}_C\left(1/g_{mP}-R_C\right)\right)}{\left(1+s{R}_1\left(\left(1+g_{mB}{R}_2{g}_{mP}{R}_L\right)C_C+C_{1,tot}\right)\right)\left(1+s{R}_2\left(C_2+\left(1+g_{mP}{R}_L\right)C_{gd}\right)\right)\left(1+s{C}_L\left(1/g_{mP}\right)\right)}$$

(8)

where $g_{mE}$, $g_{mB}\approx g_{mS7}/\left(\left(g_{mS7}+g_{mbS7}\right)R_{OUT3}\right)$, and $g_{mP}$ are the transconductance of the error amplifier, buffer, and the power transistor, respectively. $R_1=g_{mE9}{r}_{oE9}{r}_{oE11}//g_{mE7}{r}_{oE7}\left(r_{oE5}//r_{oE3}\right)$ and $C_{1,tot}=C_1+\left(1+g_{mP}{R}_{OUT}\right)C_C$ are the resistance and capacitance of node $V_1$, where $C_1=C_{gs,S7}$ and $R_{OUT}=r_{oP}//R_L$. $R_2=R_{OUT3}$ and $C_2=C_{gsP}+\left(1+g_{mP}{R}_{OUT}\right)C_{gdP}$ are the resistance and capacitance of node $V_2$. $C_C$ and $R_C$ are the Miller compensation capacitor and zeroing resistor, and $C_{gdP}$ is the parasitic capacitance of the power transistor. It can be obtained from the analysis that the expressions of the zeros and poles of the circuit are as follows:

$$p_1=\frac{-1}{R_1\left(\left(1+g_{mB}{R}_2{g}_{mP}{R}_L\right)C_C+C_{1,tot}\right)}$$

(9)

$$p_2=\frac{-g_{mP}}{C_L}$$

(10)

$$p_3=\frac{-1}{R_2\left(C_2+\left(1+g_{mP}{R}_L\right)C_{gd}\right)}$$

(11)

$$z_1=\frac{g_{mP}}{C_C\left(1-g_{mP}{R}_C\right)}$$

(12)

It can be obtained from the analysis that the dominant pole $p_1$ is at the output of the error amplifier. The $p_2$ non-dominant pole is located at the output of the LDO, and the frequency of this pole varies with the load capacitance. The gate of the pass transistor is the non-dominant pole $p_3$. Because this design uses a transient-enhanced biased Class AB super source follower with extremely small output resistance, the frequency of $p_3$ is outside UBW even under extreme conditions. In addition, the zeroing resistor $R_C$ makes the zero $z_1$ located in the left half plane, which offsets the influence of the pole $p_2$ and enhances the stability of the system.

In order to verify the stability of the proposed LDO, the stability of the LDO under different load conditions is simulated, and the results are shown in Figure 8. It can be seen that when the load capacitance is 0 pF and the load current changes from 0 to 300 mA, the phase margin (PM) of the proposed LDO is 70.1 deg@0 mA, 71.5 deg@100 μA, 72.8 deg@1 mA, 73.6 deg@100 mA, and 79.8 deg@300 mA. When the load current is 1 mA and the load capacitance changes from 0 to 100 nF, the phase margin of the proposed LDO is 72.8 deg@0 pF, 71.35 deg@100 pF, 67.71@1 nF, 54.45@10 nF, and 48.73@100nF. Therefore, the proposed LDO has good stability under all load conditions.

3. Layout and Simulation Results

The proposed LDO is designed on a 0.18 μm BCD process. Figure 9 shows the layout of this design, with an overall area of 610 µm × 523 µm (including pads). This design includes an enable circuit, a bandgap reference, an error amplifier, an active capacitor circuit, a transient-enhanced biased Class AB super source follower, and the power transistor. The designed circuit is simulated by Cadence Spectre, and the simulation results are shown as follows.

Figure 10a shows the simulation results of linear regulation and dropout voltage under different process corners. It can be seen that the proposed LDO has a constant output of 1.8 V, a dropout voltage of 200 mV, and a linear regulation of 0.55 mV/V when the input voltage ranges from 2 V to 5 V (I_L = 100 mA). Figure 10b presents the simulation results of load regulation under different process corners. It can be seen that when the load current changes from 0 to 300 mA (V_in = 3.3 V), the load regulation is 1.94 µV/mA.

Figure 11 shows the simulation results of power supply rejection (PSR) under different process corners. It can be seen that the PSR of the proposed LDO is −66 dB@0 Hz, −60 dB@1 kHz, and −40 dB@10 kHz. Therefore, the design has good power supply rejection characteristics.

The proposed LDO can supply a maximum load current of 300 mA. As shown in Figure 12, when the load current increases from 0 to 300 mA ($V_{in}$ = 3.3 V), the ground current of the proposed LDO varies from 66.4 μA to 76.2 μA under different process corners. When the input supply voltage increases from 2 V to 5 V ($I_L$ = 0 mA), the ground current of the proposed LDO varies from 30 μA to 100 μA under different process corners.

Figure 13 shows the transient response of the proposed LDO with and w/o active capacitors (A–C) and transient-enhanced bias Class AB super source follower (TEB SSF). The load current step is 100 μA–300 mA–100 μA, and the edge time is 1 μs. Figure 13a shows the behavior of the overshoot variations. The proposed LDO with an A–C structure can enhance the discharge process and reduce the maximum change to 175 mV within 3.5 µs. The proposed TEB SSF and A–C structure (TEB SSF and A–C) further strengthens this process and reduces the maximum change to 52 mV within 1.1 µs. Compared to an LDO without this structure, the setting time is shortened by 4.9 µs, and the overshoot voltage is reduced by 623 mV. Figure 13b shows the behavior of the undershoot variation. With the A–C circuit, the charging process can be enhanced, and the maximum change can be reduced to 280 mV within 2.5 μs. With the TEB SSF and A–C circuit, this process is enhanced to reduce the maximum change to 99 mV within 1.1 μs. Compared to an LDO without this structure, the setting time is shortened by 3.4 µs, and the undershoot voltage is reduced by 541 mV.

Figure 14 shows the load transient response simulation results of different edge times for 3–300 mA load steps. Figure 14a shows the load transient response of 3–300 mA@1 μs. The overshoot voltage is 38 mV, the undershoot voltage is 40 mV, and the setting time is 1.5 μs. Figure 14b shows the load transient response of 3–300 mA@300 ns. The overshoot voltage is 67 mV, the undershoot voltage is 86 mV, and the setting time is 400 ns.

Table 1. Performance comparison with state-of-the-art designs.

Parameter	[1]	[21]	[32]	[34]	This Work
Process (μm)	0.5	0.13	0.18	0.5	0.18
Area (mm2)	0.279	1.634	0.109	0.4	0.085
Supply Voltage (V)	2.3–5.5	5.3	1.31–3.3	3.5–5.5	2–5
Output Voltage (V)	1.2–5.4	5	1.2	3.3	1.8
Dropout Voltage (mV)	100	300	110	200	200
Maximum IL (mA)	150	300	50	300	300
IQ (μA)	>40	38	8.6	380	66.4
ΔVOUT (mV)	354	214	666	200	153
ΔIOUT (mA)	150	100	50	299	297
Edge Time Δt (μs)	1	NA	1	5	0.3
Setting Time(μs)	5	NA	3	8	0.4
Load Regulation (μV/mA)	NA	430	5.6	33.4	1.94
Line Regulation (mV/V)	NA	25	4.13	1.66	0.55
PSR (dB) at 1 kHz	−50	−51.9	−36.3	−65	−60
Minimum Required CTOT (pF)	29	1000	50	10	5
FOM (fs)	>18.251	NA	381.84	141.684	0.576

gives the performance summary and comparison with state-of-the-art designs. The proposed LDO provides a maximum output current of 300 mA and a regulated output voltage of 1.8 V over a supply range of 2–5 V. As can be seen from the comparison, this design has the fastest transient response and lowest load regulation with only 66.4 μA of quiescent current and without off-chip capacitors. This indicates that the proposed transient enhancement circuit structure can achieve a faster transient response and a more accurate output voltage.

To compare various regulators implemented in different technologies, an $FOM$ is adopted from [2]:

$$FOM=K\times \frac{C_{TOT}\times \mathsf{\Delta }{V}_{out}\times I_Q}{\mathsf{\Delta }{I}_{LOAD}^2}$$

(13)

$$K=\frac{\mathsf{\Delta }t\mathrm{used}\mathrm{in}\mathrm{the}\mathrm{design}}{\mathrm{the}\mathrm{smallest}\mathsf{\Delta }\mathrm{t}\mathrm{in}\mathrm{the}\mathrm{design}\mathrm{for}\mathrm{comparison}}$$

(14)

Among them, $C_{TOT}=C_{LDO}+C_{OUT}$, $C_{LDO}$ is the total capacitance used by the LDO internal circuit, and $C_{OUT}$ is the minimum output capacitance required when the LDO is stable. The smaller the $FOM$, the better the transient response achieved by the LDO. As shown in Table 1, the proposed LDO achieves the smallest $FOM$ factor among all these designs.

4. Conclusions

This work presents a 1.8 V output, 300 mA load fully integrated LDO with a fast transient response. A transient-enhanced biased Class AB super source follower is proposed to increase the slew rate at the gate of the power transistor to improve transient response while reducing the impedance of this node to enhance circuit stability. An active capacitor circuit is proposed to provide a fast source/sink current path at the output point during load transients, thereby achieving a fast transient response. Simulation results show that the proposed LDO has a linear regulation of 0.55 mV/V and a load regulation of 1.94 μV/mA. In particular, this design has an overshoot/undershoot voltage of 52/99 mV and a settling time of 1.1 μs when the load current varied from 100 μA to 300 mA with an edge time of 1 μs. When the load current steps from 3 mA to 300 mA in 300 ns, the LDO has a settling time of 400 ns and an output overshoot and undershoot voltage of 67 mV and 86 mV, respectively, achieving a transient FOM of 0.576 fs. In summary, the proposed LDO is suitable for applications such as modern fully integrated automotive sensor chips.