A 16-Bit 120 MS/s Pipelined ADC Using a Multi-Level Dither Technique

Abstract

In wireless applications, such as radars, tens of MHz signals need to be quantized using an analog-to-digital converter (ADC) with a large dynamic range. The detected signal amplitude can be random, with a small or large amplitude. In addition, the dynamic performance is degraded by capacitor mismatches. A 16-bit 120 MS/s pipelined ADC implemented in a 180 nm complementary metal–oxide–semiconductor (CMOS) process is presented in this work. We propose a multi-level dither technique that can significantly enhance the ADC linearity. The injected dither also helps improve the linearity when the ADC handles an input signal with a small amplitude. Traditional dither injection leads to an increase in the amplifier output swing. A counteracting dither injection scheme, both in sub-flash ADC and the multiplying digital-to-analog converter (MDAC), is proposed to remedy this issue. Moreover, capacitor mismatches in the first three pipeline stages are calibrated in a foreground way. The inter-stage residue gain accuracy is guaranteed by a gain-boosting amplifier. To demonstrate the effectiveness of the dither scheme, we obtained the dynamic performance of the ADC with a small input signal (−12 dBFS). The proposed calibration and dither injection technique improved the spurious-free dynamic range (SFDR) from 77 dBc to 85 dBc with −12 dBFS input. With −1 dBFS input, the SFDR remained at over 85 dBc, reaching up to the Nyquist input frequency. Therefore, the dither scheme enhances the dynamic performance when the ADC handles a signal with small amplitude.

1. Introduction

In wireless communication points, such as a base station or radar system, a large spurious-free dynamic range (SFDR) is essential to avoid interference from adjacent channels. In addition, tens of MHz of bandwidth are needed to cover the wideband input signal, thereby demanding a sample rate of >100 MHz [1,2,3,4,5,6]. A pipelined structure is usually employed in these scenarios [7,8,9,10,11,12]. All the pipeline stages operate concurrently, thereby enhancing the overall speed. Moreover, the inter-stage gain improves the accuracy because non-idealities in the back-end stages are attenuated by the gain in the preceding stages. However, two main factors limit the dynamic performance in pipelined analog-to-digital converters (ADCs). A capacitor mismatch in the multiplying digital-to-analog converter (MDAC) causes a bit-weight error. At the point of each comparator threshold, this bit-weight error leads to missing code or non-monotonicity [13]. In addition, the residue gain in the analog domain is requested to match the gain in the digital domain. Otherwise, quantization error leakage happens in the pipeline stage, severely deteriorating the dynamic performance [14]. Analog techniques can remedy the above issues but have a high cost [15,16,17,18]. Recently, the digital method has become preferable to resolve the bit-weight deviation problem, especially as complementary metal–oxide–semiconductor (CMOS) technology is now developing rapidly [19,20,21,22,23,24,25]. In [19,20,21], calibration speed was enhanced using a complicated digital algorithm with a large hardware cost. In [22,23], higher harmonics were calibrated, but the convergence speed was quite low since many parameters need to be calculated. In [24], the ADC was split and the analog circuit complexity significantly increased.

In [1,13], the authors proposed to solve the calibration of capacitor mismatch by switching the MDAC capacitors one by one. Then, all the error codes can be calculated and stored. The ADC output is reconstructed by adding or subtracting these error codes. However, the calibration accuracy is limited by the back-end ADC accuracy and the digital truncation error. Additionally, an input signal with a small amplitude is prone to a differential non-linearity (DNL) error caused by capacitor mismatch. Therefore, if the calibration accuracy is limited, the small signal conversion is degraded. To improve the linearity of the ADC, the dither technique is usually employed [26,27,28]. It provides several virtual comparison thresholds, which enhance the linearity, especially when the input signal amplitude is small. However, the injected dither decreases the signal range, thereby degrading the dynamic performance. Additionally, dither injection causes an increment in the residue signal, which degenerates the amplifier linearity. Moreover, the detailed circuit of the dither injection was not given.

This work proposes a multi-level dither technique that is implemented in a 16-bit 120 MS/s pipelined ADC. The proposed dither injection scheme is employed in both the flash sub-ADC and the MDAC parts. The voltage swing increment of the flash dither and MDAC dither are counteracted by each other. The dither signal in the residue signal path is subtracted in the digital domain, thus avoiding any dither leakage issue. The architecture of the whole ADC and the proposed dither scheme are introduced in Section 2. Section 3 gives the circuit implementation of the dither injection method in a 16-bit 120 MS/s pipelined ADC. The measurement results are given in Section 4. Finally, a conclusion is provided in Section 5.

2. Architecture of the Proposed Dither Injection Scheme

The linearity improvement effect relies on the number of the dither level [28,29]. We employ the theory in the 16-bit pipelined ADC, in which each stage consists of a flash sub-ADC and an MDAC. As shown in Figure 1, the first two stages resolve more bits than the latter stages owing to a trade-off between the power efficiency and circuit complexity [27]. Capacitor mismatches in the first three stages are calibrated, whereas the capacitor matching accuracy is enough in the back-end stages. The residue gain accuracy is guaranteed by the gain-boosting technique, thus avoiding a complicated background calibration algorithm [17]. For instance, the amplifier output in the first pipelined stage needs a 12-bit accuracy for the back-end stage. Therefore, the loop gain and bandwidth should achieve over 72 dB and 310 MHz, respectively. The proposed dither technique is adopted in the first pipeline stage, and the dithering effect is propagated to all the later pipeline stages.

Figure 2 illustrates a diagram of the first pipeline stage. The input signal (Vin) is sampled simultaneously by the sub-ADC with flash structure and the DAC capacitor (Cs). The sub-ADC employs 16 comparators, and their outputs (D) are used to switch the 16 capacitors in the MDAC directly, thereby saving time and improving the speed.

With this structure, the amplifier output can be approximately expressed as

$$V_{out}=\frac{C_s}{C_f}\times \left(V_{in}-\frac{{\displaystyle \sum _{i=1}^{16}{D}_i\times C_i}}{C_s}\times V_{ref}\right)$$

(1)

where C_i is the ith sampling capacitor, and V_ref is the reference voltage. V_ref equals the difference between the top reference (V_refp) and the bottom reference (V_refn). C_f is the feedback capacitor. It can be seen that the amplifier output is confined to the range from −1/2V_ref to 1/2V_ref. With the traditional dither injection scheme, the amplifier output exceeds this range [11]. Herein, we propose to inject the dither signal in both the sub-ADC and the DAC capacitor, which are called flash dither and MDAC dither in this work, respectively. The flash dither is realized by shifting the thresholds, which is explained in the next section. The DAC dither is implemented with an added capacitor array, which is switched by a multi-bit pseudo number (PN) generator. Note that the dither effect can be propagated along the pipeline chain, so it can also benefit the back-end pipeline stages.

3. Dither Injection Scheme and Its Circuit Implementation

Residue transfer curves are employed to explain the proposed counteracting dither technique. In Figure 3a, the black wave represents an ideal residue–input relationship curve, and the colored dots show the uniformly distributed dither injection locations. Figure 3a only shows six levels for simplicity. In Figure 3b, one level of dither around the threshold V_th1 is exemplified to depict the proposed counteracting dither technique.

The red arrow means a positive dither injection, and the blue one means a negative dither injection, both in the sub-ADC. Note that the dither injection causes the residue to exceed the original swing. The voltage swing due to the flash dither now ranges from −V_ref/2 − V_fd to V_ref/2 + V_fd, where V_fd is the flash dither amplitude. This voltage swing increment occupies the redundancy range that is otherwise allocated for other non-ideal factors, such as noise and offset. In addition, the inter-stage amplifier induces non-linearity owing to this larger voltage swing. To remedy this issue, we propose a counteracting dither technique. In Figure 3c,d, we inject a dither signal in the MDAC, and the direction is opposite to the flash dither. As shown in Figure 3c, the flash dither is positive (+V_fd) while a negative one (−V_md) is injected, and thus the residue swing restores to the original range. The other case is shown in Figure 3d. Consequently, if V_fd equals V_md, the maximum amplifier output remains the same if no dither signal is injected. The flash dither can linearize the injected pipeline stage, while the MDAC dither can be propagated to the back-end stages. The above dither injection scheme for V_th1 is simultaneously executed in all the 16 comparators in the flash ADC. The residue signal is randomized, so spurs from some uncalibrated factors are broken into the noise floor. The flash dither does not influence the final conversion result because it is corrected by the redundancy. Nevertheless, the MDAC dither must be precisely subtracted in the digital domain to avoid any dither leakage.

The number of the dither level determines the effect of the linearity improvement. We employ a 10-bit level MDAC dither. These dither levels are uniformly distributed in each sub-range. To realize the abovementioned counteracting dither technique, we modify the original MDAC and sub-ADC. The MDAC dither is realized by a capacitor array controlled by a dither generator and logic circuit, as shown in Figure 4. The least significant bit (LSB) of the MDAC dither is V_sub/2^M, where V_sub is the sub-range voltage, and M is the MDAC dither bit used. Note that the LSB of the MDAC dither amplitude is quite small. As a result, the dither DAC consists of a capacitor array with bridge capacitors, which can attenuate the weight of the capacitors and realize the small dither amplitude. In Figure 4, Cb2 attenuates the weights of C0 and C1, while Cb1 can attenuate the weights of C0 to C5 furthermore. The dither DAC is switched by a controller, as shown in Figure 5. The multi-level dither signal is generated by linear feedback shift registers (LFSR) designed in the digital domain [30].

Only a 1-bit MDAC dither controller is exemplified for simplicity. Q1 and Q2 are the sampling phase and the amplifying phase, respectively. During the sampling phase, Q1 is high, and the bottom plate of the corresponding dither capacitor is switched to a common mode voltage (V_cm). Then, during the amplifying phase, Q1 becomes low, and Q2 is high. The controlling signal Top or Bot becomes valid, according to the dither generator outputs (D_mdp and D_mdn). Therefore, the controller output switches the bottom plate of the dither capacitor to V_refp or V_refn, realizing the MDAC dither function. The controller output configuration during the amplifying phase is shown in

Table 1. The controller output.

Top	CM	Bot	Output
1	1	0	Vcm
1	1	0	Vcm
1	0	1	Vrefn
0	0	0	Vrefp

.

The flash sub-ADC contains 16 comparators, as shown in Figure 6. During the sampling phase (Q1), the input signal (V_s = V_ip − V_in) and the reference voltages are sampled to C₁ and C₂, respectively. For instance, the ith comparator samples the differential reference voltages Vthp[i] and Vthn[i], respectively. The charge on these capacitors during the sampling phase are expressed as:

$$\left\{\begin{array}{ll}{C}_1\times \left(0-Vthp\left[i\right]\right)+C_2\times \left(0-V_{ip}\right)& \mathrm{P}\mathrm{side}\\ C_1\times \left(0-Vthn\left[i\right]\right)+C_2\times \left(0-V_{in}\right)& \mathrm{N}\mathrm{side}\end{array}\right.$$

(2)

After the sampling ends, Q2 becomes high, and the input signals and reference voltages are all grounded. According to the principle of charge conservation, the differential input of the comparator core circuit is:

$$Vx=\frac{C_2}{C_1+C_2}\times V_s-\frac{C_1}{C_1+C_2}\times V_{th}$$

(3)

where V_th is the differential threshold voltage. It is noted that the capacitor mismatches in flash sub-ADC only causes an equivalent comparator offset, which can be absorbed by inter-stage redundancy. The comparator consists of a preamplifier and a latch [31,32]. In traditional flash ADCs, the threshold voltage can be generated by a simple voltage buffer. In this work, these threshold voltages are dithered, as in Figure 7.

The proposed flash dither scheme employs a resistor DAC with different bias currents, which are controlled by the dither generator output. As in Figure 7, a traditional voltage buffer is modified to implement the flash dither. Owing to the two negative feedback loops, V₁ and V₂ are nearly equal to V_refp and V_refn, respectively. All the 16 comparator thresholds are obtained from the two resistor chains. In this work, we added one resistor to each end of the resistor chain and two controlled currents to flow through the middle resistors. I_a and I_b are complementary, their sum is I and they are controlled by the N-bit dither codes. Therefore, these two currents flow into or out of the buffer, determined by the dither bit. The dither voltage can be calculated as follows:

$$V_d=\left(1-\frac{2I_b}{I}\right)\times \frac{V_{refp}-V_{refn}}{2^N}$$

(4)

Then, all the 16 comparator thresholds increase or decrease simultaneously, thereby realizing multi-level dither injection in the flash ADC. Note that the same dither bits are employed to control the flash dither and the MDAC dither so that the voltage swing increment is counteracted. Although the mismatch between these two dither injections causes a small swing incensement, it can be tolerated by the inter-stage redundancy.

4. Measurement Results

The proposed 16-bit 120 MS/s pipelined ADC with this novel dither scheme was implemented on a 180 nm CMOS process. Figure 8 illustrates the layout photo and the corresponding chip photo. The whole ADC takes up about 3.5 × 1.9 mm², and the circuit for flash dither and MDAC dither occupies about 1.54 mm², which is 23% of the whole ADC. The unit capacitor of the first stage is 18.6 × 20 μm². When the extra area is allocated for the capacitor, the matching accuracy is still worse than 16-bit according to the PDK file. The ADC consumes 347 mW, in which the additional circuit for the dither scheme only occupies about 5 mW. Figure 9 depicts the power spreadsheet of the main building blocks.

To demonstrate the effectiveness of the dither scheme, we obtained the dynamic performance of the ADC with a small input signal (−12.7 dBFS). As shown in Figure 10, without calibration or dither injection, the SFDR was about 78 dBc. This result is mainly due to a capacitor mismatch. With capacitor mismatch calibration, the SFDR improved to 81 dBc, as depicted in Figure 11. However, the small signal is prone to the residual uncalibrated error, and thus it only achieved a 3 dB improvement. In Figure 12, it can be seen that the SFDR could be significantly enhanced to 85 dB thanks to the proposed flash dither and MDAC dither.

With a large input signal (about −1 dBFS), the dynamic performance relied mainly on the analog front end. As depicted in Figure 13, after calibration, the SFDR of the ADC with a low frequency input could obtain about 90 dBc. Even with Nyquist input, the SFDR remained at over 85 dBc.

The capacitor mismatch also degraded the differential non-linearity (DNL) and integral non-linearity (INL). With the proposed calibration and dither injection scheme, DNL improved from 0.4 LSB/−0.41 LSB to 0.39 LSB/−0.41 LSB, and INL improved from 8.3 LSBs/−6.3 LSBs to 3.2 LSBs/−4.5 LSBs, as depicted in Figure 14 and Figure 15. According to the measurement results, the Walden figure of merit (FoM) was 416 fj/conv-step.

Table 2. Performance of the Proposed ADC and Comparison with Previous Works.

	[1]	[27]	[13]	This Work
Process (nm)	180	180	180	180
Supply (V)	1.8	1.8	1.8	1.8
Resolution (bits)	14	16	16	16
Power (mW)	300	385	342	347
Sampling rate (MHz)	250	125	120	120
SFDR (near full scale)	87.9	92	91	90
SNDR (near full scale)	68.2	78.6	77	77
SFDR (small signal)	N/A	85	N/A	85
SNDR (small signal)	N/A	78.1	N/A	77
FoM (fj/conv-step)	570	462	410	416

illustrates the comparison results with prior works that focused on similar ADC types. Note that only [27] and this work cared about the dynamic performance with a small input signal. Compared to [27], the FoM value in our work was more competitive. Moreover, the schemes proposed in [1,13] could barely handle a large input signal, as no dither injection was employed. Comprehensively, the proposed calibration and dither scheme greatly improve the dynamic performance and produce a relatively better FoM value.

5. Conclusions

A novel dither injection method using both flash and MDAC was proposed and verified in a 16-bit 120 MS/s pipelined ADC. The flash dither can linearize the first stage, while the MDAC dither propagates to the back-end ADC. The voltage swing increment is counteracted by other increments, significantly maintaining the linearity of the residue amplifier. The dither scheme enhances the dynamic performance when the ADC handles a signal with small amplitude. The proposed calibration and dither injection technique improved the SFDR from 77 dBc to 85 dBc with −12 dBFS input. With −1 dBFS input, the SFDR remained at over 85 dBc, reaching up to the Nyquist input frequency. Compared with the previous works, the proposed work achieves a competitive FoM value while quantizing a small input signal with high dynamic performance.