1. Introduction
Power semiconductor devices account for the largest portion of power loss in power converters [
1]. Conventional silicon (Si) power semiconductors are limited by breakdown voltage, operating temperature, and switching frequency, which significantly reduce the efficiency of power converters and necessitate complex and expensive cooling systems. Recently, wide bandgap (WBG) semiconductors, which include silicon carbide (SiC) and gallium nitride (GaN), with excellent characteristics, such as a large critical electric field, high electron mobility, and high thermal conductivity have been developed to overcome existing physical limitations. The superior characteristics of WBG semiconductors include low on-resistance, high switching speed, and high operating temperature to power semiconductor devices. Thus, power converters can achieve high efficiency and power density [
1,
2,
3,
4,
5].
However, to exploit WBG power semiconductors, more factors must be considered when using Si devices. WBG power semiconductors have a characteristic of fast switching speed attributed to their small input and output capacitances, while the disadvantages of a large
di/
dt and
dv/
dt. Therefore, WBG power semiconductors are significantly affected by parasitic inductance during switching transients, and this effect appears as ringing, undershooting, and overshooting of the voltage and current. These effects may increase the switching loss and weaken the advantage of WBG power semiconductors or even cause failure [
6,
7,
8,
9].
Therefore, minimizing the parasitic inductance of the printed circuit board (PCB) is necessary to operate WBG devices in a stable manner for increasing the efficiency and power density of the power converter by utilizing WBG power semiconductors.
Thus far, various methods have been proposed to minimize parasitic inductance. For example, it can be reduced by increasing the width of the conductor through which the current flows, or by reducing the length of the current loop [
10,
11,
12,
13,
14,
15]. The length of the power loop is minimized by directly mounting the decoupling capacitor onto a system-in-package (SiP) that comprises a half-bridge leg [
10]. This method can reduce the power loop inductance; however, soldering the capacitor directly to a SiP is complicated. In [
11], the capacitor was mounted directly on the die of a switching device, similar to that in [
10]. In [
12,
13], the current loop was significantly reduced by embedding components and devices into the PCB. Nielsen et al. [
12] proposed a structure that involves inserting capacitors vertically into the PCB, adjacent to the GaN-based half-bridge structure. Qi et al. [
13] suggested a half-bridge module, in which a GaN bare die was embedded into the inner layer of the PCB. Both of these methods minimize parasitic inductance by considerably reducing the current loop. However, they are complicated to implement because a specialized process is required. Lu et al. [
14] proposed a half-bridge module consisting of a decoupling capacitor and two GaN devices. Unlike methods proposed in [
12,
13], the proposed method is relatively simple to implement because there is no need for an additional process in the PCB. The method also maintains low inductance due to the placement of the decoupling capacitor in close proximity. However, it is only applicable to half-bridge-based converters and cannot be used for multi-level converters, such as Neutral Point Clamped inverters. The above methods are difficult to apply in the design of general power converters because they can only be applied to special packages or applications.
Accordingly, parasitic inductance reduction methods that use magnetic flux cancellation between adjacent conductors, which can be applied in the general case, have been studied [
15,
16,
17,
18,
19,
20,
21]. In [
15,
16,
17], structures can reduce parasitic inductance through single current loop-based magnetic flux cancellation. Reusch et al. [
15] and Reusch and Strydom [
16] placed conductors with opposite current directions close to each other to improve the magnetic flux cancellation. In [
17], the authors designed prototypes based on three types of single loop-based inductance reduction methods and compared their performance. The proposed methods successfully reduced parasitic inductance through improved magnetic flux cancellation; however, these methods have limitations in reducing parasitic inductance because they consider only a single current loop formed between the top and bottom layers, or in a single layer of the PCB.
In [
18,
19,
20,
21], multiple current loop-based inductance reduction methods were proposed to improve flux cancellation. In [
18], a switching package capable of constructing multiple current loops in a single layer was proposed. The package is configured to form several branches with currents in different directions adjacent to each other, allowing for reduced parasitic inductance. However, this is only applicable to certain package types of devices that can form multiple current loops. In [
19,
20,
21], more general multiple loop-based methods were proposed. Dechant et al. [
19] and Hammer et al. [
20] proposed structures that can improve the magnetic flux cancellation in multiple current loops without the limitation of package type. The proposed method improved magnetic flux cancellation between conductors by reversing the direction of the current flowing in adjacent layers in a multilayer PCB. However, these articles only presented a conceptual method and did not provide a quantitative interpretation of the improvement of inductance reduction by a multi-loop structure, nor did they provide a detailed design process based on it. Yang et al. [
21] completed the foundation of a multi-loop-based inductance reduction method by providing a detailed principle of inductance reduction by a multi-loop structure and its design method. However, the above methods [
19,
20,
21] did not fully utilize the inductance reduction effect of multi-loop structures because they only considered magnetic flux offset between layers, without considering the layers themselves.
In this study, a three-dimensional (3-D) lattice structure that can cancel the magnetic flux between the layers and in a single layer is proposed to further reduce parasitic inductance. The basic principle of magnetic flux cancellation is described, and a 3-D lattice structure is presented based on this principle. The proposed structure involves arranging a pair of adjacent PCB layers so that their current directions are opposite, leading to the cancellation of the vertical magnetic flux. Additionally, segments are inserted into each layer to generate horizontal flux cancellation. Subsequently, a pair of layers that can cancel both the vertical and horizontal fluxes are designated as reference layers and are repeated to form a multi-loop, which further enhances magnetic flux cancellation. The inductance reduction performance of the 3-D lattice structure is verified using ANSYS Q3D, and a detailed PCB layout design based on the proposed structure is also presented. Finally, improved switching performances, such as ringing, overshoot, and switching energies are experimentally verified.
3. Detailed PCB Layout Design of Proposed Three-Dimensional Lattice Structure
Figure 6 shows the parasitic inductance and current flow of a half-bridge leg during switching transients. The parasitic inductance consists of the high-side drain inductance
Ld,H of high-side devices
Q1, high-side source inductance
Ls,H, low-side drain inductance
Ld,L of low-side devices
Q2, and low-side source inductance
Ls,L. The current during the switching transients includes current
IC2Q flowing from the decoupling capacitor
Cdec to
Q1, a current
IQ2Q flowing from
Q1 to
Q2, and a current
IQ2C flowing from
Q2 to
Cdec. The direction of the current can be reversed based on the switching state of the device.
Figure 7 shows the four-layer PCB layout design with the proposed structure, which considers the parasitic inductance and current flow of the half-bridge leg. The design specifications are listed in
Table 2.
Vpk and
Ix were set to 650 V and 30 A, respectively, because the 650 V/30 A GaN power semiconductor GS66508T was selected as the switching device. Further,
wc,
t, and ∆
T were set as 18 mm, 0.07 mm, and 15 °C, respectively. While
d was set as 0.625 mm based on (7), and the proposed structure was applied to only the inner layer because the external layer required a considerably wider clearance than the inner layer. Finally,
m was selected as 5 based on (8), and
wo was selected as 3.1 mm so that the 5 segments with 0.625 mm of
d could be applied to an 18 mm conductor.
In the top layer,
Cdec and the input voltage
Vin plane exist, and
IC2Q and
IQ2C flow upward, as shown in
Figure 7a.
Figure 7b shows the PCB layout and current flow of inner layer 1. In inner layer 1, the output voltage
Vout plane exists, and
IQ2Q flows downward during the switching transients. Therefore, magnetic fluxes generated in the top and inner layers 1 cancel each other. Furthermore,
IC2Q and
IQ2C in the top and inner layer 2 flow through the vias into the segments, which results in horizontal magnetic flux cancellation. In inner layer 2, the
Vin plane exists and
IC2Q and
IQ2C flow upward, similar to the top layer, which results in vertical flux cancellation with inner layer 1, as shown in
Figure 7c.
Segments were also added to generate horizontal flux cancellation, as in
Figure 7b. Finally,
Q1 and
Q2 were mounted on the bottom layer, and
IQ2Q flowed to generate a vertical flux cancellation with inner layer 1. As explained in the design procedure, the parasitic inductance can be reduced further if inner layers 1 and 2 are set as reference layers and stacked between the top and bottom layers.
Table 3 presents a comparison of the parasitic inductance between the conventional [
21] and proposed structures. The conventional structure was applied to a four-layer PCB, as shown in the proposed structure in
Figure 7, and only the vertical magnetic flux cancellation was considered. As summarized in
Table 3, the total parasitic inductance
Ltot of the proposed structure was reduced by 24% to 8.26 nH compared to 10.85 nH.
4. Performance Verification
Figure 8 shows the prototype designed to validate the performance of the proposed structure.
Cdec exists in the top layer,
Q1 and
Q2 exist in the bottom layer, and segments for the 3-D lattice structure exist in inner layers 1 and 2.
Figure 9 shows a circuit diagram and photograph of the experimental setup. A double-pulse test was performed to verify improvements in switching characteristics: the drain-source voltage
VDS was measured using a LeCroy PP018 passive probe, and the drain current
ID was measured with a Rogowski coil CWT-UM3/B/1/80. The system parameters are listed in
Table 4.
Figure 10 shows the drain-source voltage and drain current of
Q2 during the turn-off transient. In the prototype with a conventional structure [
21],
VDS increases up to 380 V and
ID shows a fluctuation range from 43 A to −20 A, as indicated in
Figure 10a.
Figure 10b shows the turn-off transient waveforms of the proposed structure. Compared with the conventional structure, the overshoot of
VDS decreased to 359 V, and the maximum and minimum magnitude of
ID decreased to 38 A and −13.5 A, respectively. The experimental results in
Figure 10 indicate that the overshoot of
VDS is reduced by approximately 5.5%, and the fluctuation of
ID is reduced by approximately 18% with the proposed structure, meaning that the parasitic inductance is effectively reduced.
Figure 11 shows the drain-source voltage and drain current of
Q2 during the turn-on transient. The maximum magnitude of
ID decreased by 10% from 34 A to 31 A, and the minimum magnitude decreased by 35% from –10.6 A to –6.8 A with the proposed structure, as shown in
Figure 11.
Improving switching characteristics by reducing parasitic inductance can increase the efficiency of a power converter as it reduces the switching energy.
Figure 12 shows a comparison of the switching energy for a conventional vertical lattice structure and that for the proposed structure, depending on the magnitude of
ID. The proposed structure has lower turn-on and turn-off switching energies than those of the conventional structure; the turn-on energy is reduced by approximately 10% and the turn-off energy by approximately 14%.
Figure 13 shows that the normalized switching energy depends on the inductance reduction method. The switching energy without inductance reduction was used as a reference for normalization. The proposed structure reduces the total switching energy by more than 10% compared to the conventional structure [
21], and therefore, the switching energy is reduced by 26% compared to the case without an inductance reduction method.
These experimental results confirm that the proposed structure can improve the stability and efficiency of WBG power semiconductors by reducing parasitic inductance without additional devices or control schemes.
5. Conclusions
A 3-D lattice structure was proposed to reduce parasitic inductance. The proposed 3-D lattice structure generated vertical magnetic flux cancellation by placing adjacent layers in opposite current directions, and the segments were inserted to generate the horizontal magnetic flux cancellation within a layer. A pair of layers, in which vertical and horizontal flux cancellations occur simultaneously, was selected as the reference layer and stacked repeatedly to maximize inductance reduction. Based on the simulation analysis, parasitic inductance was reduced by 55.8% with the proposed 3-D lattice structure. The design example demonstrated the selection of the segment parameters and application of the proposed structure to a practical PCB layout. The experimental results showed that the proposed structure improved switching characteristics, such as the overshoot and ringing of the drain-source voltage and drain current. The switching energy was reduced by 26% with the proposed structure compared to that without the inductance reduction method.
The proposed 3-D lattice structure demonstrates a significant reduction in parasitic inductance through a PCB layout design, making it applicable to WBG power semiconductor-based converters regardless of the package type of the switching devices. This allows for effective mitigation of the ringing and overshoots caused by the fast-switching speed of WBG power semiconductors, addressing the limitations of these devices and enabling high efficiency and power density operating with improved stability. However, it should be noted that the proposed structure may have limitations in higher power levels due to clearance and temperature rise considerations, resulting in reduced effectiveness in reducing inductance compared to lower power levels. Therefore, for a more universal inductance reduction method, further research on PCB layout structures that are not limited by power level should be explored.