Impact of Pre-Annealed ZrO₂ Interfacial Layer on the Ferroelectric Behavior of Hf_0.5Zr_0.5O₂

Abstract

This work systematically investigates the impact of a pre-annealed ZrO₂ interfacial layer on the ferroelectric behavior of Hf_0.5Zr0.₅O₂ (HZO) capacitors. The remanent polarization (2Pr) value of HZO capacitors, including configurations such as W/HZO/TiN/p⁺ Si, W/HZO/(pre-annealed) ZrO₂/TiN/p⁺ Si, W/HZO/SiO₂/TiN/p⁺ Si, and W/HZO/SiO₂/p⁺ Si, exhibits significant variations. The W/HZO/(pre-annealed) ZrO₂/TiN/p⁺ Si capacitor demonstrates superior ferroelectric performance, with a 2Pr value of ~32 µC/cm². Furthermore, by optimizing the thickness combination of HZO and the pre-annealed ZrO₂ interfacial layer, a capacitor with a 10 nm HZO and 2 nm ZrO₂ achieves the largest 2Pr value. The pre-annealing process applied to ZrO₂ is found to play a very important role in inducing the orthorhombic phase and thus enhancing ferroelectricity. This enhancement is attributed to the pre-annealed 2 nm ZrO₂ interfacial layer acting as a structural guide for the subsequent HZO orthorhombic phase, thereby improving the ferroelectric performance of HZO capacitors. These findings provide a comprehensive explanation and experimental verification of the impact of pre-annealed ZrO₂ on ferroelectric devices, offering novel insights for the optimization of ferroelectric properties.

1. Introduction

Since the discovery of ferroelectricity in HfO₂-based thin films in 2011 [1], HfO₂-based ferroelectric devices have attracted considerable attention due to their advantages over traditional perovskite materials, including low power consumption, high scalability, and excellent compatibility with standard semiconductor manufacturing processes [2,3,4]. One effective strategy to stabilize ferroelectricity and enhance device performance involves the introduction of various doping elements, such as Si, Zr, Al, Y, La, Sr, and Gd [5,6,7,8,9,10]. The ferroelectric property observed in HfO₂-doped films is attributed the non-centrosymmetric orthorhombic phase (o-phase, space group: Pca21) formation [11,12,13]. Theoretically, this phase is predicted to arise from the imposition of significant mechanical stress. Extensive research has been conducted to induce the o-phase and enhance ferroelectricity, including the use of in-plane strain through methods such as a metallic capping layer, typically TiN [14] but also including other metal materials, as well as semiconductor substrates [15,16,17]. However, stacking HZO on a metal electrode, while not a conventional focus, imposes limitations in its applications, particularly in metal–oxide–semiconductor (MOS) devices. Achieving ferroelectric HZO on a semiconductor substrate is still a significant challenge, especially on an Si substrate (for example, FeFETs) [18]. Recent studies have highlighted the potential of ZrO₂ interfacial layers on either TiN or on Si substrates, demonstrating their ability to enhance ferroelectric characteristics in HZO [19,20,21,22,23,24]. In these investigations, a 300 °C atomic layer deposition (ALD) process was employed to form a crystallized ZrO₂ layer, serving as a bottom nucleation layer that facilitates the formation of the o-phase in HZO. However, the concept of utilizing a pre-annealing treatment to enhance the crystallization of ZrO₂, subsequently promoting the ferroelectricity of HZO, has not been explored, despite its importance.

In this paper, a systematic investigation on the influence of pre-annealed ZrO₂ on HZO ferroelectric thin films is reported. By forming (pre-annealed) ZrO₂/TiN/p⁺ Si, SiO₂/TiN/p⁺ Si, and SiO₂/p⁺ Si structures, we identify the maximum 2Pr value. Moreover, an optimal combination of ZrO₂ and HZO layer thickness reveals the largest 2Pr value. The pre-annealed ZrO₂ layer is found to inhibit the monoclinic phase (m-phase) and enhance the o-phase. This discovery provides a robust explanation for the impact of the pre-annealed ZrO₂ layer on the ferroelectric behavior of HZO, with significant implications for optimizing high-performance ferroelectric devices.

2. Materials and Methods

The whole fabrication process and schematic figures of different HZO ferroelectric capacitors are illustrated in Figure 1a–e. Beginning with a p-type heavily doped Si wafer (R: 0.001–0.005 Ω·cm), a wet chemical cleaning procedure is conducted to eliminate organic contamination before a 10 nm thick TiN bottom electrode is prepared through ALD. The gate-stack process involves the sequential deposition of either 1~4 nm ZrO₂ via ALD at 250 °C, utilizing (C₅H₅)Zr[N(CH₃)₂]₃ and O₃ gas as precursor (Figure 1c), or 2 nm SiO₂ via plasma-enhanced chemical vapor deposition (PECVD) at 250 °C, using a SiH₄ precursor and N₂O gas (Figure 1d). The choice between ZrO₂ and SiO₂ deposition depends on the desired interfacial layer composition for different HZO capacitors. Subsequently, the layer undergoes a pre-annealing treatment at 400 °C for 1 min in a nitrogen atmosphere before the deposition of the ferroelectric layer. A 10 nm HZO layer with a Hf:Zr ratio of 1:1 is introduced through ALD at 250 °C using a (Hf/Zr)[N(C₂H₅)CH₃]₄ (Hf:Zr = 1:1) cocktail precursor and O₃ gas. Finally, a 30 nm W top electrode is capped on the ferroelectric film through DC sputtering, and a mesa structure is formed via wet etching. After the formation of the Al back electrode through thermal evaporation, post-deposition annealing (PDA) is carried out at 500 °C for 1 min in a nitrogen atmosphere, as shown in Figure 1a. Similarly, reference samples without an interfacial layer (Figure 1b) and those using a heavily doped p-type substrate (Figure 1e) to replace the bottom electrode are also prepared for better comparison.

The crystal phase structures of the ferroelectric layers are analyzed using grazing incidence X-ray diffraction (GIXRD) with an incident angle of 0.5° and a 2θ range of 25°–40°, and with a scanning step of 1°/1 min to achieve higher resolution. High-resolution transmission electron microscopy (HRTEM), coupled with energy-dispersive spectrometry (EDS), is employed for the comprehensive examination of cross-sectional microstructures, morphology, and element mapping distribution, particularly at the interface of ZrO₂ interfacial layers. For characterizing ferroelectric behavior, polarization-electric field (P-E) measurements are carried out using a Positive-Up–Negative-Down (PUND) method with a pulse with a top width of 100 ns and a rising/falling time of 10 μs. Electrical measurements are carried out with a high-precision semiconductor device (Agilent B1500A, Agilent Technologies, Santa Clara, CA, USA). During the electrical measurement, the bottom electrode of the samples is connected to the ground terminal or virtual ground terminal of the instruments.

3. Results

The dependence of the electric field and remanent polarization of HZO capacitors on different structural configuration is shown in Figure 2a. Notably, the W/HZO/(pre-annealed) ZrO₂/TiN/p⁺ Si capacitor exhibits the largest remanent polarization (2Pr of 32 µC/cm²), highlighting the advantageous role of the ZrO₂ interfacial layer in ferroelectric devices. Interestingly, the capacitor with a 2 nm SiO₂ layer on the TiN bottom electrode demonstrates a similar Pr compared with W/HZO/TiN/p⁺ Si under the same electric field. Furthermore, the hysteresis curve of the W/HZO/SiO₂/p⁺ Si capacitor presents the lowest, as well as an asymmetric, loop, which is due to electrode asymmetry. The top and bottom electrode materials (W and p⁺ Si) have different work functions, which leads to different barrier heights at the interfaces, resulting in different leakage currents under positive and negative bias. It is worth mentioning that all P-E curves were obtained from devices in their pristine state.

In Figure 2b, the endurance measurement results for HZO capacitors described in Figure 2a are presented. Notably, the insertion of the 2 nm ZrO₂ interfacial layer results in a significant increase in the 2Pr value of the HZO capacitor. Moreover, the larger 2Pr value remains almost constant during the cycling test until a hard breakdown around 10⁷ cycles, indicating superior endurance properties compared with the W/HZO/TiN/p⁺ Si capacitor and W/HZO/SiO₂/TiN/p⁺ Si capacitor. Both samples exhibit an earlier breakdown, particularly for the W/HZO/SiO₂/TiN/p⁺ Si capacitor, probably because the 2 nm PECVD SiO₂ layer cannot form a crystallized structure at 400 °C, and this amorphous structure deteriorates the ferroelectric behavior. The W/HZO/SiO₂/p⁺ Si capacitor shows a similar tendency, consistent with the findings reported by Toprasertpong [25]. The discernible reduction in endurance is attributed to the differences in the ferroelectric phase crystallization caused by the distinct boundary conditions of HZO during annealing.

The W/HZO/(pre-annealed) ZrO₂/TiN/p⁺ Si capacitor exhibits superior ferroelectric performance compared to configurations with a SiO₂ interfacial layer, a TiN electrode, and a p⁺ Si substrate. The poor ferroelectricity of the capacitor on the p⁺ Si substrate is ascribed to the native SiO₂ layer (~1.7 nm) formed on the surface during the HZO ALD process, acting as a barrier that inhibits ferroelectric switching, which will also lead to a relative high gate leakage current with ultrathin equivalent oxide thickness (EOT). The asymmetric hysteresis loop in the positive and negative directions is due to the different electrode materials in terms of the work function of the p⁺ Si bottom electrode and the W top electrode. As is well known, the absence of an interfacial layer is of vital importance for good ferroelectric function, due to the fact that the interfacial layer acts as the barrier which inhibits ferroelectric switching [26]. Interestingly, the capacitor with the TiN electrode, lacking an interfacial layer, exhibits remanent polarization smaller than that with a ZrO₂ interfacial layer. To unravel this phenomenon and unveil the mechanism, a comprehensive investigation was undertaken.

To investigate the effect of a pre-annealed ZrO₂ interfacial layer on the ferroelectricity of HZO capacitors, various conditions were established. Initially, a fixed 2 nm pre-annealed ZrO₂ interlayer was prepared in advance. By varying the HZO thickness from 5 to 15 nm, interesting behavior of the Pr values was observed, as shown in Figure 3a,c. The maximum 2Pr is achieved with a 10 nm HZO sample, and either increasing or decreasing the HZO thickness deteriorates the ferroelectric behavior. This is likely because 5 nm is too thin to achieve optimal ferroelectric properties, while HZO layers thicker than 10 nm result in an increased phase intensity of the peak associated with the paraelectric m-phase in the HZO films. Figure 3b depicts the influence of the ZrO₂ interlayer thickness on the P-E characteristics. All the samples show well-saturated P-E hysteresis loops. The Pr values do not monotonously increase or decrease with the thickness of the ZrO₂ layer. The samples with 1 nm and 2 nm interfacial layers induce a higher Pr value for the HZO film than those with thicker (3 nm and 4 nm) ZrO₂ interfacial layers, as shown in Figure 3d. This is due to thicker ZrO₂ layers exhibiting more antiferroelectric behavior, which could suppress the ferroelectric properties of the HZO layer. However, the 2 nm ZrO₂ sample shows a higher Pr value than the 1 nm sample, likely because 1 nm ZrO₂ cannot form a crystallized structure that supports the o-phase growth of HZO. Neither too-thick nor too-thin ZrO₂ layers are favorable for achieving a large Pr value.

An optimal HZO thickness versus the pre-annealed ZrO₂ thickness was experimentally obtained, which demonstrates superior ferroelectric properties over previous reports. In this study, a pre-annealing treatment was conducted on the ZrO₂ interfacial layer before HZO deposition and subsequent HZO crystallization. To understand the impact of the annealing process on the ZrO₂ interfacial layer, remanent polarization, microstructure composition, and interface morphology were investigated for W/HZO/(as-deposited) ZrO₂/TiN/p⁺ Si and W/HZO/(pre-annealed) ZrO₂/TiN/p⁺ Si capacitors, respectively.

The effect of pre-annealing treatment on the ZrO₂ interfacial layer of the HZO capacitor’s remanent polarization is shown in Figure 4a. The W/HZO/(pre-annealed) ZrO₂/TiN/p⁺ Si capacitor exhibits significantly larger remanent polarization, highlighting the advantage of using a pre-annealed ZrO₂ interfacial layer for HZO ferroelectric devices. The GIXRD patterns of capacitors deposited on TiN, as-deposited ZrO₂, and pre-annealed ZrO₂ layers are characterized, as shown in Figure 4b. For samples on the as-deposited ZrO₂ and TiN, a part of the m-phase is observed, while the m-phase disappeared on annealed ZrO₂. Moreover, the center of the (111)o/t peak for the as-deposited ZrO₂ also shows a mismatch compared with the reference sample and the annealed ZrO₂, potentially causing a decrease in ferroelectric behavior. Figure 4c shows cross-sectional TEM images of W/HZO/(as-deposited) ZrO₂/TiN/p⁺ Si and W/HZO/(pre-annealed) ZrO₂/TiN/p⁺ Si capacitors, respectively. For the W/HZO/(as-deposited) ZrO₂/TiN/p⁺ Si capacitor, there is a sharp interface between the HZO and ZrO₂ layers due to the limited reaction and diffusion during the PDA process (see Figure 4c) for the ferroelectricity of the HZO layer. The as-deposited ZrO₂ layer had an amorphous structure after the ALD process at 250 °C, and the following HZO layer was grown on this amorphous structure. During the subsequent annealing process, the as-grown ZrO₂ may not provide enough capping strength. On the other hand, the HZO ferroelectric grains were crystallized in the same orientation along with the underlying pre-annealed ZrO₂ grains, as shown in Figure 4c. This is likely due to the crystalline ZrO₂ grains’ work as the nucleation base for the crystallization of the HZO grains during the next PDA process. It is worth mentioning that even after the PDA process, there is no intermixing of HZO and ZrO₂, as shown in Figure 4d, where the Zr element distribution outranges Hf. This indicates that the crystallization of the HZO layer was promoted by the crystallized ZrO₂ layer. Based on these findings, a schematic view of the working principal can be illustrated. The pre-annealing treatment enhances the bottom ZrO₂ crystalline structure (Zr atoms in green), as marked by the red box (Figure 4e). The improvement in ZrO₂ surface’s crystallinity introduces alterations in the atomic arrangement and lattice parameter constants, which modifies the surface energy consequently and thereby affects the phase composition. In comparison, poor ZrO₂ crystallinity leads to random directional growth of the following HZO (Figure 4f), forming a polycrystalline layer that exhibits ferroelectric behavior. However, the mechanism of the phase transition driven by the surface energy has not been clearly investigated before. Developing a comprehensive understanding requires further in-depth research.

4. Conclusions

In this work, we conducted an in-depth investigation into the ferroelectric behavior of HZO capacitors incorporating a pre-annealed ZrO₂ interfacial layer. The results reveal the profound impact of the pre-annealed ZrO₂ interfacial layer on the ferroelectric properties of HZO. Notably, the introduction of a pre-annealed interfacial layer proves to be an effective strategy for significantly enhancing the remanent polarization in ferroelectric devices. Importantly, this advantageous effect is consistently observed across various capacitor configurations, highlighting the broad applicability of the proposed approach. In summary, the pre-annealing treatment of the ZrO₂ interfacial layer offers a viable and implementable method to further optimize the behavior of ferroelectric devices. The insights gained from this study contribute valuable knowledge to the ongoing efforts in advancing the field of ferroelectric materials and their applications in the FeRAM and Fe(M)FET fields.