A New Symmetrical Source-Based DC/AC Converter with Experimental Verification

Abstract

This research paper introduces a new topology for multilevel inverters, emphasizing the reduction of harmonic distortion and the optimization of the component count. The complexity of an inverter is determined by the number of power switches, which is significantly reduced in the presented topology, as fewer switches require fewer driver circuits. In this proposed topology, a new single-phase generalized multilevel inverter is analyzed with an equal magnitude of voltage supply. A 9-level, 11-level, or 13-level symmetrical inverter with RL load is analyzed in MATLAB/Simulink 2019b and then experimentally validated using the dSPACE-1103 controller. The experimental verification of the load voltage and current with different modulation indices is also presented. The analysis of the proposed topology concludes that the total required number of components is lower than that necessary for the classical inverter topologies, as well as for some new proposed multilevel inverters that are also compared with the proposed topology in terms of gate driver circuits, power switches, and DC sources, which thereby enhances the goodness of the proposed topology. Thus, a comparison of this inverter with the other topologies validates its acceptance.

1. Introduction

In recent years, multilevel inverters (MLIs) have become a viable technology for various power conversion applications, owing to their ability to overcome the limitations associated with traditional two-level inverters. These inverters are pivotal in the realm of power electronics, offering significant advancements in power quality, efficiency, and controllability [1]. MLIs were introduced in 1975 [2] due to the need for better quality output voltage, lower electromagnetic interference, lower blocking voltages of switches, and reduced filter sizes with higher efficiency [3,4]. Multilevel inverters produce a stepped staircase waveform from various DC sources [5] and proved to be reliable converters for various power applications, for example high-voltage direct current (HVDC), AC drives, hybrid vehicles, and renewable energy system (RES) conversions [6,7]. The MLI is gaining popularity due to its increasing industrial applications in effective power generation using renewable energy. The size of the filter required for an MLI is small, as the MLI produces higher-quality output voltages that are nearly sinusoidal with less harmonic content. Nevertheless, the classical MLIs have nowadays been overcome by new configured reduced-switch multilevel inverters. Generally, MLIs are divided into three groups known as cascaded H-bridge (CHB), flying-capacitor (FC), and neutral-point clamped (NPC) MLIs, which were first presented in 1996, 1990, and 1981, respectively [8,9,10,11,12]. The cascaded H-bridge MLI, introduced in 1996, marked a significant milestone in multilevel inverter technology. This topology employs multiple H-bridge converter cells connected in series, enabling the synthesis of high-quality sinusoidal waveforms with minimal harmonic content. Its modular structure facilitates scalability and allows for fault tolerance, making it a preferred choice for medium- to high-power applications [11]. Topologies such as the diode-clamped and capacitor-clamped multilevel inverters have gained prominence for their simplicity, reliability, and ease of control. By distributing the voltage levels symmetrically across multiple power semiconductor devices, symmetrical multilevel inverters achieve superior voltage waveform quality and reduced switching stress on individual devices, thereby enhancing system robustness and longevity. As the number of voltage levels increases in a multilevel inverter, the quality of the output voltage improves. However, this improvement is accompanied by challenges related to the increased complexity of the MLI and its associated financial implications. Therefore, increasing the voltage levels (phase voltage) with the least or optimized number of overall components is nowadays a hot topic of research worldwide. On the other hand, asymmetrical MLIs have emerged as a compelling alternative, particularly in applications requiring precise voltage control, reduced component count, and increased voltage levels. Unlike their symmetrical counterparts, asymmetrical multilevel inverters feature non-identical voltage levels across each phase, achieved through varying the DC voltage sources or the capacitor values [13]. This flexibility allows for greater customization of the voltage levels to match specific application requirements, thereby optimizing system performance and efficiency. The CHB MLIs are configured as symmetrical and asymmetrical, depending on the value of equal magnitude and unequal magnitude of the DC sources. Symmetrical MLIs, characterized by their balanced voltage levels across each phase, have been widely studied and implemented in various high-power applications. However, in the past two decades, many researchers noticed mixed reactions about the advantages and disadvantages of the three above-mentioned MLIs [14]. Therefore, various researchers started to design new MLI topologies with a reduced number of switches [15,16,17]. The larger number of the output voltage levels with lower components has been proposed for both symmetrical and asymmetrical MLIs [18,19]. Several control modulation techniques, such as selective harmonic elimination (SHE), space vector pulse-width modulation (SVPWM), carrier-based pulse-width modulation, and nearest level control (NLC), have been adopted [20,21,22,23].

In this paper, two symmetrical circuit topologies, i.e., circuit−I and circuit−II, are proposed. This paper is structured into distinct sections. In Section 2, the two circuit topologies named circuit−I and circuit−II are proposed. Both circuits are capable of achieving a minimum of nine voltage levels. However, these circuits can also be employed to generate output voltage levels beyond nine. For the generation of a 9-level output voltage, the topological structure remains the same for both circuits (I and II). However, for output voltage levels other than nine, the two proposed topologies operate differently, as described in Section 2. Section 3 deals with the switching pulses and the operational modes of the proposed MLI. Following this, in Section 4, a comparative analysis is incorporated with various existing recent MLI topologies. In Section 5, comprehensive coverage is provided regarding the parameters of different components, the simulation results, and the hardware results. To verify the proposed design, the circuit is tested via MATLAB/Simulink R2019b, and the results are well described to depict the performance of the proposed circuit. Finally, Section 6 introduces a conclusion summarizing the key findings and implications of this research on MLIs.

2. Proposed Reduced-Switch Topology

In this section, both proposed circuit topologies (I and II) are described. Their extendable generalized topologies are thoroughly described in Section 2.1 and Section 2.2, whereas different modes of operation are clearly explained in Section 3, proposing two topologies in circuit−I and circuit−II. It is evident that the desirable extension of the topologies (I and II) can be achieved as per the required voltage levels. Whereas the number of components needed to produce the voltage levels is the same in both circuits (I and II), the number of bi-directional switches required in circuit−II is larger, resulting in higher conduction losses at higher voltage levels.

2.1. Circuit Operation of the Proposed Circuit−I

The proposed circuit−I is depicted in Figure 1a. First of all, the proposed topology consists of nine switches, generating nine level. The switches used are bi-directional and unidirectional. Bi-directional switches are employed for the flow of current in either direction. The unidirectional switches are $S_1,S_4,S_5,S_6,S_7, \mathrm{and} S$ whereas $S_2$, $S_3$, and $S_9$ are the bi-directional switches employed in the circuit. An H-bridge is employed for polarity generation, which contains four switches; in contrast, the rest of the circuit is used for level generation and contains five switches, as shown in Figure 1a. The MLI being symmetrical in nature, all the voltage magnitudes of the proposed MLI are the same. Therefore, a 9-level stepped output voltage can be generated only from one DC source. In Figure 1b, a generalized configuration of the proposed circuit is shown. It can be noticed that by adding only one bi-directional switch along with a capacitor, the attainment of the subsequent higher-voltage level is feasible. The minimum number of voltage levels achieved is nine when four capacitors of equal magnitudes and eight power switches are used. It can be noticed that by adding only one bi-directional switch along with a capacitor, the next higher-voltage level can be achieved. The minimum number of voltage levels achieved is nine when four capacitors of magnitude $V_1,V_2,V_3,V_4=V_{\mathrm{dc}}$ and nine switches, $S_1,S_2,S_3,S_4,S_5,S_6,S_7,S_8,S_9$, are used, where the switches $S_5,S_6,S_7,S_8,S_9$ are used to generate polarity, and the switches $S_1,S_2,S_3,S_4$ are used to generate the voltage levels. Thus, the switches $S_1,S_2,S_3,S_4,S_5,S_6,S_7,S_8,S_9$ and the capacitors having magnitude $V_1,V_2,V_3,V_4=V_{\mathrm{dc}}$ remain fixed throughout the overall topological structure. The only bi-directional switches and capacitors that are added to the existing circuit for generating the next higher-voltage level are ${S^{\prime }}_1,{S^{\prime }}_2,\dots \dots \dots {S^{\prime }}_{(\mathrm{n}-1)},S_{\mathrm{n}}$ and ${V^{\prime }}_1,{V^{\prime }}_2,\dots \dots \dots {V^{\prime }}_{\left(\mathrm{n}-1\right)},V_{\mathrm{n}},$ respectively.

The addition of a bi-directional switch, ${S^{\prime }}_1$ and of a capacitor having voltage magnitude of ${V^{\prime }}_1$ generates nine voltage levels. Further, the addition of the switch ${S^{\prime }}_2$ with a capacitor next to the previous capacitor, having magnitude of ${{\mathrm{V}}^{\prime }}_2$, generates eleven levels. Moreover, a 13-level output voltage is generated by the further addition of the switch ${S^{\prime }}_3$ along with a capacitor having ${{\mathrm{V}}^{\prime }}_3$ as the voltage magnitude. Thus, to generate the desired n-level output voltage, the switch ${{\mathrm{S}}^{\prime }}_{\mathrm{n}}$ is employed with a capacitor having ${V^{\prime }}_n$ as the voltage magnitude.

2.2. Circuit Operation of the Proposed Circuit-II

The proposed circuit−II contains nine switches, as shown in Figure 2a, of which six (S₁, S₂, S₃, S₄, S_1a, S_4a) are unidirectional, and three (S_2a, S_3a, S₅) are bi-directional, with four capacitors (V_1a, V_2a, V₁, V₂). It consists of an H-bridge employing the switches S₁, S₂, S₃, S₄ that are generally used for polarity generation. As depicted in Figure 2b, cell-a, cell-b, etc., up to cell-n are enhanced as per the desired voltage levels to obtain the generalized configuration of circuit−II. There are two unidirectional and two bi-directional switches, along with two capacitors, in each cell unit, and these cells are cascaded to achieve higher levels, as depicted in Figure 2b. Thus, for generating the n^th voltage level, a cascading of cells till the nth cell is required, which contains two bi-directional switches (S_2n, S_3n), two unidirectional switches (S_1n, S_4n), and two capacitors (V_1n, V_2n). Five switches (S₁, S₂, S₃, S₄, S₅) and two capacitors (V₁, V₂) remain the same throughout the generalized proposed circuit−II.

Figure 3 shows the different types of arrangements for the bi-directional flow of current, depicted as (Figure 3a) Common Emitter IGBT, (Figure 3b) Diode Bridge with one Power Switch and (Figure 3c) Common Collector IGBT respectively. Considering the conduction loss point of view, the arrangements in Figure 3a,c seem to be better options than that in Figure 3b, as both of them contain only two diodes, whereas the configuration shown in Figure 3b has four diodes. When it comes to economic cost considerations, the arrangements in Figure 3a,c appear better than that in Figure 3b, as two driver circuits are needed to drive the bi-directional configuration shown in Figure 3c. Thus, taking the two parameters into account, the configuration depicted in Figure 3a, which ensures less conduction losses at an economical cost, is the better option and was chosen to be developed for the prototype model, employing one driver circuit with less conduction losses.

The various ways of providing a DC supply to capacitors are depicted in Figure 4a–c and 4d, respectively, where V_n is the n^th voltage required to generate the n^th output voltage levels.

There are four ways to provide DC voltages with the same magnitudes to capacitors, as follows:

• One DC supply with DC/DC converters is employed for the required capacitors.
• One AC supply is fed to the transformer primary side, with isolated multi-windings on the secondary side, then connected to a bridge rectifier, and fed to the required capacitors.
• Every photovoltaic module is connected with DC/DC converters for the required capacitors.
• Photovoltaic modules connected in series with DC/DC converters are employed for the required capacitors.

3. Modes of Operation

Various modes of operation in both the negative as well as the positive half cycle of the proposed 9-level circuit for circuit−I are depicted in Figure 5. It could be clearly noticed from the proposed topology depicted in Figure 1a and Figure 2a that the nomenclature of the components is only changed for the proposed inverter at the first stage, and therefore, the same components with different names (for circuit−I and circuit−II) generate different modes of voltage level.

The switching states of both the proposed circuit−I and circuit−II inverters are depicted in

Table 1. Switching states of the proposed 9-level inverter.

Modes	Switching States 1 = ON; 0 = OFF									Circuit−I Voltages	Circuit−II Voltages	Stepped Output Voltage Generation
Circuit−I	$S_1$	$S_2$	$S_3$	$S_4$	$S_5$	$S_6$	$S_7$	$S_8$	$S_9$	$V_1=V_2=V_{dc}$ $V_3=V_4=V_{dc}$	$V_{1a}=V_{2a}=V_{dc}$ $V_1=V_2=V_{dc}$
Circuit−II	$S_{1a}$	$S_{2a}$	$S_{3a}$	$S_{4a}$	$S_1$	$S_4$	$S_3$	$S_2$	$S_5$
Mode-1	1	0	0	1	1	0	0	1	0	$V_1+V_2+V_3+V_4$	$V_{1a}+V_{2a}+V_1+V_2$	$+4V_{dc}$
Mode-2	1	0	1	0	1	0	0	1	0	$V_1+V_3+V_4$	$V_{1a}+V_1+V_2$	$+3V_{dc}$
Mode-3	0	1	0	1	1	0	0	1	0	$V_3+V_4$	$V_1+V_2$	$+2V_{dc}$
Mode-4	0	0	0	0	0	0	0	1	1	$V_4$	$V_2$	$+V_{dc}$
Mode-5	0	0	0	0	1	0	1	0	0	---	---	$+0V_{dc}$
	0	0	0	0	0	1	0	1	0	---	---	$+0V_{dc}$
Mode-6	0	1	0	1	0	0	1	0	1	$V_3$	$V_1$	$-V_{dc}$
Mode-7	0	1	0	1	0	1	1	0	0	$V_3+V_4$	$V_1+V_2$	$-2V_{dc}$
Mode-8	1	0	0	1	0	0	1	0	1	$V_1+V_2+V_3$	$V_{1a}+V_{2a}+V_1$	$-3V_{dc}$
Mode-9	1	0	0	1	0	1	1	0	0	$V_1+V_2+V_3+V_4$	$V_{1a}+V_{2a}+V_1+V_2$	$-4V_{dc}$

. One output voltage level is generated by each mode. For different modes of operation, the current paths were made thicker. Only four positive cycles, i.e., Mode-1, Mode-2, Mode-3, and Mode-4, generate +4V_dc, +3V_dc, +2V_dc, and +V_dc, respectively, whereas four negative cycles, i.e., Mode-6 (−V_dc), Mode-7 (−2V_dc), Mode-8 (−3V_dc), and Mode-9 (−4V_dc), produce four negative voltage output and are shown in Figure 5; the exception is Mode-5, with zero cycles.

The pulse patterns generated using the dSPACE1103 controller by a carrier-based level-shifted PWM provided to the switches for the proposed 9-level MLI (for circuit−I and circuit−II) are depicted in Figure 6. This technique involves modulating the widths of the pulse signals based on a carrier wave and the desired output voltage levels, ensuring the efficient control of the semiconductor switches to attain the required voltage output.

4. Comparison with other MLI Topologies

In this section, several MLIs, including some recently proposed symmetric inverter topologies, are contrasted with the proposed topology. The generalized formulae for different topologies proposed in [24,25,26,27,28,29,30] are shown in

Table 2. Comparison chart of the generalized formulations.

MLI Compared with the Proposed Topology	Total Switches (M)	Gate Driver Circuit (N)	Capacitors/Isolated DC Sources (O)	Main Diodes (P)	Switches
					Unidirectional Switches (Q)	Bi-Directional Switches (R)
[24]	$2(N_L-1)$	$2(N_L-1)$	$\frac{(N_L-1)}{2}$	$2(N_L-1)$	$2(N_L-1)$	---
[25]	$\frac{3(N_L-1)}{2}$	$\frac{3(N_L-1)}{2}$	$\frac{(N_L-1)}{2}$	$\frac{3(N_L-1)}{2}$	$\frac{3(N_L-1)}{2}$	---
[26]	$2(N_L-1)$	$2(N_L-1)$	$\frac{(N_L-1)}{2}$	$2(N_L-1)$	$2(N_L-1)$	---
[27]	$(N_L+3)$	$(N_L+3)$	$\frac{(N_L-1)}{2}$	$(N_L+3)$	$(N_L+3)$	---
[28]	$7(N_L-1)/8$	$7(N_L-1)/8$	$\frac{(N_L-1)}{2}$	$\frac{(N_L-1)}{8}$	$\frac{(N_L-1)}{8}$	$3\frac{(N_L-1)}{4}$
[29]	$N_L+1$	$N_L+1$	$\frac{(N_L-1)}{2}$	$N_L+1$	$N_L+1$	---
[30]	$(N_L+5)/2$	$(N_L+5)/2$	$\frac{(N_L-1)}{2}$	4	4	$(N_L-3)/2$
Proposed Circuit−I Topology	$\frac{(N_L+9)}{2}$	$\frac{(N_L+9)}{2}$	$\frac{(N_L-1)}{2}$	$(N_L+3)$	6	$\frac{(N_L-3)}{2}$
Proposed Circuit−II Topology	$N_L$	$N_L$	$\frac{(N_L-1)}{2}$	$\frac{3(N_L-1)}{2}$	$\frac{(N_L+3)}{2}$	$\frac{(N_L-3)}{2}$

for various parameters such as total switches (M), gate driver circuits (N), capacitors/isolated DC sources (O), main diodes (P), unidirectional switches (Q), and bi-directional switches (R). In addition, parameters like the peak inverse voltage (PIV) across the power switch and the total standing voltage (TSV) of the inverter are included. The output voltage levels are denoted by N_L.

The number of gate driver circuits required corresponds to the number of switches utilized, as each switch necessitates one driver circuit to generate a gate pulse. The main diodes are the ones associated with the switches. One anti-parallel diode is connected in the case of a unidirectional switches, whereas two or four diodes are associated with a bi-directional switch, as depicted in Figure 3.

Due to the aforesaid reasons, the configuration of the bi-directional switch proposed in Figure 3a was selected, and thus two diodes were considered for a bi-directional switch. The total component number was calculated based on the total number of switches, gate drivers, main diodes, and capacitors/DC used for the proposed inverter in this paper, as well as the configurations proposed [24,25,26,27,28,29,30].

All the aforementioned structures are shown in Figure 7. The MLI described in [24], requires two switches and a voltage source to achieve a level, which is then added in series to generate both positive and negative voltage levels with the use of an H-bridge. The configuration in [25] shows a single module with six switches and two DC sources that were used to generate the following voltage levels. In [26], a reduced-switch MLI with the optimal use of a DC link space is presented, where four switches and a DC source are required to produce the next level. As suggested in [27], two DC sources and four power semiconductor switches are combined to provide the subsequent voltage level. The MLIs proposed in [28,29,30] use several bi-directional switches, capacitors, and DC sources. In this paper, circuit−I generates the next voltage level through the addition of four switches with two DC sources. The proposed circuit−I and circuit−II generate higher-voltage levels using lesser power semiconductor switches in comparison with recent reduced-switch topologies [24,25,26,27,28,29,30].

The proposed topology (circuit−I and circuit−II) with a 9-level output, as detailed in

Table 3. Comparison of the proposed inverter with recent topologies.

Cited Papers	Voltage Levels ${\mathit{N}}_{\mathit{L}}$	Total Switches (M)	Capacitors/Isolated DC Sources (O)	PIV (Peak Inverse Voltage)	TSV (Total Standing Voltage)
[24]	9	16	4	4 Vdc	24 Vdc
[25]	9	12	4	Vdc	12 Vdc
[26]	9	16	4	3 Vdc	24 Vdc
[27]	9	12	4	Vdc	12 Vdc
[28]	9	7	4	2 Vdc	13 Vdc
[29]	9	10	4	4 Vdc	16 Vdc
[30]	9	7	4	3 Vdc	20 Vdc
Circuit−I and Circuit−II Topology	9	9	4	4 Vdc	24 Vdc

, was thoroughly studied and compared with recently proposed topologies [24,25,26,27,28,29,30]. For the inverters proposed in [24,26], the required number of driving circuits and power switches was 16, 12, and 16, respectively, which was reduced to 9 switches (6 unidirectional and 3 bi-directional) in the proposed MLI topology. Comparing the proposed topology with the inverter introduced in [24,25,26,27], reductions in both power switches and driver circuits are observed. Due to the decrease in the number of power switches, the proposed topology is easier to construct, simpler to control, and more reliable.

For all the considered parameters (M, N, O, P, Q, R), a graph was created comparing the topologies in [24,25,26,27,28,29,30] with the proposed topology, i.e., circuit−I and circuit−II, as depicted in Figure 8a. The graph evidently illustrates that the as the voltage levels increase, proposed topology requires fewer switches to achieve a voltage level, compared to the suggested MLIs in [24,25,26,27,28,29,30]. A new parameter known as the level-to-switch ratio (L/S ratio) was introduced to showcase the efficiency of the proposed MLI. The L/S ratio (phase voltage) denotes the required number of switches per output voltage level. The L/S ratio for a 13-level inverter is depicted in Figure 8b and was computed using Table 2. For an inverter, a higher L/S ratio is considered favorable, as higher levels of voltage can be achieved with the optimal number of or fewer switches. The magnitude of the L/S ratio for the proposed circuit−I (C-I) and circuit−II (C-II) are 1.18 and 1, respectively, and was much better than that of the inverters proposed in [24,25,26,27,28,29,30].

The TSV of the proposed MLI is relatively elevated, as illustrated in Table 3. However, the cost of the inverter is determined not solely by the TSV, but also by the PIV of each power switch. In spite of having a comparatively higher TSV, the inverter can be made economical by designing the inverter or selecting the components of the inverter in a hybrid model. The hybrid model of inverter implies that higher-rated power switches should be selected as the switches having a higher PIV, whereas lower-rated power switches should be selected as the switches having a lower PIV.

It should also be noted that only one PV source or one DC source is required for the suggested MLI topology. Considering the power switches, the proposed MLI requires only nine power switches (6 unidirectional and 3 bi-directional). Thus, a high TSV would not always have a negative impact on an inverter, especially when the MLI uses an H-bridge to generate polarity. These inverters, which create polarity via an H-bridge, have a positive impact on high-voltage applications. The proposed inverter is modular in structure and can also be cascaded in a modular fashion to achieve higher voltage, whereas inverters with self-polarity generation capability have a restricted application to a limited range of voltage levels or to higher voltages.

5. Simulation and Experimental Verification

A level-shifted SPWM was used to simulate the proposed topology (circuits I and II). The prototype model of the proposed MLI was developed in a laboratory utilizing a dSPACE-1103 controller. The prototype model utilizes the following components: a power switch (IGBT-CT60AM), gate driver circuits (TLP250), DSO-X 2024A, and an RL load, as shown in Figure 9.

In MLIs, the term “blocking voltage” signifies the voltage threshold that every switching component, IGBTs or MOSFETs, must endure while in the inactive state. Surpassing the threshold can trigger the semiconductor breakdown, resulting in malfunction and potentially harming the entirety of the inverter system. Therefore, selecting switching devices with appropriate voltage ratings is crucial in multilevel inverter design to ensure reliability and safe operation. The blocking voltages across switches are depicted in Figure 10. The value of the blocking voltage across the switches S₁, S₂, and S₃ are 60 V, 55 V, and 27.5 V, respectively, as shown in Figure 10a. Similarly, in Figure 10b, the blocking voltage of S₄, S₅, and S₆ are depicted as 32 V, 110 V, and 110 V, respectively. As shown in Figure 10c, the values of the blocking voltage of S₇, S₈, and S₉ are 110 V, 110 V, and −80 V, respectively.

The circuit parameters are included in

Table 4. Circuit parameters in the simulation and experimental tests and outputs at different levels.

Parameters	Name and Value or Type
Switching parameters IGBT	CT-60AM-18F: 900 V, 60 A Von, IGBT = 1.3 V, Von, Dio = 1.5 V, RDio = 0.01Ω, RIGBT = 0.11Ω, β = 3
Types of switching devices and their controlling elements	Diode driver Controller, switching frequency	MUR1560G: 600 V, 15 A TLP250: 10–35, ±1.5 A DS1103, 6 kHz
Common parameters of simulation and experimental tests	9-level inverter (same for circuit−I topology and circuit−II topologies) (V1 = V2 = V3 = V4 = Vdc = 27.5 V) R = 200 Ω, L = 150 mH, Vpk = 110.3 V, Ipk = 0.71 A.
	11-level inverter, (Circuit−I Topology) (V1 = V2 = V3 = V4 = V5 = Vdc = 30 V) R = 200 Ω, L = 100 mH, Vpk = 145 V, Ipk = 1.2 A.
	13-level inverter, (circuit−II topology) (V1 = V2 = V3 = V4 = V5 = V6 = Vdc = 21 V) R = 200 Ω, L = 100 mH, Vpk = 125.7 V, Ipk = 1.2 A.

for both simulation and experimentation. For the basic 9-level inverter, taking into account parameters such the magnitude of all four capacitors with balanced voltages V₁, V₂, V₃, V₄ = 27.5 V, R = 200 Ω, and L = 150 mH at a fundamental frequency of 50 Hz, a prototype is shown. A switching frequency of 6 kHz resulted in an output voltage of 110 V and a load current of 0.71 A. A single DC source was used along with the DC/DC converter to provide equal values of DC magnitude, as shown in Figure 4a. The driver circuit utilized for each power switch is depicted in Figure 11, with the TLP250 serving as an opto-isolator.

All the simulated results for the 9-level inverter are presented in Figure 12 for the proposed circuit topology-I and circuit topology-II. The output voltage and output current of the proposed MLI were 110.3 V and 0.71 A, respectively, as depicted in Figure 12a. Figure 12b depicts the %THD of phase output voltage which was 13.52%.

Figure 13 depicts real-time switching pulses for the nine switches used in the proposed MLI, since the suggested configuration architecture was the same (circuit−I and circuit−II). The switching pulses of three switches, i.e., (S₁, S₂, S₃); (S₄, S₅, S₆); (S₇, S₈, S₉), were grouped for 10 msec and are depicted in Figure 13a, Figure 13b, and Figure 13c, respectively. The switching pulse patterns of the switches present in circuit−II were similar to those in circuit−I, as shown in Figure 6.

The experimental results for the 9-level have been shown in Figure 14, which validate the simulation results. Figure 14a depicts the experimental result for 2.5 cycles whereas Figure 14b depicts the for 1 complete cycle.

The experimentation and simulation are performed for 11-level output using the proposed circuit-I topology. As indicated in Table 4, for V₁ = V₂ = V₃ = V₄ = V₅ = V_dc = 30 V with load values R = 200 Ω and L = 150 mH, the output voltage (peak) and output current are recorded as 145 V and 1.2 A respectively. The value of THD and the simulation output voltage are depicted in Figure 15a and corresponded to 145 V and 11.14%. For 13-level the simulation and the experimentation are performed using the proposed circuit-II topology. The simulation result for the output voltage and THD for 13-level of proposed circuit-II topology for V₁ = V₂ = V₃ = V₄ = V₅ = V₆ = V_dc = 21 V with load values R = 200 Ω and L = 100 mH have been shown in Figure 15b and corresponded to 125.7 V and 9.37% respectively.

As mentioned earlier, experimentation and simulation are conducted for both an 11-level output and a 13-level output utilizing proposed circuit-I and proposed circuit-II topologies. The experimental results for the output voltage and load current for the 11-level topology and 13-level topology are depicted in Figure 16 and Figure 17, respectively. Figure 16a depicts the output voltage and load current for 11-level MLI for 2.5 cycles whereas Figure 16b depicts the output voltage and current for different modulation index. From the experimental results illustrated in Figure 16a, it is evident that the output voltage (peak) and load current (peak) for the 11-level setup are 145 V and 1.2 A, respectively, validating the simulation results.

Similarly, the experimental results for the 13-level configuration depicted in Figure 17a gives an output voltage (peak) and load current (peak) of 125.7 V and 1.2 A, respectively, further confirming the accuracy of the simulation results. Figure 17b depicts the output voltage and current for different modulation index for 13-level at different modulation index.

6. Conclusions

This work focused on a novel symmetrical MLI topology with fewer power semiconductor switches than those normally used. Both topologies, i.e., the proposed circuit−I and circuit−II were simulated in MATLAB/Simulink R2019b environment that used three bi-directional switches along with six unidirectional switches and four capacitors to generate a nine-level output. Both the proposed circuit topologies can be used in a generalized manner to generate an output of N levels. The DC supply can be fed to the capacitors in various ways, as explained in Section 2, whereas a single DC source is used along with a DC/DC converter to provide DC supply to the capacitors employed in this topology. Moreover, a single DC source can also be employed to obtain the same topology. The experimental outputs validated the simulation results of the 9-level suggested inverter. To generate nine-level voltage, the topology remained the same for both circuits. However, for output levels greater than nine, the two proposed topologies operate differently. The THD value obtained for the 9-level voltage was 13.52%. Further experimentation and simulation were performed for an 11-level output using the proposed circuit topology−I, yielding a THD value of 11.14%. Experimental and simulation analyses were also conducted for a 13-level output employing the proposed circuit topology−II, resulting in a THD value of 9.37%. Moreover, the comparisons (in the forms of charts as well as graphs) of the proposed inverter topologies with other recent MLI topologies as well as with classical topologies are presented. In the comparative study, it was evident that the proposed topology requires fewer components compared to the other cited topologies.