Design and Analysis of a High-Gain, Low-Noise, and Low-Power Analog Front End for Electrocardiogram Acquisition in 45 nm Technology Using g_m/I_D Method

Abstract

In this work, an analog front-end (AFE) circuit for an electrocardiogram (ECG) detection system has been designed, implemented, and investigated in an industry-standard Cadence simulation framework using an advanced technology node of 45 nm. The AFE consists of an instrumentation amplifier, a Butterworth band-pass filter (with fifth-order low-pass and second-order high-pass sections), and a second-order notch filter—all are based on two-stage, Miller-compensated operational transconductance amplifiers (OTA). The OTAs have been designed employing the $g_m/I_D$ methodology. Both the pre-layout and post-layout simulation are carried out. The layout consumes an area of 0.00628 mm² without the resistors and capacitors. Analysis of various simulation results are carried out for the proposed AFE. The circuit demonstrates a post-layout bandwidth of 239 Hz, with a variable gain between 44 and 58 dB, a notch depth of −56.4 dB at 50.1 Hz, a total harmonic distortion (THD) of −59.65 dB (less than 1%), an input-referred noise spectral density of <34 $\mathsf{\mu }$Vrms/$\sqrt{\mathrm{Hz}}$ at the pass-band, a dynamic range of 52.71 dB, and a total power consumption of 10.88 μW with a supply of ±0.6 V. Hence, the AFE exhibits the promise of high-quality signal acquisition capability required for portable ECG detection systems in modern healthcare.

1. Introduction

In the last two decades, tremendous and rapid technological advancement has been observed in the world of electronics. The shrinking of feature size (i.e., channel length of a transistor) is a testament to this advancement. Although digital circuits have already been working on technology nodes (interchangeable with channel length) lower than 5 nm [1,2], their analog circuit counterparts have not advance at the same pace. For the past two decades, most analog circuits have been developed using a 180 nm node or above [3,4,5,6,7,8,9,10,11,12,13,14,15,16,17] due to some benefits enjoyed by the larger technology nodes, for example, ease of design, larger amplification, low noise, etc. However, in mixed-signal circuits, analog circuits need to be fabricated with the digital circuits on the same chip to meet various purposes [18]. One such analog circuit is an operational amplifier (OPAMP), which usually has two inputs and a single output.

OPAMPs are versatile integrated circuits (ICs) widely used in various applications, including small-signal amplification, filtering, wave generations, arithmetic operations, and analog-to-digital (ADC) and digital-to-analog (DAC) conversion. In recent years, novel OPAMP architectures have emerged [19,20,21,22,23], aiming to enhance their functionality for specific domains. One such critical domain is biomedical electronics, where OPAMPs play a crucial role [24] and serve as fundamental building blocks. In biomedical electronic circuits, OPAMPs need to address the unique features demanded by bio-potential signals (i.e., ECG, EEG, EMG), which include high amplification (as these signals are inherently weak), low noise levels (to ensure accurate signal acquisition and subsequent processing), and low power consumption. These features become indispensable for portable medical devices such as ECG monitors, where OPAMPs are commonly used for acquiring ECG signals generated by the heart [25] to enable precise monitoring and diagnosis. OPAMPs are also extensively employed in other medical platforms, including diagnostics, therapy, imaging, and instrumentation. The versatility and adaptability of OPAMPs continue to drive innovation in healthcare technology [26].

Figure 1 shows a typical block diagram of an analog front end (AFE) for an ECG acquisition system. The sensors are attached to the human body to collect the analog signal. This signal is passed to the AFE for amplification and noise removal. The processed signal is then digitized using an analog-to-digital converter. This work focuses on the blocks highlighted in the AFE figure.

In comparison with analog circuits, designing digital circuits requires less effort as the input signals are limited to only two voltage levels—logic 1 (HIGH) and logic 0 (LOW). Indeed, the digital circuit design principle utilizes the switching (ON or OFF) concept, which can be easily realized by transistors like MOSFET or BJT. However, on the other hand, analog circuits deal with continuous signals, comprising infinite voltage levels. This increases complexity in the design. Analog circuits mostly use transistors to amplify signals. Multiple transistors are used to design a circuit that can implement mathematical functions on signals, known as OPAMP. Most studies focus on the design of OPAMP in larger nodes, usually 180 nm or more. Very few studies can be found for designs of 90 nm [27] and 45 nm [28,29]. This is due to the fact that below 180 nm channel length the transistors suffer greatly from short channel effects. This effect is not accounted for in the widely used long-channel model (also known as the Ideal or Shockley model). This adds to the design complexity. However, lower technology nodes (smaller channel length) can offer great benefits in terms of performance parameters. The long-channel model, which is widely used for analog circuit design, is not very accurate for lower nodes. There are other models, such as EKV, BSIM, etc., that can better predict the transistor behavior in lower nodes, but they are too complex, as they involve too many variables and also lack a well-established design flow.

The $g_m/I_D$ method can simplify the design process for designers [30], as the $g_m/I_D$ parameter is not dependent on any model equation and is applicable in all regions of operation. For this semi-empirical approach, the necessary curves are generated directly from the simulator, which closely matches the actual measurement. In [31], the design and analysis of different OPAMP architectures are discussed, where long-channel MOSFET models are used. It is very difficult to design circuits in low-technology nodes (channel length ≤ 180 nm) using the long-channel model. The $g_m/I_D$ method explained in [30] provides various examples of designs with MATLAB scripts. The method utilizes look-up table (LUT), but it lacks the analysis of circuits to meet multiple specifications such as power, gain-bandwidth product (GBW), power supply rejection ratio (PSRR), common mode rejection ratio (CMRR), etc. Also, no specific design methodology is discussed in this work and searching values from a table can become tedious and time consuming. The work in [32] describes the use of a licensed software called ‘Analog Designer’s Toolbox’ (ADT). To use the toolbox, the user needs to provide MOSFET model parameters in written form. The integrated circuit designer’s usually have access to realistic models provided by manufacturing companies (such as TSMC). Deriving necessary parameters from these realistic models for the ADT toolbox adds more design complexity. The authors in [33] discuss the design of differential amplifier circuits using $g_m/I_D$ methodology. This work assumes some specifications. The design process involves solving a number of equations using the specifications. In solving these equations, a significant amount of the unknown variable values are required. In finding those variable values, the authors needed more characteristic curves. The work of [34] focuses on the design of CMOS telescopic OTA and [35] focuses on a down-conversion mixer. The authors only mentioned a design flow using $g_m/I_D$ but did not explain the flow. The selection of design parameters from $g_m/I_D$ curves or LUT are not demonstrated. All the cited works except [34] lack the usage of realistic MOSFET models of various technology nodes (such as 45 nm, 90 nm, 180 nm, etc., models from TSMC), resulting in inaccuracy in the design to some extent.

In this work, the characteristic curves generated from the simulator (Cadence) using a realistic MOSFET model from TSMC (45 nm) are used. ‘SPICE’ simulators can also be used to generate the curves. An efficient script that can be used to generate all the necessary curves at once is developed. This script can be used inside the simulator. A design methodology is developed that involves analysis of the selected circuit (2 stage OTA) to meet multiple specifications (Power, GBW, CMRR, PSRR, Noise, etc.) through a step-by-step design process using the $g_m/I_D$ curves and optimization approaches. The usual design flow of the $g_m/I_D$ method is modified for accurate results. In the proposed design flow, the usage of a design equations is minimized, which eliminates the determination of unknown variable values from characteristic curves. As a result, the number of necessary characteristic curves is minimized. The proposed design flow is presented through a flow chart for better understanding. Using this systematic design process flow, an OTA (interchangeable with OPAMP) in 45 nm technology node is designed, which is used to implement the various blocks—an instrumentation amplifier, a notch filter, a low-pas filter, and a high-pass filter of the proposed ECG acquisition system, as shown in Figure 2. The target performance metrics are verified through various simulations, which includes transient, ac, stability, noise, common-mode rejection ratio (CMRR), power-supply rejection ratio (PSRR), total harmonic distortion (THD), etc.

The paper is structured as follows. Section 2 presents a detailed explanation of the developed methodology, which includes analysis and design of the OTA. Design constraints and the design of the ECG acquisition system is explained in Section 3. A simple and brief review of the various types of analyses required for analog integrated circuits are mentioned in Section 4.1. Section 4.2.1 explains the schematic-level simulations of the designed OTA and compares the result with contemporary designs. ECG acquisition system simulations are shown and analyzed in Section 4.2.2. Section 4.3 presents the layout implementation and also demonstrates the post-layout simulations of both the OTA (Section 4.3.1) and the whole ECG acquisition system (Section 4.3.2). The designed AFE is compared with contemporary works in Section 4.4. Conclusions of the work are drawn in Section 5. This section includes the comparison with recent reported works.

2. Methodology

This section is divided into two sub-sections. In Section 2.1, a detailed analysis of the OTA circuit is presented and a conclusion is drawn for each MOSFET device’s required inversion region, area, and $g_m/I_D$ to meet the various specifications. In Section 2.2, the design procedure and optimization of the OTA circuit is explained, followed by the design of the AFE system.

2.1. Analysis of Circuit

There are several architectures for OTA [19,20,21,22,36]. Two-stage Miller-compensated OTA is chosen for its simplicity, robustness, and popularity [37]. This architecture can deliver high gain and output swing. Figure 3 depicts the two-stage Miller-compensated OTA circuit. In this OTA, a differential input stage ($M_1-M_2$) amplifies the input signal, and a common-source output stage ($M_6-M_7$) provides a high output impedance. A capacitor, C_c, following the Miller compensation technique, is inserted between the output and input of the second stage to ensure the stability of the proposed OTA. C_c lowers the gain at high frequencies and reduces the phase shift caused by the parasitic capacitance. The current through $M_1$, $M_3$ branch is copied into the $M_2$, $M_4$ branch through current mirror action of the $M_3$, $M_4$ load MOS pair. The signal is further amplified by the output stage formed by $M_6$, $M_7$ MOSFETs. ${\mathrm{I}}_{BIAS}$ is copied through the current mirror action of $M_8$, $M_5$ and $M_7$, $M_5$.

An OTA designed for the portable ECG system must provide low power, low noise, and high gain [38]. Low power (${\mathrm{V}}_{supply}\times$ ${\mathrm{I}}_{total}$) demands lower supply voltage and lower bias current ($I_{bias}$). Since the proposed OTA is intended to be implemented in 45 nm process technology, a bias of ±0.6 V has been chosen. To ensure lower power, a total current ≤1 $\mathsf{\mu }$A is preferable. Through specification-aware analysis of the circuit, the required inversion region can be predicted. Typically, the transistors are kept in the saturation region for amplification purpose. To maintain the MOSFET device operation in the saturation region, Equation (1) needs to be satisfied.

$$|V_{DS}|\ge |V_{GS}-V_{TH}|$$

(1)

Power spectral density of the input-referred noise (IRN) voltage of a MOSFET is given by the following equation [39],

$$\frac{\overline{v_i^2}}{\Delta f}=4kT\gamma \frac{1}{g_m},$$

(2)

and for the single-ended differential amplifier (1st stage), it can be written from [39]

$$\frac{\overline{v_i^2}}{\Delta f}\propto \frac{g_m\mathrm{of}\mathrm{load}}{g_m\mathrm{of}\mathrm{input}}=\frac{g_{m3}}{g_{m1}}.$$

(3)

Equation (2) suggests that if $g_m$ is lowered, IRN will increase. However, from [39],

$$\begin{array}{c}\hfill g_m\propto I_D,Area.\end{array}$$

(4)

Therefore, the area (WxL) of the active loads should be minimized while the area of the input drivers ($M_1,M_2,M_6$) should be maximized. A p-channel MOSFET is chosen as the input driver as it gives less flicker noise compared to its counterpart n-channel device [40]. For lower power, $I_D$ should be kept small so the width (W) can be increased to increase $g_m$, which results in an increase of $g_m/I_D$, hinting towards the weak or moderate inversion region of the driver MOSFETs.

Again, GBW is related to $g_m/I_D$ through Equation (5) [31]. Therefore, the high $g_m/I_D$ value required for the weak inversion region causes the GBW to drop.

$$\begin{array}{c}\hfill GBW\propto \frac{1}{g_m/I_D}\end{array}$$

(5)

According to Equation (6) [31], a higher value of $g_m/I_D$ can cause higher THD.

$$\begin{array}{c}\hfill THD\propto g_m/I_D\end{array}$$

(6)

For bio-potential signal acquisition circuits, it is important to keep the THD as low as possible to ensure linear amplification. Thus, a trade-off between noise and THD has to be made. However, for the higher gain, $g_m/I_D$ must be increased, as the parameter is related in proportion to intrinsic gain, $g_m/g_{ds}$.

From Equation (7), for a high CMRR, a high value of $g_m$ is preferred to keep a smaller current mismatch between the input drivers $M_1\mathrm{and}{M}_2$. Also, keeping the device larger reduces the mismatch and short channel effects [41].

$$CMRR\approx \frac{g_m}{\Delta g_m}(1+2g_m{R}_{ss})$$

(7)

For a higher PSRR, it is imperative to have a higher gain for the OTA, as per Equation (8) [31,39].

$$PSRR=\frac{\Delta V_{DD}}{\Delta Vout}=g_{m2}{g}_{m6}(r_{02}\left|\right|r_{04}\left)\right(r_{06}\left|\right|r_{07})$$

(8)

To realize an OTA for low power with a balanced THD, noise, gain, and CMRR and PSRR performance, a low-bias current ($I_{BIAS}$), moderate $g_m/I_D$ (moderate inversion) region for the driver MOSFETs, and strong inversion is chosen for the rest of the devices. Although weak inversion (sub-threshold region) can provide higher ${\mathrm{g}}_m$ for a given $I_D$ and hence, higher gain with lower power [42], this region is highly sensitive to the gate voltage and can limit the linearity of the device gain [43]. To reduce the channel length modulation effect, higher channel lengths for the devices are chosen.

Table 1. Summary of design requirements for individual MOSFETs of the two-stage Miller-compensated OTA.

MOSFET	Inversion Region	Area	${\mathit{g}}_{\mathit{m}}/{\mathit{I}}_{\mathit{D}}$
$M_1,M_2$	Moderate	Large	High to Medium
$M_3,M_4$	Strong	Small	Low
$M_5,M_8$	Strong	Small	Low
$M_6$	Moderate	Large	High to Medium
$M_7$	Strong	Small	Low

summarizes the necessary inversion region, area, and $g_m/I_D$ for all the devices.

The design Equations (9) and (10) [31] are used in the calculation of $g_m/I_D$ for driver MOSFETs and for choosing the $I_D$ and Cc of the circuit.

$${(g_m/I_D)}_{1,2}=4\pi GBW/SR$$

(9)

$$GBW=g_{m1,2}/C_C$$

(10)

To attain a phase margin of 60 degrees, Equations (11) and (12) from [31] are manipulated.

$$g_{m6}=10\ast g_{m2}$$

(11)

$$C_c\ge 0.22\ast C_L,$$

(12)

where $C_L$ is load capacitance and is a design specification.

2.2. Design Procedure

In the context of the sub-micron design and design complexity, design with available models such as EKV (Enz-Krummenacher-Vittoz), long-channel (square law), etc., may become difficult. Therefore, the $g_m/I_D$ method is utilized. The developed design and optimization flow implementing the $g_m/I_D$ method is displayed in Figure 4. The inclusion of the first decision block (diamond shaped) in the flow-chart offers a greater accuracy of the design. The developed flow is a slight modification of the traditional flow.

2.2.1. Parameter Extraction from the Literature

The first step in designing the OTA starts with the extraction of the specifications from the literature review. In order to design a low-power OTA, a total current of 800 nA and a supply of $\pm 0.6$ V is chosen. The selected values keep the power of the OTA below 1 $\mathsf{\mu }$W. In the works of [19,20,21], the designed OTAs yield gain values between 31.1 and 47.6 dB, a PSRR and CMRR range between 37.2 and 70 dB and 65 and 105 dB, respectively, THD values are <$1\%$, and the input-referred noise spans between 0.12 and 174 $\mathsf{\mu }$V/$\sqrt{\mathrm{Hz}}$. In [44], the authors investigated various segments of the ECG wave and reported a minimum required slew rate of <1 V/s or 1 $\mathsf{\mu }$V/$\mathsf{\mu }$S. In this work, a gain of 60 dB (1000 in linear) and −3 dB frequency of 1.25 kHz for the OTA is selected, as the OTA for the ECG acquisition system is designed for a bandwidth of 150 to 1 kHz, depending upon its usage [45]. This produces a gain bandwidth product of 1.25 MHz. The slew rate of 0.67 $\mathrm{V}/\mathsf{\mu }$s is chosen for design convenience. The load capacitance ($C_L$) is considered as 2 pF. The specifications chosen for the design of OTA are listed in

Table 2. Design specifications for the two-stage Miller-compensated OTA.

Parameter	Value
${\mathrm{V}}_{DD}$	±0.6 V
${\mathrm{I}}_{BIAS}$	200 nA
GBW	1.25 MHz
Slew Rate	0.67 V/$\mathsf{\mu }$s
CMRR	High (≥60 dB)
PSRR	High (≥60 dB)
THD	Low (≤1%)
$C_L$	2 pF

.

2.2.2. $g_m/I_D$ Curve Generation

The schematics of Figure 5 are used for p-channel and n-channel MOSFET’s characteristic curves generation. The ‘vdc’ parameter of ‘V0’ dc source (gate source voltage, $V_{GS}$) is swept from 0.1 to 0.9 V. The drain-to-source voltage controlled by the ‘v1’ source of the MOSFET is kept constant. The ‘half supply’ variable is set to 0.6 for $M_5,M_6,M_7$, and $M_8$ and 0.3 for $M_1,M_2,M_3$, and $M_4$ MOSFETs. The source on the right (‘V2’) is used only to view the width value of the MOSFET as a legend for the generated curves and has no effect on these curves.

Variables regarding the $g_m$/$I_D$ method, such as $g_m$ (trans-conductance), $g_m$/$I_D$ (trans-conductance efficiency), ${\mathrm{g}}_m$/${\mathrm{g}}_{ds}$ (intrinsic gain), ${\omega }_T$ (transit frequency), and $I_D$, $I_D$/(W/L) (current density), are plotted against $V_{GS}$ for various channel lengths (495 nm, 1 $\mathsf{\mu }$m, 5 $\mathsf{\mu }$m, 10 $\mathsf{\mu }$m) through parametric sweeps for both n-channel and p-channel MOSFETs while keeping the width (1 $\mathsf{\mu }$m) and drain-source voltage (‘half supply’ variable) fixed. $V_{GS}$ acts as a common variable between all the other plots. Cross-plotting of the various variables (such as $g_m/I_D$ vs. $g_m/g_{ds}$ or $I_D$ or $V_{OV}$ (overdrive voltage), etc.) is performed. Figure 6 displays only the $g_m$/$I_D$ vs. $V_{OV}$ plot for L = 1 $\mathsf{\mu }$m, 5 $\mathsf{\mu }$m and 10 $\mathsf{\mu }$m. In 45 nm technology node, the simulated Figure 6 shows that the $g_m/I_D$ value varies from 8 to 36. Generally, a lower $g_m$/$I_D$ refers to the strong inversion region and a higher value refers to the weak inversion region. The moderate inversion region starts from $V_{OV}$≥ 0 mV, where the $g_m/I_D$ value is nearly 30 $\mathsf{\mu }$S/$\mathsf{\mu }$A for the simulated channel lengths.

Although the aspect ratio of MOSFETs can be calculated from the current density plot (if $I_D$ is known or assumed), an observation is made that plotting for a required or selected ‘width’ provides more accuracy in circuit-level simulation. In this work, a 100 nA current is chosen to flow through drivers $M_1$ and $M_2$. An ‘ocean script’ is developed to generate the various plots. The script can be loaded using a ‘load’ command from the ‘virtuoso’ command window and also from ‘SKILL IDE’. ‘SKILL’ functions such as ‘ocnYvsYplot (?wavex Id ?wavey gmoverId)’ in ocean script will create a cross-plot of ‘Id’ in the Y-axis and ‘gmoverId’ in the X-axis for W = 1 $\mathsf{\mu }$m. A sample ocean-script has been provided in Appendix A, where only the $g_m/I_D$ vs. $I_D$ plot of pMOS is generated using the schematic in Figure 5 (Left). It should be mentioned that the schematic must be simulated beforehand. Then the script can be utilized.

2.2.3. Aspect Ratio Selection from $g_m/I_D$ Curves

In order to determine the aspect ratio, the drain-to-source voltage, $V_{DS}$, of each MOSFET is selected. A good distribution of total supply (0.6 + 0.6 = 1.2 V) at the first stage would be as follows: 0.6 V for $M_5$, 0.3 V for $M_1,M_2$, and 0.3 V for $M_3,M_4$. For the second stage, the distribution of the total supply may be equal (in $M_6,M_7$), as it will ensure no off-set voltage at the output. The TSMC 45 nm (gpdk45) technology file has a maximum limit of channel length value of 10 $\mathsf{\mu }$m. The aspect ratio has been selected considering this constraint.

Aspect Ratio for Input Pairs (${\mathit{M}}_{\mathbf{1}},{\mathit{M}}_{\mathbf{2}}$):

For a GBW of 1.25 MHz and SR of 0.67 V/$\mathsf{\mu }$s, the value of 23.6 $\mathsf{\mu }$S/$\mathsf{\mu }$A for $g_m/I_D$ is calculated from Equation (9). From the $g_m/I_D$ vs. $I_D$ curve in Figure 7a, a $g_m/I_D$ value of 23.769 (close to 23.63) for 100 nA is selected for L = 5 $\mathsf{\mu }$m. Therefore, $g_{m1}$ becomes 2.37 $\mathsf{\mu }$S for 100 nA. In the first stage, the goal is to achieve a gain ($A_{V1}$) of at least 30 dB (33 in linear) so that the remaining gain can be achieved from the next stage. The calculated ($g_{ds1}+g_{ds3}$) for a gain of 33 is 71.8 nS according to Equation (13) [31].

$$\begin{array}{c}\hfill A_{V1}=\frac{g_{m1}}{g_{ds1}+g_{ds3}}\end{array}$$

(13)

To achieve a gain of at least 30 dB, the denominator must be ≤71.8 nS. If 71.8 nS is distributed equally in the two terms in the denominator, then $g_{ds1}$ = 35.9 nS. Therefore, the requirement for $g_m/g_{ds}$ of $M_1,M_2$ is 66. Using the $g_m/g_{ds}$ vs. $g_m/I_D$ curve for the selected L = 5 $\mathsf{\mu }$m, the $g_m/g_{ds}$ is found as 52.5 from Figure 7b, which is closer to the requirement (<66). This gives a $g_{ds}$ value of 45.1 nS. The Vov value is obtained from Figure 7c as 70.22 mV for $g_m/I_D$ = 23.769 $\mathsf{\mu }$S/$\mathsf{\mu }$A and L = 5 $\mathsf{\mu }$m. This value helps determine the required dc bias voltage at the gates of the input pairs. The selected width is 1 $\mathsf{\mu }$m.

Aspect Ratio for First-Stage Active Loads (${\mathit{M}}_{\mathbf{3}},{\mathit{M}}_{\mathbf{4}}$):

To satisfy the gain requirement of the first stage, the $g_{ds}$ of $M_3,M_4$ must be ≤(71.8 nS − 45.1 nS) = 26.7 nS. Also, the analysis in the previous Section 2.1 sub-section indicates a selection of a strong inversion (low $g_m/I_D$) region for $M_3,M_4$. From Figure 8a, the $g_m/I_D$ is found to be 17.11 $\mathsf{\mu }$S/$\mathsf{\mu }$A for 100 nA drain current at L = 10 $\mathsf{\mu }$m, and for the same length and $g_m/I_D$ value, the $g_m/g_{ds}$ is obtained as 49.6 from Figure 8b. The calculated gm and gds values are 1.711 $\mathsf{\mu }$S and 34 nS, respectively. Although the gds value is higher than the requirement (>26.7 nS), we have proceeded with this value for the first iteration. The selected width is 1 $\mathsf{\mu }$m.

Aspect Ratio for Tail Current Source (${\mathit{M}}_{\mathbf{5}},{\mathit{M}}_{\mathbf{8}}$):

The tail current source must be designed to provide a current of 200 nA. When designing the tail current source, choosing the overdrive voltage is crucial. As per the analysis, a strong inversion region is required, which means a lower $g_m/I_D$ for the current source. Equation (14) [39] establishes an inverse relationship between $g_m/I_D$ and $V_{OV}$. Therefore, a high $V_{OV}$ will be chosen.

$$\begin{array}{c}\hfill g_m/I_D=\frac{2}{V_{OV}}\end{array}$$

(14)

Choosing a high $V_{OV}$, a more stable current can be achieved, regardless of the small variations at the gate voltage. This will lead to more symmetrical operation of the input pairs and less current mismatch between them. As a result, differential gain ($A_D$) will increase while lowering the common-mode gain ($A_{CM}$). This leads to achieving a high CMRR, as suggested by Equation (15) [39].

$$\begin{array}{c}\hfill CMRR=\frac{A_D}{A_{CM}}\end{array}$$

(15)

From Figure 9a, for a 200 nA current the lowest $g_m/I_D$ is found to be 15.78 $\mathsf{\mu }$S/$\mathsf{\mu }$A for L = 10 $\mathsf{\mu }$m. This $g_m/I_D$ value provides a $g_m/g_{ds}$ of 85.39 from Figure 9b and a $V_{OV}$ of 137.3 mV from Figure 9c for the same length.

Aspect Ratio for Second-Stage Input Driver (${\mathit{M}}_{\mathbf{6}}$):

The simulation carried out only for the first stage using the chosen aspect ratios provides 385.7 mV as the biasing voltage ($V_{GS}$) of the second-stage input driver MOSFET ($M_6$). Also, a gain of 38.21 dB (81.38 in linear) is acquired at the output of the first stage. For the requirement of a gain of at least 1000 (60 dB), at least a gain of 12.29 at the second stage is needed. The requirement of $g_m/I_D$ for $M_6$ is the same as the input pairs, i.e., $g_m/I_D$ = 23.76 $\mathsf{\mu }$S/$\mathsf{\mu }$A.

Using Figure 10c, a drain current of ~550 nA (close to the requirement of 600 nA) for $V_{GS}$ = 385.7 mV has been selected. The channel length at this condition is obtained as 495 nm from this figure. A $g_m/I_D$ value of 21.01 (close to 23.76) and a $g_m/g_{ds}$ value of 24.082 are obtained at this channel length from Figure 10a and Figure 10b, respectively. The ${\mathrm{g}}_{m6}$ value is then calculated as 11.55 $\mathsf{\mu }$S. The second-stage gain is provided by Equation (16) [39].

$$\begin{array}{c}\hfill A_{V2}=\frac{g_{m6}}{g_{ds6}+g_{ds7}}\end{array}$$

(16)

Using Equation (16), the calculated ($g_{ds6}+g_{ds7}$) = 940 nS. If $g_{ds6}=g_{ds7}$ is assumed, then $g_{ds6}=g_{ds7}$ = 470 nS, and the required $g_{m6}/g_{ds6}$ is 24.5, which is slightly higher than the selected value of 24.082. The width of ${\mathrm{M}}_6$ is 1 $\mathsf{\mu }$m.

Aspect Ratio for Second-Stage Active Load (${\mathit{M}}_{\mathbf{7}}$): The first stage simulation delivers a bias voltage, $V_{GS}$, of 424.8 mV for $M_7$. Analysis of the circuit favors the use of strong inversion for $M_7$. From Figure 11c, the length of ${\mathrm{M}}_7$ is chosen as 3 $\mathsf{\mu }$m for the desired current value of 550 nA at VGS = 424.8 mV. This channel length provides $g_m/I_D$ = 17.15 $\mathsf{\mu }$S/$\mathsf{\mu }$A from Figure 11a and $g_m/g_{ds}$ = 77.84 from Figure 11b. The necessary gm is calculated as 9.43 $\mathsf{\mu }$S and the gds is 122 nS (<470 nS). This yields a gain larger than the preferred gain of 12.29 at the second stage. The width is 1 $\mathsf{\mu }$m.

2.2.4. OTA Circuit Simulation and Optimization

The OTA in Figure 3 has been designed in Cadence ‘virtuoso’ using the selected aspect ratios, as shown in

Table 3. Summary of dc operating points of each MOSFET device for the first iteration.

MOSFET	Aspect Ratio (W/L)	${\mathit{V}}_{\mathbf{DS}}$	${\mathit{I}}_{\mathit{D}}$	${\mathit{g}}_{\mathit{m}}/{\mathit{I}}_{\mathit{D}}$
$M_1,M_2$	1/5	−301.62 mV	101.38 nA	23.91
$M_3,M_4$	1/10	386.64 mV	101.38 nA	16.96
$M_5$	6/10	−511.73 mV	203.05 nA	15.61
$M_6$	7/5	331.27 mV	573.03 nA	20.87
$M_7$	5/1	−868.72 mV	573.03 nA	16.91
$M_8$	6/10	−424.84 mV	199.64 nA	15.73

, and simulated using ‘spectre’. The frequency response of the simulated OTA is shown in Figure 12. The simulated gain is 64.5 dB and obtained GBW is 954 kHz, which are close to the chosen gain (≥60 dB) and GBW (1.25 MHz), respectively.

Figure 13 shows the dc operating points of each MOSFET devices after simulation. In the first stage, the tail current source drain current ($I_{D5}$) is $I_{D5}$ = 203.05 nA, and in the second stage the output current ($I_{D7}$) is 573.036 nA. The simulated drain currents are close to the chosen value ($I_{D5}$ = 200 nA and $I_{D7}$ = 600 nA).

The dc operating points of the circuit are summarized in Table 3. The simulated $g_m/I_D$ values are consistent with the selected values from the curves.

In order to improve noise performance and to increase $V_{DS6}$ and $I_{D6,7}$, the $M_6$ and $M_7$ devices are re-designed by increasing their area. Also, at the first stage, it is required to match the $g_m/I_D$ of the input drivers perfectly and increase $V_{DS5}$. Therefore, re-distribution of the voltages are as follows: $V_{DS5}$ = 0.575 V, $V_{DS1,2}$ = 0.25 V, and $V_{DS3,4}$ = 0.375 V. The aspect ratios are re-calculated.

Figure 14 reveals the new choice (final iteration) of $g_m/I_D$, VOV, and $g_m/g_{ds}$ selection for input pairs. The shaded region depicts the moderate inversion region. This can be confirmed from Figure 15, showing the $fT$x$g_m/I_D$ vs. Vov plot, which has a bell-shaped curve. The peak value at $V_{OV}$ = 135 mV lies inside the moderate inversion region. It should be noted that the moderate inversion region starts from Vov = 0. The operating point for the driver MOSFETs is 66.85 mV, which is inside the moderate inversion region.

The design is finalized after a few iterations. After that, the OTA is simulated for dc, transient, ac, noise, input–output wave shape similarity, gain, power-consumption, and input-referred noise analyses. The aspect ratios are tweaked to meet the requirements (if not met) further, and the simulations are re-run.

Table 4. Design parameters for the two-stage Miller-compensated OTA of instrumentation amplifier.

Parameter	Value
${\mathrm{V}}_{DD}$	±0.6 V
${\mathrm{I}}_{BIAS}$	200 nA
${(\mathrm{W}/\mathrm{L})}_{M1,M2}$	1 $\mathsf{\mu }$m/5 $\mathsf{\mu }$m
${(\mathrm{W}/\mathrm{L})}_{M3,M4}$	1 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m
${(\mathrm{W}/\mathrm{L})}_{M5,M8}$	6 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m
${(\mathrm{W}/\mathrm{L})}_{M6}$	7 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m
${(\mathrm{W}/\mathrm{L})}_{M7}$	5 $\mathsf{\mu }$m/1 $\mathsf{\mu }$m
Cc	500 fF

summarizes the finalized design of the OTA.

2.2.5. Instrumentation Amplifier and Filter Circuits Simulation and Optimization

The circuit topology (for individual blocks) is decided from the literature review and ease of design perspective. Active RC filters are chosen for this work, and subsequently low-pass, high-pass, notch filters, and instrumentation amplifier (IA) circuits are separately designed and simulated. For each individual circuit, the desired gain and component values (resistor and capacitor) are decided from the design equation, component sweep, and parametric analysis. Initially, the −3 dB (cut-off) frequency is derived from the specifications. Using the design equations, all the component values are calculated. Then, applying sweep and parametric analysis (keeping the calculated values inside the sweep range), the component values are selected and optimized. The design and optimization flow is displayed in Figure 16.

All the individual circuits are tested for ringing-free (oscillation-free) operation, which is ensured by (closed-loop phase margin ≥ 60°) transient and ac simulations.

2.2.6. Trade-Off and Optimization for the AFE

Eventually, the individual circuits are cascaded for the realization of the whole system (AFE). All the necessary analyses are simulated to check and verify the operation of the AFE. For the final trade-off and optimization, analysis of the simulated circuit is performed manually. Minute changes are made to optimize (reduce IRN, power) the individual circuits. For optimization, the developed flow of work is followed.

Table 5. Finalized aspect ratios for the optimized OTAs.

Parameter	IA	LPF	HPF	Notch
${(\mathrm{W}/\mathrm{L})}_{M1,M2}$	1 $\mathsf{\mu }$m/5 $\mathsf{\mu }$m	2.5 $\mathsf{\mu }$m/5 $\mathsf{\mu }$m	1 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m	1 $\mathsf{\mu }$m/5 $\mathsf{\mu }$m
${(\mathrm{W}/\mathrm{L})}_{M3,M4}$	1 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m	1 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m	1 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m	1 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m
${(\mathrm{W}/\mathrm{L})}_{M5,M8}$	6 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m	6 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m	6 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m	6 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m
${(\mathrm{W}/\mathrm{L})}_{M6}$	7 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m	1 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m	1 $\mathsf{\mu }$m/5 $\mathsf{\mu }$m	5 $\mathsf{\mu }$m/5 $\mathsf{\mu }$m
${(\mathrm{W}/\mathrm{L})}_{M7}$	5 $\mathsf{\mu }$m/1 $\mathsf{\mu }$m	0.9 $\mathsf{\mu }$m/0.9 $\mathsf{\mu }$m	10 $\mathsf{\mu }$m/1 $\mathsf{\mu }$m	7 $\mathsf{\mu }$m/1 $\mathsf{\mu }$m

summarizes the optimized OTAs for different circuits.

3. ECG Acquisition System Design

Figure 17 shows the full circuit diagram for the proposed AFE for ECG signal acquisition. The system contains a band-pass filter with a notch. Two-stage OTAs (un-buffered) are utilized instead of three-stage OTAs (buffered) to reduce the transistor count. As the final stage of the OTA is a common source amplifier, it provides high output impedance. Thus, the design of filters must employ very high resistance values in order to avoid the loading effect. A three-stage OTA would reduce the resistor values but it is difficult to design for the necessary phase margin.

ECG signals mostly vary from 10 $\mathsf{\mu }$V to 5 mV in amplitude and are mostly concentrated between 0.05 Hz and 35 Hz frequency [46]. According to [47,48,49], a 0.2 mV–5 mV voltage range is considered for the design. Frequency ranging from 0.05 Hz to 250 Hz is chosen for the design, as per [4,47,50,51]. The constraints for the filters of ECG acquisition systems are as follows: (1) Low input-referred noise density (<400 $\mathsf{\mu }$Vrms/$\sqrt{\mathrm{Hz}}$), (2) High order, (3) Low THD (<−50 dB), and (4) Low power consumption (<50 $\mathsf{\mu }$W) [38]. For the filters, Active-RC topology is used, though a Gm-C filter might seem preferable [52]. A Gm-C filter can accommodate higher bandwidths but is sensitive to parasitics [53]. In [54], a comparison shows that the Active-R filter performed slightly better than the Gm-C filter. In [53], the authors found Gm-assisted Active-RC’s linearity is better than Gm-C. The tunability of Active-RC for gain and bandwidth is much easier [55].

An instrumentation amplifier with low noise performance is added as the input stage. The gain of the instrumentation amplifier helps the overall noise to decrease [56]. A total of nine OTAs are used for the four blocks.

3.1. Instrumentation Amplifier

An nstrumentation amplifier (IA) is used to subtract the two input signals while providing a suitable gain to the whole system. Three OTAs and seven resistors (6xR1, Rvar1) are required for the design of the IA. The ‘Rvar1’ ($R_{gain}$) variable resistor can be adjusted to control gain.

$$A_V=1+\frac{2R}{R_{gain}}$$

(17)

Utilizing design Equation (17) [57], the values of the resistors are determined for a specific gain. To avoid the loading effect, R and $R_{gain}$ are selected to be at least greater than 10 times.

3.2. Notch Filter Design

The second block of the circuit is a second-order active Twin-T topology notch filter. Two OTAs, three capacitors (2xC1, C2), and five resistors (2xR2, R3, R4, R5) are required in the design of this block. This type of filter usually provides no gain.

$$\begin{array}{c}\hfill f_N=\frac{1}{4\pi RC}\\ \hfill Q=\frac{f_N}{BW}\\ \hfill K=1-\frac{4}{Q}\end{array}$$

(18)

Applying Equation (18) [57], resistor and capacitor values are determined for a high-Q high notch-depth.

3.3. Low-Pass Filter Design

The third block of the circuit is a fifth-order Butterworth low-pass filter. Cascaded topology is used in realizing the fifth-order filter. Though function replacement realization is preferred over other topology [38], cascade-active topology is easier to design for the required band and additional gain. Two second-order filters followed by a first-order filter provide a fifth-order filter. To ensure ringing-free operation, a minimum of a 45-degree phase margin is required, while 60 degrees is preferable in the closed-loop systems [31,39]. The two second-order sections gains are chosen to be 0 dB. This ensures more than a 60-degree phase margin in the closed-loop system. The final section is a first-order section with a gain > 0 dB. The ‘Rvar2’ is a variable resistor to control gain. The LPF block comprises three OTAs, five capacitors (5xC3), and nine resistors (5xR6, 2xR7, R8, Rvar2). The LPF is designed for a higher cut-off frequency of 250 Hz, which is a requirement of ECG acquisition systems.

$$f_c=\frac{1}{2\pi RC}$$

(19)

Using Equation (19) [57], capacitor (C), and resistor (R) values are calculated.

3.4. High-Pass Filter Design

The final block of the circuit is a second-order Butterworth high-pass filter. For proper biasing conditions, the inverting input is connected to ‘VSS’ instead of ‘gnd’ through R10. This block contains one OTA, two capacitors (2xC4), and four resistors (R9, 2xR10, R11). Ideally, for an ECG signal the lower cut-off frequency is 0.05 Hz.

$$f_c=\frac{1}{2\pi RC}$$

(20)

Employing design Equation (20) [57], capacitor value (C) is calculated after careful selection of resistor value (R).

The designed parameters (resistors and capacitors) of the whole system are summarized in

Table 6. Design parameters for the proposed ECG acquisition system.

Parameter	Value
R1	300 M$\mathsf{\Omega }$
R2	32 M$\mathsf{\Omega }$
R3	16 M$\mathsf{\Omega }$
R4	10 M$\mathsf{\Omega }$
R5	99 M$\mathsf{\Omega }$
R6	190 M$\mathsf{\Omega }$
R7	400 M$\mathsf{\Omega }$
R8	900 M$\mathsf{\Omega }$
R9, R10	3.5 G$\mathsf{\Omega }$
R11	1 G$\mathsf{\Omega }$
Rvar1	60 M$\mathsf{\Omega }$
Rvar2	200 M$\mathsf{\Omega }$
C1	99.2 pF
C2	198.4 pF
C3	1.4 pF
C4	900 pF

. The large resistors can be substituted with MOSFETs (operating as resistors).

4. Simulation and Results

The section portrays the various simulation results and discusses the findings. A brief introduction to various ‘analyses’ is first provided in Section 4.1. Then pre-layout simulations of the OTA and the proposed ECG acquisition system are shown in Section 4.2, followed by the post-layout simulations in Section 4.3. A comparison with recent works is stated in Section 4.4. Here, all the simulations are carried out in the Cadence virtuoso software version: 6.17 using the 45 nm MOSFET model by TSMC.

4.1. Analyses and Test-Bench

A ‘symbol’ view is given to the schematic of Figure 3. The ‘symbol’ view contains seven pins. The view is used to prepare a test-bench schematic (as shown in Figure 18) for various analyses, i.e., dc, ac, noise, pole-zero, etc.

DC analysis: The dc analysis reveals the biasing (operating) condition of all the MOSFET devices. By this, it is verifiable whether a device is operating in the cut-off, sub-threshold, triode, or saturation region. Variable ‘vdc’ is set to common-mode voltage, while the ‘acm’ variable is set to 0. Proper biasing current is applied using the ‘IBIAS’ variable. Using the ‘Vsupply’ variable, the supply voltage is provided. The ‘Cc’ variable sets the coupling capacitor value. These parameter values will be required for most of the analyses.

Transient analysis: Transient analysis is performed to check the circuit operation for change of inputs with time. Proper bias condition parameters are given as stated in the DC analyses. Additionally, for the two inputs (inverting, non-inverting) the ‘vsin’ source parameters ‘Amplitude’ and ‘Frequency’ are set to 1 mV and 20 Hz, respectively, for our simulation. ‘Initial Phase for Sinusoid’ for the inverting source is set to 180. The time-domain output is observed at the ‘Output’ pin. THD and SNR can also be performed after transient analysis. Once the transient waveform is plotted, the spectrum can be plotted for a signal from the ‘measurement’ option at the virtuoso visualization window.

AC analysis: With the help of ac analyses, the ac performance metrics, such as gain, phase, −3 dB frequency (cut-off), and unity-gain bandwidth (UGBW), can be measured. The variables ‘vdc’, ‘IBIAS’, ‘Cc’, and ‘Vsupply’ are set to proper values. The‘acm’ parameter is set to 1m. The inverting input source ‘acp’ parameter is set to 180 degree. This sets the two ac inputs to 180 degree out of phase. To observe gain and phase, ‘AC Gain & Phase’ from ‘Direct plot’ can be used.

Pole-zero analysis: For ‘pz’ analysis, the positive output, negative output, and input voltage parameter from the ‘pz’ analysis window are set. The dc biasing is given. Then, pole-zero summary can be observed or plotted using ‘Main form’.

Noise analysis: One of the key parameters of the system is input-referred noise. It can be measured using the test-bench. Proper biasing needs to be provided. The ‘acm’ variable must be set up for one of the inputs. This input source generates the noise. Then, in ‘Noise’ analyses form, that source must be selected as input. In ‘Direct plot’, the ‘Main form’ has the option for noise-related curve generation. ‘Noise summary’ is also an excellent option for input-referred noise measurement.

CMRR analysis: A different test-bench schematic is developed for the CMRR analysis, where two of the same OTA connections are provided. One connection is similar to the test-bench shown in Figure 18 and the other has the two inputs tied together to a ‘vdc’ source only (no ‘vsin’) to provide a common-mode voltage. After that, the CMRR expression is evaluated. Virtuoso calculator is used to create the expression. Usually, a higher CMRR is desirable.

PSRR analysis: A different test-bench schematic is developed for the PSRR analysis, where output is connected to inverting input via the ‘iprobe’ cell from ‘analogLib’. ‘xf’ analysis is selected for this purpose.

Monte Carlo: This simulation provides the statistical report of different outcomes due to process, variation, and temperature (PVT). For the schematic in Figure 18, the ‘vth’ parameter is chosen to be evaluated for the variations. The ‘dc’ parameter expressions can be extracted using ‘calculator’. For this simulation, the ‘ADE XL’is used. The results can be observed in histograms.

4.2. Schematic-Level Simulation

4.2.1. Operational Trans-Conductance Amplifier (OTA)

The designed OTA is simulated using ‘spectre’ using TSMC’s 45 nm pdk technology with a supply voltage of ±0.6 V. The dc analysis confirms the operating condition of all the MOSFET devices in the required inversion/saturation region. Figure 19 shows the magnitude response of the OTA, which shows that the low-frequency (dc) gain is 64.5 dB or 1679 (65.69 at the first stage and 25.56 at the second stage), −3 dB frequency (cut-off) is at 864 Hz, and a unity-gain bandwidth is 1.24 MHz. The choice of ‘moderate inversion’ region for the driver MOSFET’s ($M_1$, $M_2$, $M_6$) with a higher $g_m/I_D$ than in the ‘strong inversion’ region assures the high gain. The first stage gain is very close to the chosen $g_m/g_{ds}$ value (68.22 in Figure 14).

From the pole-zero analysis presented in Figure 20, the dominant pole approximately at 843 Hz sets the −3 dB frequency. In total, four poles and three zeros are observed. No right half poles but one right half zero is observed. The poles are from the input (P4), mirror (P3), first stage output (P2), and second-stage output (P1).

From the pole-zero diagram, P3 and Z1 nullify each other. The gain starts to decay at a frequency of 843 Hz (P1), which is further enhanced by the pole P2 at 389 KHz. The gain reaches 0 dB at 1.24 MHz. The pole P4 further increases the negative slope of gain at 1.75 MHz. Taking Bode’s approximation into account, the three poles before 3.4 MHz create a slope of −60 dB/decade, where the two zeros increase the slope to −20 dB/decade. The system shows a phase margin of an acceptable 34 degree.

A common mode rejection ratio (CMRR) of 66.52 dB over a bandwidth of more than 10 kHz is observed in Figure 21, which confirms an attenuation of more than 1000 times for the common noise coming through the two inputs. This is due to the high differential gain from high $g_m/I_D$ value. The low mismatch in $g_m$ values of $M_1,M_2$ also contributes to this findings. Power supply rejection ratios (PSRRs) of −53.17 and −76.55 dB within 1 kHz bandwidth for positive and negative sources noise are observed in Figure 22. If any noise appears at the power supply, the OTA will attenuate that noise by at least 456 times.

The transient analysis with the given test-bench can be utilized for THD calculation. This can be done from ‘Virtuoso Visualization and Analysis’ (also known as ‘ViVA’ window) in ‘Measurements’ from Spectrum. Figure 23 displays a ottal harmonic distortion (THD) of −114.9 dB (less than 1%) for the 400 $\mathsf{\mu }$V peak-to-peak (p-p) signal at 100 Hz. The THD here is a second-order harmonic. Due to differential input, the remainder of the even-order harmonics are nullified.

The OTA gives out an output impedance of 2.06 M$\mathsf{\Omega }$ and a large input impedance of 5.13 G$\mathsf{\Omega }$ inside the frequency of interest, as seen from Figure 24 and Figure 25. For output impedance measurement, a voltage source is added to the OTA’s output node. The current is measured at the same node, while frequency is varied.

When an input capacitance of 100 pF [58] is assumed as layout pad capacitance, the input impedance is reduced to 3.03 G$\mathsf{\Omega }$. This is shown in Figure 26.

Table 7. Performance comparison of the proposed OTA with previously reported work.

Parameter	This Work	[19]	[20]	[21]
Tech (nm)	45	350	180	180
Topology	Miller-OTA	CR-OTA 1	GBFC-IBL 2	MI-OTA 3
Supply (V)	±0.6	2	±0.75	±0.5
$I_{Total}$ (A)	816 n	160 n	570 n	200 n
Power (nW)	980	320	855	267.5
Gain (dB)	64.5	39.8	47.6	31.17
PSRR (dB)	76.55	70	-	37.26
CMRR (dB)	66.55	65	105.6	90.05
THD (%)	<1	<1	<1	<1
IRN ($\mathsf{\mu }$V)	15.9	2.05	0.12 (PSD)	174
Zin ($G\mathsf{\Omega }$)	5.1	-	0.3	-

¹ CR-OTA = current re-used operational trans-conductance amplifier; ² GBFC-IBL = gain-boosted folded-cascode with impedance boosting loop; ³ MI-OTA = multiple-input operational trans-conductance amplifier.

summarizes a performance comparison of the proposed OTA with the state-of-the-art OTAs. Considering the lowest technology node, the proposed OTA provides the best gain and PSRR, and a comparable power, CMRR, THD, integrated IRN, and Zin.

The NEF of the circuit is determined to be 10.43 and calculated as Equation (21). The high NEF is due to the design being done in a smaller technology node while using less area. To improve both NEF and figure of merit (FOM), power consumption (total current) must be reduced while bandwidth must be increased.

$$NEF=V_{ni,rms}\sqrt{\frac{2I_{tot}}{\pi ·U_T·4kT·BW}}$$

(21)

The process variation of the technology can change the performance of the OPAMP [59], which in turn can change the response of the circuit. Figure 27 illustrates the Monte Carlo histograms at T = 27 °C for 100 points of the threshold voltage parameter of $M_{1,2}$. A deviation of nearly ±20 mV is observed from the mean value. The OTA designed in this work has a 72.3 mV difference in gate-to-source voltage. This ensures the desired region operation. The designers may opt for PVT simulations as it reveals biasing related challenges.

4.2.2. ECG Acquisition System

All the filters and instrumentation amplifiers are simulated separately before forming the whole ECG system. Various performance parameters and figures are obtained via dc, ac, transient, xf, noise analyses using spectre simulator.

Table 8. Input-referred noise, power consumption, and total harmonic distortion for the filters.

Parameter	Second-Order HPF	Notch Filter	Fifth-Order LPF
Input-Referred Noise	70.1 $\mathsf{\mu }$Vrms/$\sqrt{\mathrm{Hz}}$	14 $\mathsf{\mu }$Vrms/$\sqrt{\mathrm{Hz}}$ @ PB	130 $\mathsf{\mu }$Vrms/$\sqrt{\mathrm{Hz}}$
Power Consumption	2.034 $\mathsf{\mu }$W	2.67 $\mathsf{\mu }$W	1.21 $\mathsf{\mu }$W
Total Harmonic Distortion	−92.5 dB	−52.1 dB	−112.2 dB

summarizes the various performance parameters of the high-pass filter (HPF), notch filter, and low-pass filter (LPF), designed for the ECG system. All of the individual parameters are within the acceptable value mentioned in [38]. As the first block is an instrumentation amplifier and provides gain, the input-referred noise is reduced for the whole system.

Figure 28 shows the schematic used as the test-bench for the ecg acquisition system. Supply voltages (VDD, VSS) are given as ‘stimuli’.

Figure 29 shows the magnitude response of the ECG system. The pass-band gain of the system is 58 dB. The lower cut-off is at 82.24 mHz, resulting from the second-order HPF poles, and the higher cut-off is at 248.15 Hz, which is due to the poles of the fifth-order LPF. The cut-offs of the notch filter are at 41.38 Hz and 60.78 Hz. The notch depth is 56.4 dB at 50.1 Hz. These results confirm that the designed circuit can function within the specified bandwidth of the ECG signals, where the 50 Hz power-line frequency is selectively notched out.

Figure 30 verifies the stability performance of the whole system through a pole-zero map. All the poles are situated inside the left half plane (LHP), while few zeros are located at the right half plane (RHP). Right half plane poles makes the system unstable, but zeros do not. Right half plane zeros provides a +20 dB/decade gain and −90 degree phase change. This makes it difficult to achieve the desired phase margin, as the gain will increase at that frequency but phase decreases, which will reduce the phase margin (total phase change from 0 or 180 degree till 0 dB gain). Since the proposed system reaches 0 dB gain near 1 kHz frequency, the effects of the RHP zeros becomes insignificant.

The input-referred noise is demonstrated in Figure 31. Flicker noise is typically a low-frequency noise and is high at low frequencies. It decreases with the increase in frequency. From 0.01 to 0.1 Hz, the noise decreases, which is a typical behavior of flicker noise. The notch filter attenuates the signal by nearly 56 dB at 50.1 Hz. This will make the signal weak, but there will be strong noise at that frequency. Similar behavior is observed from the figure, which shows a large spike of 927.452 $\mathsf{\mu }$ input-referred noise at 50.11 Hz.

Using the MIT-BIH dataset, an ECG signal [60] with added noise at 50 Hz and 500 Hz is fed to the ECG system. The overall gain of the system is set to 46 dB by changing the value of variable resistances for gain control. The ECG signal voltage spectrum is shown in Figure 32 (Left), with externally added noise at 50 and 500 Hz. In a typical ECG signal spectrum, most of the considerable signal is within the 35 Hz range. This can be confirmed by the magnitude from 0 to 35 Hz, which ranges between 25 and 500 µV. The output voltage spectrum of the ECG system is shown in Figure 32 (Right), where it can be seen that noise at 50 Hz is not visible and noise at 500 Hz is reduced, while the magnitude of the signal is increased to a maximum value of nearly 26 mV.

Figure 33 depicts the time domain signals, where VL (green) and VR (blue) are input signals from electrodes of the left arm and right arm, respectively. Vout (red) is the output signal from the ECG system. As demonstrated, the noise at the output signal is minimized and can be understood by comparing the haziness of the VL, VR, and Vout signals.

The THD values in Figure 34 represent the system’s performance within the range. All THD values are less than −50 dB. For the ECG signal range (0.2 mV–5 mV), the designed system provides good linearity and a 158–797-times larger signal at the output. It is worth mentioning that the dc analysis of the whole system has been done to ensure an appropriate region of operation of all the transistors.

The dynamic range (DR) is calculated as the ratio of maximum output voltage to minimum output voltage in dB and is computed to be 52.71 dB.

4.3. Post-Layout Simulation

4.3.1. Operational Trans-Conductance Amplifier (OTA)

From the schematic-level cell views, the devices are generated and then routed to complete the layout. All of the OTAs are design-rule-checked, layouted, and extracted using Cadence virtuoso’s ‘Layout XL’ tool (PVS, QRC plugins). For post-layout simulation, a ‘config’ view is created for the test-bench circuit (‘schematic’ view). The ‘config’ view is also known as the hierarchy editor. From the ‘config’ view, all the OTAs are set to the ‘av-extracted’ view. This ‘av-extracted’ view contains all the parasitic resistances and capacitances formed after the layout. Then, the test-bench ‘schematic view’ and ADE L (Analog Design Environment) are opened from the ‘config’ view. Again, ‘spectre’ is chosen as the simulator for the ADE L. Using the same ‘states’ from pre-layout simulation (saved previously), simulations are carried out for various analyses.

For the ECG system layout, only the OTAs (total nine) of various blocks (IA, filters—Notch, LPF, HPF), the interconnection between them, and the bias circuit are considered. For each OTA, the $I_{BIAS}$ can be replaced by two (one p-channel and one n-channel) diode-connected MOSFETs of $W/L$ = $1.2\mathsf{\mu }/10\mathsf{\mu }$. All the R, C components are excluded from the layout. Figure 35 show the proposed layout view of the instrumentation amplifier OTA.

Advanced layout technique such as the common-centroid method is applied for both differential pairs and current mirror inside the OTAs. This helps to reduce mismatch. No dummies are used, but sufficient space is kept for dummies, if required. The layers used for layout are shown in Figure 35a. For routing purposes, only metal 2, 3, and 4 are used, as higher metals have lower resistivity. This reduces voltage drop in interconnects. The direction for metals 1 and 3 is kept vertical, and for metals 2 and 4 it is horizontal. No metal jogging is done. Multiple vias are placed wherever possible. This allows for better signal strength. For block-to-block interconnection, metal 4 is used. Devices with widths greater than 1 $\mathsf{\mu }$m are broken into smaller multiple devices with widths of 1 $\mathsf{\mu }$m. Guard rings for pMOS and nMOS devices are used to prevent latch-up issue. All the pMOS devices of OTA share a common ‘nwell’, while nMOS devices share a common ‘pdummy’. The top half of the layout is used for pMOS devices and the bottom for nMOS devices. Routing symmetry is maintained between $M_1,M_2$ pairs and $M_5,M_8$ pairs. This helps in matching. The IA-OTA poses dimensions of 42.58 µm × 16.995 µm (W × H). The dimensions could have been reduced with less gaurd rings and a more compact floor-plan (placement of devices). Though capacitors are not included in the layout, ‘mimcaps’ can be used to implement such capacitors. ‘pmoscap’ would reduce the area but also reduces the performance of the system, as it incorporates resistance along with it. In 45 nm node, the sheet resistance of various metals would cause a very large area for resistors only. Consequently, in this work, off-chip resistors and capacitors are used.

Four different layouts and PEX for IA-OTA, Notch-OTA, LPF-OTA, and HPF-OTA are created. Figure 36 shows the post-layout magnitude response of the IA-OTA. The gain is slightly increased, while the −3 dB frequency is reduced due to the added parasitics. The CMRR, PSRR, and Zin remained similar, which can be seen from Figure 37, Figure 38 and Figure 39. The post-layout THD has improved by 8.8 dB and Figure 40 confirms the improvement. These changes did not vary much and could be deemed acceptable.

4.3.2. ECG Acquisition System

Finally, the layout of the ECG system is designed with the OTAs, as shown in Figure 41. The red-marked region is IA, blue is Notch, yellow is LPF, green is HPF, and black is bias circuit. The layout dimensions are 85.62 µm × 67.79 µm (W × H), occupying an area of 0.0058 mm² without the biasing circuit and 85.62 µm × 73.39 µm (W × H), occupying an area of 0.00628 mm² with the biasing circuit. This area does not include pad area.

Figure 42 demonstrates the post-layout frequency response of the ECG acquisition system, where no significant changes are observed. The new bandwidth is approximately 239 Hz, which is only 7 Hz lower than that obtained from the schematic-level simulation.

Figure 43 verifies a good similarity in noise performance with the pre-layout simulation. This justifies that the layout has less parasitic effects.

Figure 44 displays the systems output in the application of noisy ECG inputs, which is similar to the schematic-level simulation output.

4.4. Comparison with State-of-the-Art Designs

Table 9. Performance comparison of the designed ECG acquisition system with contemporary designs.

Parameters	This Work 1	[58] 2	[21] 1	[61] 1	[62] 1	[63] 2
Technology (nm)	45	180	180	180	180	180
Supply (V)	±0.6	1.8	±0.25	0.5	0.5	1
Order	HPF-2nd, LPF-5th	LPF-2nd	BPF-3rd	LPF-4th	BPF-2nd	LPF-5th
Power ($\mathsf{\mu }$W)	10.88	4.5–19.4	0.161	0.003	0.0313	0.041
Gain (dB)	58.06	34.5	0	−5.6	37.1	−7
BW (Hz)	0.08–239.6	1.7–352	0.1–250	200	1.5–112	250
IRN ($\mathsf{\mu }$V)	33.6	3.47	198	91.9	17.9	134
PLI Removal	Notch	Notch	Notch	No	No	No
Area (mm2)	0.00628 (off-chip RC)	156.25	0.0528 (off-chip cap)	0.074	0.167	0.24
NEF	10.43	2.99	-	-	-	-
Dynamic Range (dB)	52.71	-	66.98	48.5	55.5	61.2

¹ Post-layout simulated; ² Measured.

summarizes a comparison of the performance metrics with state-of-the-art designs for ECG acquisition systems. Among the mentioned works, this work utilizes the smallest technology node (45 nm). The order of the filter and gain of the system designed here are the highest among the reported works. This work has the smallest chip area and has the best input-referred noise with power-line-interference removal capability. Usually, a smaller NEF (noise efficiency factor) is preferred in biomedical ASICs (application specific integrated circuits). However, the lower technology node and smaller area are some of the factors that contributed to the high NEF. The remaining parameters are comparable. These results highlight the fact that the $g_m/I_D$ methodology with slight modification used in this work can be utilized in designing OTAs with reduced time and effort.

5. Conclusions

This paper focuses on the design flow for a low-power, low-noise, and high-gain ECG acquisition system. A two-stage OTA is successfully designed using the developed $g_m/I_D$ methodology. All the blocks are designed and simulated separately. Finally, they are cascaded to form the band-pass filter with a notch (ECG system) to remove power-line interference (PLI). The designed ECG acquisition system is simulated at T = 27 °C using TSMC 45 nm technology in Cadence virtuoso. DC, AC, transient, power, CMRR, PSRR, noise, pole-zero, and THD are analyzed. The design is layouted and to fortify confidence in the design, post-layout simulations after parasitic extraction (PEX) are performed. The AFE successfully de-noised a noisy ECG signal (MIT-BIH dataset). Comparison of the performance metrics with state-of-the designs for both the OTA and the ECG acquisition system implemented in this work shows their superiority considering the lowest technology node used herein. Therefore, the proposed design in this work has excellent promises for the realization of an ECG acquisition system for modern healthcare.