Research on Fixed-Slope On-Chip Soft-Start Method Applied to Buck DC–DC Converter

Abstract

A fixed-slope soft-start method applicable to Buck converters for on-chip integration is proposed to address the issue of varying power stresses (device voltage, current stress) during start-up with different output voltages. The main mechanism involves combining feedback coefficient sampling with a fixed-slope reference voltage to achieve a slow rise in the reference voltage by equating the soft-start charging current to a pulse current through the on-chip integration of a small capacitor. This allows for fixed-slope start-ups for different set output voltages. Spike elimination techniques are employed to address charging current spikes caused by pulse periods, enhancing precise control over the soft-start time. By replacing the traditional resistor divider network with a capacitive divider network in the soft-start method, DC power consumption is minimized. Upon completion of the soft start, a smooth transition to a steady-state operation occurs, with the automatic shutdown of the soft-start module reducing static power consumption. A specific circuit design and layout verification based on 0.18 μm high-voltage BCD technology demonstrates that the proposed method maintains a fixed-slope start-up of approximately 5 mV/μs within the chip’s output range of 0.9 V to 4 V, with a slope control accuracy of up to 98%. The soft-start circuit effectively eliminates surge currents generated during start-up under full load conditions of 3 A and no-load conditions of 0 A, reducing the overall surge current by 44% and enabling a stable voltage rise and the smooth transition to a steady-state operation.

1. Introduction

With the rapid development of smart IC electronic technology, portable devices have gained popularity in various fields such as consumer electronics and medical applications. In order to provide stable operating voltage for portable devices, efficient and high-quality power management integrated circuits (ICs) play an increasingly important role due to their high efficiency, strong load capacity, and low static current characteristics. Fully integrated compact DC–DC converters are widely used in a growing number of applications given their effectiveness and quality [1,2,3].

During the start-up phase of a DC–DC converter, as the output voltage has not yet been established, the control loop will operate at a full duty cycle. This can lead to a momentary surge current from the power source to the load capacitor. On the one hand, this surge current can cause a temporary drop in the supply voltage, resulting in the inability of the front-end application modules to function properly. On the other hand, considering the tolerance for power stresses, which includes the voltage and current stresses of various components, excessive surge currents may lead to chip damage due to output voltage overshoot.

The most common soft-start method is to replace the error amplifier input voltage V_REF with a voltage that rises at a certain slope [4], which means that the start-up time is limited by the ramp voltage, the scheme is highly reliable and free of inrush currents and voltage overshoots [5], and then, subject to the limitations of the process bias, a large capacitor is required to ensure the soft-start time [6,7]. Reference [8] uses a pulsed current for soft-start capacitor charging. This method is somewhat equivalent to reducing the charging current to ensure the use of smaller capacitors, but by using this process, the charging branch switch caused by the voltage burr will greatly affect the accuracy of the soft-start time. Reference [9] uses a digitally controlled soft-start circuit. This method does not introduce soft-start capacitance, but in order to eliminate the inrush, the current and overshoot voltage need to be sacrificed in order to eliminate the performance of the starting speed, and the staged digital control logic is also more complex. Reference [10] uses a dual-negative feedback loop control to generate a slowly rising reference voltage to clamp the error amplifier node in order to achieve a stable duty cycle start-up. This method eliminates the inrush current and improves the start-up speed at the same time, but the introduction of the dual-loop design requires higher gain and bandwidth op-amps, which makes it more difficult to design. Reference [11] uses an inverter in a Buck converter using a RC to generate a soft-start capacitance, but it does not introduce a soft-start capacitor. The Buck converter through the RC generates 40 ns delay to the constant duty cycle mode for the soft start. It can effectively compress the overall area if the output voltage is low when the constant duty cycle meets the conditions of the start, or, if the output voltage is high, the loaded start-up constant duty cycle may lead to the failure of the output voltage to start. Secondly, this method cannot be achieved in a more highly accurate soft-start control. Reference [12], in the same way as reference [13], uses an RC circuit to generate a slowly rising reference voltage, and this type of method must use a larger RC if a larger start-up time is desired. Reference [14] employs Pulse-skipping soft starting, which effectively reduces the on-chip soft-start capacitance, but again does not achieve soft-start functionality under the worst starting conditions.

In many IC applications, there are strict requirements for multiple power supply rails, and even the timing of power supply start-up to achieve efficient energy management. In such applications, using traditional fixed-time soft-start methods may lead to issues when facing different power stresses during no-load start-up across multiple power supply rails. Considering the worst-case start-up scenarios may result in sacrificing start-up time, or even impacting the selection of load components.

Therefore, to address the aforementioned issues, this paper proposes a low-power fixed-slope on-chip soft-start method for Buck DC–DC converters. This method effectively resolves the issue of varying power stresses during soft-start at different output voltages, and eliminates the risk of surge currents generated during on-chip start-up.

2. Design of Buck Converter Architecture with Fixed-Slope Soft Start

Figure 1 illustrates the ACOT (Advanced Constant On Time) architecture Buck converter with a fixed-slope soft-start. By precisely controlling the conduction time of the power switches in each cycle, and by adjusting the turn-off time through negative feedback, the system indirectly controls the operating frequency without the need for an oscillator, thereby providing excellent transient response characteristics.

Additionally, at the beginning of the chip’s soft-start sequence, there may be a non-zero output voltage. When the chip is forcefully started, it is easy to create a path from the output to ground. In some boost systems, there may exist a path from the output to the input, leading to excessive backflow current that can damage the chip. Therefore, the system needs to first determine if there is a pre-bias voltage output during the soft-start period.

Figure 2 illustrates the timing waveforms of the chip’s no-load start-up process. As shown in the left part of the figure, when a pre-bias voltage is present [15], the V_FB voltage exceeds the soft-start reference voltage V_{REF_SS}. Both the high-side and low-side power switches are turned off at this point. The soft-start module outputs the soft-start reference voltage normally. Once this reference voltage surpasses a threshold voltage relative to V_FB, the pre-bias start-up module deactivates. The system logic takes over the original signal to drive the power switches, transitioning the system into the normal soft-start mode.

In this paper, on the one hand, the soft-start voltage, V_{REF_SS}, is used to replace the reference voltage, V_REF, at the positive input of the Error Amplifier (EA), representing a traditional and highly reliable method for reducing the inrush current during the start-up phase. On the other hand, this paper adopts a periodic pulse signal to charge the soft-start capacitor, significantly enhancing precise control through the use of a voltage spike elimination circuit. This approach achieves capacitance multiplication, substantially reducing the capacitor size and facilitating the integration of the soft-start capacitor into the chip.

Furthermore, compared to the traditional fixed-time soft-start mode, the fixed-slope soft-start mode can generate the required output voltage with a stable slope when different output voltages are selected by the user. This ensures that power supply stress requirements are met across all output scenarios. In contrast, the conventional fixed-time soft-start method may result in higher power-supply stress if a larger output voltage is selected to start up after a predefined fixed time.

It is noteworthy that the fixed-slope soft-start design in this paper is based on sampling V_OUT and V_FB. Therefore, the system requires some load capacitor charging. At the start-up phase, the high-side power transistors are activated for a specific duration to obtain sampled values of the output voltages, unless a pre-bias voltage is present. Although the pulse current and voltage spike cancellation technique reduces the capacitor’s footprint, the circuit remains in a switching state post-sampling due to effects like charge injection and clock feedthrough. Hence, it is advisable to use a soft-start capacitor within the range of 5 pF.

3. Low Power Fixed Ramp Soft Start

3.1. Sensing Method for Feedback Coefficients

The core circuit of the feedback coefficient sampling module is depicted in Figure 3. The objective is to produce a soft-start reference voltage with a constant slope, essentially generating a voltage value that exhibits a linear relationship with the output voltage [16].

$${\mathrm{V}}_{\mathrm{OUT}}=f\cdot {\mathrm{V}}_{\mathrm{REF}}=\mathrm{K}\cdot {\mathrm{T}}_{\mathrm{SS}}$$

(1)

where V_OUT is the output voltage, f is the feedback coefficient, V_REF is the reference voltage, K is the sampling factor, and T_SS is the soft-start time.

After the completion of the chip’s establishment time, the soft-start enables signal EN_SS transitions from a high level to a low level. The sampling circuit begins operation, M₇ turns on, and the reference current flows through M₇ to inject the current into the sampling capacitor, C_SENSE. The positive terminal of the comparator is connected to the capacitive voltage divider network of V_FB, replacing the traditional resistive voltage divider network, which significantly reduces the trade-offs between area and power consumption. This allows the module to have extremely low quiescent power consumption when turned off. The resulting voltage obtained is the following:

$${\mathrm{K}}_1{\mathrm{V}}_{\mathrm{FB}}=\frac{{\mathrm{C}}_1}{{\mathrm{C}}_1+{\mathrm{C}}_2}\cdot {\mathrm{V}}_{\mathrm{FB}}$$

(2)

K₁ is the series voltage divider of C₁ and C₂, and V_FB is the feedback voltage.

At the same time, the right-hand side V_OUT generates a ramp voltage input to the negative terminal of the comparator through the RC network, which can be approximated in the first order as the following:

$$\{\begin{array}{l}{\mathrm{K}}_2{\mathrm{V}}_{\mathrm{OUT}}={\mathrm{V}}_{\mathrm{OUT}}\left(1-{\mathrm{e}}^{-{\mathrm{T}}_{\mathrm{O}\mathrm{N}}/{\mathrm{R}}_{\mathrm{R}}{\mathrm{C}}_3}\right)\approx {\mathrm{V}}_{\mathrm{OUT}}\cdot \frac{{\mathrm{T}}_{\mathrm{ON}}}{{\mathrm{R}}_{\mathrm{R}}{\mathrm{C}}_3}\\ {\mathrm{K}}_2{\mathrm{V}}_{\mathrm{OUT}}={\mathrm{K}}_1{\mathrm{V}}_{\mathrm{F}\mathrm{B}}\end{array}$$

(3)

K₂ is the coefficient for the first-order sampling of V_OUT, and T_ON is the sampling time.

When K₂V_OUT is higher than K₁V_FB, the comparator flips, and the overall sampling time ends with the final V_Ff equal to the following:

$$\{\begin{array}{l}{\mathrm{T}}_{\mathrm{O}\mathrm{N}}=\frac{{\mathrm{K}}_1{\mathrm{V}}_{\mathrm{F}\mathrm{B}}\cdot {\mathrm{R}}_{\mathrm{R}}{\mathrm{C}}_3}{{\mathrm{V}}_{\mathrm{OUT}}}={\mathrm{K}}_1\cdot {\mathrm{R}}_{\mathrm{R}}{\mathrm{C}}_3\cdot f\\ {\mathrm{V}}_{\mathrm{Ff}}=\frac{{\mathrm{I}}_{\mathrm{R}\mathrm{E}\mathrm{F}}\cdot {\mathrm{T}}_{\mathrm{ON}}}{{\mathrm{C}}_{\mathrm{SENSE}}}=\frac{{\mathrm{I}}_{\mathrm{R}\mathrm{E}\mathrm{F}}\cdot {\mathrm{K}}_1\cdot {\mathrm{R}}_{\mathrm{R}}{\mathrm{C}}_3\cdot f}{{\mathrm{C}}_{\mathrm{SENSE}}}={\mathrm{K}}_2\cdot f\end{array}$$

(4)

where f is the system feedback coefficient. From Equation (4), it can be seen that the final sampling voltage, V_Ff, obtained by removing the fixed term parameters such as passive components and reference current, is only linearly inversely proportional to the system feedback coefficient, f.

The designed sensing circuits are not unique, and other sensing circuits with higher reliability or higher accuracy can be used, as long as the same result is obtained in the end.

3.2. Fixed-Slope Reference

In the previous section, we obtained the sampled voltage with characteristics related to the feedback coefficient. In order to generate a soft-start time related to the feedback coefficient, as in Equation (1), we need to convert the obtained voltage into a time variable. As shown in Figure 4, the circuit diagram for generating the variable slope reference voltage is presented, where the core part of the circuit is a voltage-to-current conversion circuit. By enhancing the output impedance through negative feedback structure, a stable sampling current is generated, as follows:

$${\mathrm{I}}_{\mathrm{SS}}=\frac{{\mathrm{V}}_{\mathrm{Ff}}}{{\mathrm{R}}_{\mathrm{SS}}}$$

(5)

In order to integrate the soft-start capacitor into the chip for precise soft-start control, the conventional approach involves generating an nA-level charging current to ensure a certain soft-start time. This method significantly reduces the size of the soft-start capacitor. However, due to limitations such as process variations, the nA-level current produced by this approach is not stable. In applications where strict requirements exist for timing or start-up times, the resulting uncertainty in soft-start time from this method can have a significant impact.

In this paper, by using a CLK signal with a certain duty cycle, the continuous current is converted into a pulsed current. The equivalent charging current, I_eqv, can be expressed as the following:

$${\mathrm{I}}_{\mathrm{e}\mathrm{q}\mathrm{v}}={\mathrm{I}}_{\mathrm{S}\mathrm{S}}\cdot {\mathrm{D}}_{\mathrm{CLK}}$$

(6)

where D_CLK is the duty cycle of the CLK signal.

By adjusting the duty cycle, the equivalent value of the charging current can be significantly reduced, allowing for a substantial decrease in the capacitance value of the soft-start capacitor, C_SS, and enabling the integration of capacitors on chip.

As shown in Figure 5, the oscillator generates a clock with a fixed frequency, and the high pulse duration of the clock is controlled through a negative feedback mechanism. This allows for the generation of a relatively stable duty-cycle clock signal.

Substituting Equations (4)–(6) finally gives the fixed ramp soft start time as the following:

$${\mathrm{T}}_{\mathrm{SS}}=\frac{{\mathrm{C}}_{\mathrm{SS}}\cdot {\mathrm{V}}_{\mathrm{REF}}}{{\mathrm{I}}_{\mathrm{eqv}}}=\frac{{\mathrm{C}}_{\mathrm{SS}}\cdot {\mathrm{V}}_{\mathrm{REF}}\cdot {\mathrm{R}}_{\mathrm{SS}}}{{\mathrm{K}}_2\cdot {\mathrm{D}}_{\mathrm{CLK}}\cdot f}=\frac{{\mathrm{K}}^{\prime }\cdot {\mathrm{V}}_{\mathrm{REF}}}{f}$$

(7)

$${\mathrm{V}}_{\mathrm{S}\mathrm{LOPE}}=\frac{{\mathrm{V}}_{\mathrm{OUT}}}{{\mathrm{T}}_{\mathrm{SS}}}=\frac{1}{{\mathrm{K}}^{\prime }}$$

(8)

From Equation (7), it can be observed that the final soft-start time is linearly related to the reference voltage, V_REF, and the feedback coefficient, f. Regardless of whether the output voltage changes by altering the output voltage through, V_REF, or by modifying f, the output voltage will consistently increase with a fixed slope during the soft start.

From Equations (4), (5), and (7), it can be concluded that the first-order terms related to temperature and process in the charging current I_SS generated by the resistance and capacitance are eliminated in V_Ff/R_SS, achieving characteristics that are almost independent of Process, Voltage, and Temperature (PVT). Additionally, the final soft-start time, T_SS, includes an additional term, C_SS. Considering the very low temperature characteristics of MOM and MIM capacitors, the only variables affecting the soft-start time are process parameters. With a well-designed layout and the inclusion of trimming capacitance CTr, it is feasible to achieve a soft-start time with nearly zero PVT coefficient, dependent only on the reference voltage, V_REF, and feedback coefficient, f.

The trimming capacitor employs digital trimming, where a set of binary codes controls the bypass switches of CTr to perform switching actions. The magnitude of C_SS significantly influences the final soft-start time and the start-up slope of V_OUT. However, high absolute accuracy is not essential in this scenario. Additionally, as the capacitance of C_SS has already been minimized through current scaling, a basic control logic suffices for capacitor trimming.

In the circuit shown in Figure 4, a significant current spike occurs when the switch M₆ turns on. Since we have reduced the equivalent charging current and scaled the capacitance value, C_SS, accordingly, the impact of the current spike caused by the switch on generating the reference voltage becomes significant. This current spike will momentarily raise the voltage on the positive plate of C_SS when M₆ turns on. This effect will accumulate with each CLK cycle, leading to adverse effects on precise soft-start control.

A schematic diagram of the principle of voltage spike generation is given in Figure 6.

When the switch, SW, is open, the voltage at point D of M₄ drain will be pulled up to V_IN by the pull-up current. When the switch, SW, is closed, the voltage at point D will drop to the voltage value on the positive plate of C_SS. The parasitic capacitance at point D is mainly composed of the gate-drain capacitance, C_GD, of M₄ and the drain-body capacitance, C_DB. The change in charge for C_GD and C_DB before and after the switch operation is as follows:

$$\{\begin{array}{l}\Delta {\mathrm{V}}_{\mathrm{D}}=\Delta {\mathrm{V}}_{\mathrm{GD}}+\Delta {\mathrm{V}}_{D\mathrm{B}}=2\left({\mathrm{V}}_{\mathrm{I}\mathrm{N}}-{\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}\_\mathrm{C}\mathrm{S}}\right)\\ \Delta {\mathrm{Q}}_{\mathrm{D}}=\left({\mathrm{C}}_{\mathrm{G}\mathrm{D}}+{\mathrm{C}}_{\mathrm{D}\mathrm{B}}\right)\cdot \Delta {\mathrm{V}}_{\mathrm{D}}\\ \hspace{1em}\hspace{1em}=2\left({\mathrm{C}}_{\mathrm{G}\mathrm{D}}+{\mathrm{C}}_{\mathrm{D}\mathrm{B}}\right)\cdot \left({\mathrm{V}}_{\mathrm{IN}}-{\mathrm{V}}_{\mathrm{REF}\_\mathrm{CS}}\right)\end{array}$$

(9)

Therefore, the amount of change in C_SS voltage caused by each switching cycle is the following:

$$\begin{array}{l}\Delta {\mathrm{V}}_{\mathrm{SS}}=\Delta {\mathrm{Q}}_{\mathrm{D}}\cdot {\mathrm{C}}_{\mathrm{SS}}\\ \Delta {\mathrm{V}}_{\mathrm{SS}}=2\left({\mathrm{C}}_{\mathrm{G}\mathrm{D}}+{\mathrm{C}}_{\mathrm{D}\mathrm{B}}\right)\cdot \left({\mathrm{V}}_{\mathrm{I}\mathrm{N}}-{\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}\_\mathrm{C}\mathrm{S}}\right)\cdot {\mathrm{C}}_{\mathrm{SS}}\end{array}$$

(10)

From an interpretation of Equation (9), the methods to reduce current spikes essentially involve either reducing the size of parasitic capacitance or in minimizing the voltage difference across the parasitic capacitance before and after switching. Considering the requirements of the current mirror structure for output impedance, the space for improving parasitic capacitance is generally limited. Therefore, in this study, we address this issue by altering the voltage difference across the parasitic capacitance before and after switching.

The voltage spike elimination circuit designed in this paper, as shown in the red box part of Figure 4, operates based on the following principle: when the switching tube M₆ transitions from on to off, the original drain voltage of M₄ is pulled up to V_IN. At this moment, through the buffer M₄, the drain voltage is clamped to V_{REF_CS}. In the subsequent cycle, when M₄ turns back on, the voltage rise caused by the parasitic capacitance is reduced to almost zero. Only the remaining non-ideal effects, such as clock feedthrough and charge injection, are negligible compared to the size of C_SS.

Figure 7 illustrates the simulation verification of the current spike elimination circuit designed in this paper. The lower part of the figure shows the simulated waveforms of V_{REF_SS} and I_eqv after incorporating the current spike elimination circuit. It is evident that the current spike has been significantly reduced. The impact of this current spike on the overall slope of the generated reference voltage is approximately 1.5 times larger than the theoretical calculation, indicating a severely adverse effect on precise soft-start control.

3.3. Self-Off Reference Voltage Switching

The self-closing reference voltage switching circuit is given in Figure 8. It is mainly composed of a comparator and a D flip-flop.

When the chip-enabled terminal goes high, the internal reference and other modules will start up first. Once the reference voltage is established, the reset signal rises, and the switching circuit beings operating. When V_{REF_CS} is less than the internal reference voltage, V_REF, the comparator output, V_C, rises, causing EN_SS to transition to a low level. This initiates the fixed-slope soft-start module, enabling the switch M₁₁ and allowing the soft-start reference voltage to be input to the EA-positive terminal. When V_{REF_CS} exceeds the internal reference voltage, V_REF, the switch M₁₂ turns on, correctly inputting V_REF to the EA-positive terminal, thereby concluding the overall soft-start process. EN_SS then switches to a high level, closing all soft-start-related modules and enabling self-shutdown functionality, significantly reducing system static power consumption.

3.4. Pre-Biased Start-Up

When a power chip starts up, it faces two potential scenarios. In a loop without a soft-start, if the reference voltage significantly exceeds the feedback voltage, the high-side power transistor may remain on for an extended period, causing the inductor to generate damaging forward surge currents [17,18]. In a loop with a soft-start, if there is a pre-bias voltage across the load capacitor when the chip starts up, and the feedback voltage far exceeds the soft-start reference voltage. The low-side power transistor may remain on for an extended period, leading to the inductor creating a path from output to ground, generating damaging reverse-surge currents that can harm the chip.

Figure 9 presents a pre-bias start-up protection circuit. The input of the hysteresis comparator is connected to both the feedback voltage, V_FB, and the soft-start reference voltage, V_{REF_SS}. If V_FB is initially much higher than V_{REF_SS}, the hysteresis comparator outputs a low level. Subsequently, through the following logic circuit, the high-side and low-side power transistors are turned off. At this point, the soft-start circuit operates normally. Once V_{REF_SS} surpasses V_FB, the comparator outputs a high level, releasing control over the two power transistors.

Figure 10 shows the system simulation verification waveform when there is a pre-bias voltage. Assuming the pre-bias voltage is set to 1/2 of V_OUT, it can be observed that the soft-start reference voltage rises normally at a certain slope. During this stage, both the high-side and low-side power transistors are forcibly closed. Once the soft-start reference voltage exceeds the feedback voltage, the pre-bias protection circuit releases control over the power transistors, allowing the system to complete the soft-start process smoothly.

4. Simulation Results and Analysis

In this paper, the proposed circuit has been verified using layout design and full simulation based on a 0.18 μm BCD process, and Figure 11 shows the photo of the soft-start layout of the design in this paper, which has an area of 185 μm × 110 μm.

The designed Buck converter with ACOT architecture is suitable for most of the battery-powered systems at an input voltage of 2.5~5.5 V, and the output voltage range supports adjustments of 0.9~4 V, with a maximum carry current of 3 A, and the chip operates in power-saving mode with a quiescent power consumption of 16 μA.

The internal fixed-slope soft-start circuit controls the slope of the output voltage at start-up, which avoids excessive inrush currents and ensures a controlled output voltage rise time. Figure 12 and Figure 13 show the PVT simulation of the soft-start module’s reference voltage before trimming, setting V_OUT = 900 mV, V_FB = 600 mV, and a start-up slope of 5 mV/μs. Simulated wave form results with different colored lines representing different PVT conditions.

The change in slope caused by the drift of capacitance due to process variations is actually quite small. The primary objective of the fixed-slope soft start proposed in this paper is to generate a signal with a relatively high-precision fixed slope, ensuring that the final output voltage rises at a constant rate. In the face of slope variations under different process angles, the output voltage will simply rise at other fixed slopes, without transitioning to a non-fixed slope.

Figure 14 gives a visual representation of the PVT characteristics of the slope of the reference voltage generated by the soft-start circuit. The reference voltage slope reaches a maximum deviation of 1.6% at the FF process angle and −40 °C.

It can be seen that the slope of the reference voltage is able to remain essentially independent of the temperature and the supply voltage under the process angle SS/TT/FF determination.

It can also be concluded that under the PVT validation results, the final output slope remains basically consistent.

The output voltage waveforms of the Buck converter with an on-chip integrated fixed-slope soft-start mechanism are given in Figure 15. Since the soft-start reference voltage includes variables such as feedback coefficients, the system is capable of soft-starting at a fixed slope of 5 mV/μs within the output voltage of 0.9~4 V, with a slope control accuracy of more than 98%.

Figure 16 shows the soft-start related waveforms of the chip with or without a soft start circuit. Since the system waveforms of the chip are without/with soft start, it can be seen that the peak inductor current without soft-start can be up to 6.8 A. With the soft-start inductor current under the start of the two load states having no significant overshoot, the peak inductor current under full load can be up to 3.8 A, and the overall inrush current is reduced by 44%. Under the action of the self-shutdown circuit, the overall static power consumption of the module is less than 2 nA after the completion of the soft-start.

Table 1. References comparison.

Parameter.	This Work	Ref. [8]	Ref. [9]	Ref. [10]	Ref. [11]
Process	180 nm BCD	500 nm CMOS	/	350 nm CMOS	180 nm CMOS
Area/mm2	0.020	0.018	/	0.022	/
Soft start Time/μs	/	5500	1500	380	90
Output Voltage Range/V	0.9~4	3~12	18	12~45	1.2~2
Maximum load current/mA	3000	400	120	500	200
Soft start Capacitance/pF	2.5	3.1	0	5	0
Load capacitance/μF	22	20	4.7	20	10
Start-up reliability	High	Low	Low	Low	Low
Control Method	Sampling-based analog control	Counter-based digital control	Counter-based digital control	Analog control for current-limiting feedback	Fixed delay digital control
Soft-start slope/(mV/μs)	5 ± 5%	0.55~2.2	/	31~118	13~22

provides a validation comparison of the fixed-slope soft-start method designed in this paper. As the essence of the soft-start circuit is to solve the problem of excessive inrush current during start-up. It is clear from the analysis in Section 1 that the traditional fixed-time soft-start circuit may face the occurrence of large inrush current when configured with different output voltages for start-up, and the design of this paper’s fixed-slope soft-start effectively circumvents this problem. Therefore, Table 1 compares only the start-up slopes to determine whether or not the designed converter has the occurrence of a configuration with a different risk of inrush current when starting with different output voltages. In addition, the designed method in this paper is simple. In the modification of off-chip feedback coefficients to adjust the output voltage on the introduction of a fixed slope soft-start function, the internal integration of the soft-start capacitance is as low as 2 pF, ensuring that, in the output voltage in the overall output voltage range of the maximum load conditions, the output voltage can be a fixed slope smoothly into the steady-state stage. The item of start-up reliability in the Table refers to the risk of soft start under the most adverse start-up conditions, such as whether there is a risk of excessive stress on power devices when starting at the maximum output voltage of a fully loaded system.

5. Conclusions

This paper addresses the issue of different power stresses when a traditional fixed-time soft-start is applied to different output voltages. To solve this problem, a fixed-slope soft-start circuit integrated on-chip for Buck converters is proposed. The soft-start circuit effectively eliminates the surge current generated during start-up under full load (3 A) and no-load (0 A) conditions. The overall surge current is reduced by 44%, and the output voltage smoothly rises and transitions into a steady-state operation phase. This verifies the feasibility and reliability of the proposed fixed-slope soft start and the overall architecture.