Mobility Extraction Using Improved Resistance Partitioning Methodology for Normally-OFF Fully Vertical GaN Trench MOSFETs

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

This paper investigated mobility extraction of the trench-channel and trench-bottom mobility in the vertical trench-MOSFETs by using the resistance partitioning method. However, I have some questions about mobility calculation and results like below. So, this paper would be acceptable after answering these questions.

1. In Figure 1 (a), the gate is not expressed in the trench. Please check the figure.

2. ID-VDS output characteristics are not shown in the manuscript, so please show it.

3. Why is VGS different in calculating Rtot (VG = 2.5 V) and effective mobility (VGS = 3 V)? I think Rtot value is different according to VGS, if so, the mobility will be affected by VGS.

 

4. In calculating trench-channel mobility, is there no effect on the channel length? Please explain why the channel length is not considered in the equation of mobility.

Comments on the Quality of English Language

The English is well-written for publication.

Author Response

Thank you for your review of our publication. Here are the modifications related to each of your points, that I applied on the article :

1. Addition of a Gate label in Fig. 1a.
   2. Addition of I_D-V_DS output characteristics as Fig. 3c
   3. Modification of V_G = 2.5V to V_G = 3V in Fig. 5b. This was a mistake on my side, as I indeed calculated the effective mobility in this voltage condition (3V)

Here is my answer to the question asked in point 4. ("In calculating trench-channel mobility, is there no effect on the channel length? Please explain why the channel length is not considered in the equation of mobility") :
If you talk about the channel length, you must talk about the thickness of the p-GaN (blue layer in Fig.1). In our methodology, the channel mobility is calculated thanks to equation (3). This equation is based-on the assumption that we have already a uniform carrier density through the whole p-GaN layer (blue layer in Fig.1a). So we assume by definition that the channel mobility depends only on the p-GaN doping and its uniformity and not on the channel length.
Moreover, you can also notice that since we have a linearity of the R_ON with W_tr in Fig. 5b., we can already deduce the charge uniformity along the channel length of the p-GaN layer.

 

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

In this paper, the authors present the fabrication, characterization, and extraction of parameters for the trench bottom and trench-channel of fully-vertical GaN trench MOSFETs. The motivation behind the work and the fabrication process are clearly described, but the mobility extraction could be more rigorous.

 

1.      The authors use Vd = 2V for threshold voltage (Vth) extraction and Vs = 3V for integrating charge density. Please explain the reason for the choice of Vd and Vs, especially when mobility extraction is typically performed in the linear regime with low Vds to maintain a uniform charge distribution along the channel and suppress the diffusion current.   

2.      Determining Vth is crucial. The authors should provide detailed information about the linear fit used, including the range over which the fit was applied and the quality of the fit. Similarly, for calculating the total charge, the determination of the limit of CV integral, Vonset, should be clearly explained too.

3.      Rbot is determined by fitting the slope of Rtotal versus trench width. To improve the accuracy of this linear fitting, more data points should be included for each trench width to show the statistical distribution. It would also be beneficial to vary the trench widths beyond the current three data points, particularly extending to smaller widths below 1 μm to better approach the y-intercept. With more data points and their statistical distribution, the quality of the fit and the errors in the fitted values for 2Rs + 2Rch can be reported.

4.      Please include details on the extraction of Rs using TLM structures, such as the range of Lch used and the quality of the fit.

5.      All extracted resistance values should include error bars to indicate their precision.

6.      The paper mentions that the extracted trench-bottom and channel mobilities are low. It would be helpful to provide a benchmark for channel mobility, comparing it with state-of-the-art values and typical mobilities reported for GaN trench-MOSFETs. This comparison will help contextualize the reported values.

Author Response

Thank you for your review of our publication. Here are the modifications related to each of your points, that I applied on the article :

1. Addition of correlation factor r on Fig. 3a. , Fig. 5b, and Fig. 6 to show the quality of the fit (Vth extrapolation, Ron vs Wtr, TLM measurements)
   2. Precision of the CV integral limits (V_onset values) of the Vonset for the transistor (device A) and the planar capacitor (device B) in lines 167-171.
   4. Addition of TLM results, giving to the reader results on the fitting quality and resistances components (access, contact, source)
   6. Addition of a benchmark at the end of the publication comparing the mobilities of the state of the art and the ones of the article

 

Here are my answers for the questions asked in points 1., 2., 3., :

1. “The authors use Vd = 2V for threshold voltage (Vth) extraction and Vs = 3V for integrating charge density. Please explain the reason for the choice of Vd and Vs, especially when mobility extraction is typically performed in the linear regime with low Vds to maintain a uniform charge distribution along the channel and suppress the diffusion current.“

The choice of V_D = 2V has been chosen arbitrarily only to have an idea of the V_th value of a given transistor.
Differently, the choice of V_S = 3V as been chosen in order to be related to the linear inversion regime of a transistor in the Id-Vd output characteristic. Indeed, if we refer at the added Fig. 3c, one can see that we are in the inversion regime at V_G = 3V and V_D = 0.5V.

 

2. “Determining Vth is crucial. The authors should provide detailed information about the linear fit used, including the range over which the fit was applied and the quality of the fit. Similarly, for calculating the total charge, the determination of the limit of CV integral, Vonset, should be clearly explained too.”
   V_th extrapolation
   To determine the V_th, an extrapolation of the linear fit in the inversion regime was applied, as shown in Fig. 3a. The fitting is done from 1.73V to 2.26V with 5 points, for the transfer curve related to V_D = 2V. A correlation factor r is found to be equal to 0.99.

 

3. “Rbot is determined by fitting the slope of Rtotal versus trench width. To improve the accuracy of this linear fitting, more data points should be included for each trench width to show the statistical distribution. It would also be beneficial to vary the trench widths beyond the current three data points, particularly extending to smaller widths below 1 μm to better approach the y-intercept. With more data points and their statistical distribution, the quality of the fit and the errors in the fitted values for 2Rs + 2Rch can be reported.”

-Statistical distribution proposition
I understand your point. However, please note that for Fig. 5b (Ron vs Wtr) aims to shows only to a typical set of transistors with different W_tr.

-Width extension below 1µm
Our initial layout is limited to the fabrication of transistors featuring gate trench width (W_tr) from 1µm to 6µm, by steps of 1µm. This indeed limits the precision of the study and brings some uncertainty about the intercept of the R_ON when W_tr tends to 0.

 

5. “All extracted resistance values should include error bars to indicate their precision.”

Again, your point is valid. However, Fig. 5b (Ron vs Wtr) aims to shows only to a typical set of transistors with different W_tr.

Reviewer 3 Report

Comments and Suggestions for Authors

This paper presents a study on improving electrical performance of GaN based MOSFET by utilizing a vertical trench structure. My recommendation is to publish after addressing the following comment:

1. In this study, Al2O3 was deposited as the gate dielectric and followed by a RTA at 400C in the end of deposition. Could authors comment if any Al diffusion will occur in this case to introduce more trap states? and if any other dielectric e.g. Hf(Al)O2 could be used to further optimize the electrical performance

2. From Figure 2 STEM images, could authors provide more quantitative conformality/step coverage of Al2O3 and TiN since the thickness variation is still observed from Figure 2b, and could authors comment on what could be the issue when lacking the conformality.

3. For Figure 5b, Vg should be 3V as indicated in context.

 

Author Response

Thank you for your review of our publication. Here are the modifications related to each of your points, that I applied on the article :

3. Modification of V_G = 2.5V to V_G = 3V in Fig. 5b. This was a mistake on my side, as I indeed calculated deduced the effective mobility in this voltage condition (3V).

 

Here are my answers for the questions asked in points 1. and 2. Additionnal references linked to my answers are listed for each points :

1. “In this study, Al₂O₃ was deposited as the gate dielectric and followed by a RTA at 400C in the end of deposition. Could authors comment if any Al diffusion will occur in this case to introduce more trap states? and if any other dielectric e.g. Hf(Al)O2 could be used to further optimize the electrical performance”

Al diffusion
To the best of our knowledge, no Al diffusion into the GaN seems to occur at 400°C. This can be corroborate especially by the works of Pedro & al. [1], [2] and Tadmor & al. [3] on MOS structures, where no Al diffusion into the GaN as been observed even at post—deposition annealing of 400-600°C.

Alternative dielectric of Al2O3
Other gate dielectrics could be used to replace the Al₂O₃ and optimize the MOSFET electrical performances. Among them, the following dielectrics could be great candidates to answer this problematic :
-HfAlO₂ could be used to enhance the permittivity of the dielectric, and so, improving the oxide capacitance, transconductance, as-well-as the channel mobility of the device. [4]
-AlON has proved to improve the dielectric/GaN interface (reduction of V_FB hysteresis, gate leakage, charge injection) [3] [5] [6], and improving the thermal budget (T_{cristallization} ~ 1000°C) for the transistor fabrication.
-AlSiO has demonstrated that the Si concentration in its matrix allows to reduce the leakage current due to a higher conduction barrier [7], as well as reducing the Vth / VFB hysteresis [8]. Higher thermal stability (crystallization at ~950°C) compared to Al₂O₃ has also been observed for that dielectric

 

 

[1] : P. Fernandes Paes Pinto Rocha, L. Vauche, B. Mohamad, W. Vandendaele, E. Martinez, M. Veillerot, T. Spelta, N. Rochat, R. Gwoziecki, B. Salem, V. Sousa, Impact of post-deposition anneal on ALD Al2O3/etched GaN interface for gate-first MOSc-HEMT, Power Electronic Devices and Components, Volume 4, 2023, 100033, ISSN 2772-3704
[2] : Liad Tadmor et al 2023 Semicond. Sci. Technol. 38 015006
[3] : Pedro Fernandes Paes Pinto Rocha. Optimization of dielectric/GaN interface for MIS gate power devices. Electric power. Université Grenoble Alpes [2020-..], 2023. English. ffNNT : 2023GRALT074ff. fftel-04496081f
[4] : Takuji Hosoi et al 2020 Jpn. J. Appl. Phys. 59 021001
[5] : Kojima, E.; Chokawa, K.; Shirakawa, H.; Araidai, M.; Hosoi, T.; Watanabe, H.; Shiraishi, K. Effect of Incorporation of Nitrogen 1042 Atoms in Al2O3 Gate Dielectric of Wide-Bandgap-Semiconductor MOSFET on Gate Leakage Current and Negative Fixed Charge. 1043 Appl. Phys. Express 2018, 11, 061501
[6] : Mikito Nozaki, Kenta Watanabe, Takahiro Yamada, et al. “Implementation of Atomic Layer Deposition-Based AlON Gate Dielectrics in AlGaN/GaN MOS Structure and Its Physical and Electrical Properties”. In: Jpn. J. Appl. Phys. 57 (6S3 June 1, 2018), 06KA02. ISSN: 0021-4922, 1347-4065.
[7] : Daigo Kikuta, Kenji Itoh, Tetsuo Narita, et al. “Al2O3/SiO2 Nanolaminate for a Gate Oxide in a GaN-based MOS Device”. In: Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 35.1 (Dec. 2016), 01B122. ISSN: 0734-2101, 1520-8559
[8] : Chirag Gupta, Silvia H. Chan, Anchal Agarwal, et al. “First Demonstration of AlSiO as Gate Dielectric in GaN FETs; Applied to a High Performance OG-FET”. In: IEEE Electron Device Lett. 38.11 (Nov. 2017), pp. 1575–1578. ISSN: 0741-3106, 1558-0563. DOI: 10 . 1109 / LED . 2017.2756926.

 

2. “From Figure 2 STEM images, could authors provide more quantitative conformality/step coverage of Al2O3 and TiN since the thickness variation is still observed from Figure 2b, and could authors comment on what could be the issue when lacking the conformality.”

Quantitative conformability coverage of Al2O3 and TiN
-In our case, we do not expect any difference in conformity for the Al2O3 gate dielectric and the TiN gate metal.

Issues encountered when lacking conformability
-Lacking the conformability could induced different issues :
Firstly, it could impact the gate breakdown due to sharp non inhomogeneitis on the sidewalls as well as non-uniform gate dielectric thickness.
Secondly, since the gate dielectric thickness could be non-uniform in these areas, difference in capacitance could be expected in local areas, influencing directly the channel mobility.
Finally, since the V_th is related to the t_ox, a non-uniform gate dielectric thickness would have a detrimental impact on the V_th value

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

Thank you for your answer. This paper is well organized so it can be published as it is.