Double-Loop Controller Design of a Single-Phase 3-Level Power Factor Correction Converter

Abstract

This paper presents a study on the double-loop controller design technique for a single-phase power factor correction (PFC) three-level (TL) boost converter. Designing a double-loop controller using conventional methods is challenging due to the 120 Hz voltage ripple in the output voltage. This study proposes new double-loop control design methods using a band-stop filter and MATLAB SISOTOOL, detailed in a step-by-step sequence. A band-stop filter with a 120 Hz stop band is applied to the double-loop controller design. Modeling based on the state-space equation, applicable to the full duty range, is constructed to obtain the transfer function. The double-loop controller structure is then designed, and optimal gains that satisfy the design requirements are obtained through automatic tuning using the MATLAB SISOTOOL library. The simulation results demonstrate the performance of the proposed method, which is further verified by experimental results.

1. Introduction

Global population growth, economic growth, industrialization, and technological advancements continue to increase the demand for today’s limited energy resources. Electronic systems, in particular, account for a significant portion of energy consumption. Efficient management and conservation of these systems can significantly contribute to energy savings and cost reduction. In response to the growing demand for limited energy resources and rising energy prices, improving power efficiency in electronic systems has become a critical challenge.

In recent years, research on efficient energy conversion technologies has been active, and power factor correction (PFC) has garnered significant attention, particularly for single-phase PFC. Power factor correction offers several benefits, including improved power quality, increased energy efficiency, and reduced power losses.

The circuit to implement a single-phase PFC consists of a voltage controller to regulate the direct current (DC) voltage at the output and a current controller to control the alternating current (AC) at the input, maintaining it in a sinusoidal wave to achieve a nearly uniform power factor. The detailed configuration is presented in Section 3, “Double Loop Controller Design”. In a single-phase PFC system, there is only one power source. Therefore, the single-phase AC is passed through an all-pass filter (APF) to create a virtual AC with a 90-degree phase shift. This virtual AC is then converted to DC through a d-q conversion for control purposes. With d-q conversion, alternating current is effectively converted to direct current, allowing for control and regulation in a single-phase PFC system [1]. This approach is widely used due to its high efficiency, simple topology, continuous input current, and step-up voltage conversion ratio. Another approach could involve using the instantaneous AC control method; however, this approach may introduce steady-state errors.

Single-phase PFC systems often utilize boost converters to leverage these benefits. Boost converters are preferred in single-phase PFCs because they can adjust the output voltage by boosting it while maintaining a high power factor.

However, with the recent increase in the use of high-power applications, the use of single-level boost converters in PFC circuits has increased the volume and weight of the inductor, and losses in the power devices have become a major factor affecting the cost and efficiency of the converter. These applications are energy-intensive and consume significant power from the power network. High-power applications, such as electric vehicles, electric buses, railroad cars, power plants, substations, and distribution systems in energy production, as well as distribution systems for electric vehicles, require substantial power.

To compensate for the disadvantages of the single boost converter structure, the application of a boost converter with a three-level (TL) structure to PFC has been studied as a possible solution [2,3,4,5]. Compared to conventional boost converters, TL boost converters offer higher efficiency and a wider control range. However, since single-phase PFC circuits generate a 120 Hz ripple at the output, designing a double-loop controller is challenging. This challenge is further compounded when adopting a TL boost converter structure. Previous research has utilized notch filters or lead-lag compensators to compensate for the 120 Hz ripple. However, these methods can potentially induce instability and complicate the design of a double-loop controller [6].

This paper presents the results of a study in which a single-phase PFC double-loop controller design technique, accommodating the 120 Hz ripple, is applied to a TL boost converter. After constructing the state-space equations applicable to the entire duty range to obtain the transfer function, a double-loop controller was designed using MATLAB SISOTOOL. The validity of the designed controller was verified through PSIM simulations and experimental results.

2. System Modeling

The circuit diagram of the single-phase three-level (TL) PFC converter with a diode bridge rectifier is shown in Figure 1. This configuration has the disadvantage of an increased number of semiconductor switches, diodes, and capacitors due to the cascade connection compared to the two-level configuration. However, it also has advantages, such as a reduced volume and weight of the inductor and reduced voltage stress on the semiconductor switches. In fact, the three-level configuration can reduce the voltage ratings of the semiconductor switches and diodes to half of those in the two-level configuration. Therefore, the three-level PFC converter can significantly reduce material costs.

The dynamic mathematical model of the TL PFC converter can be obtained by analyzing the switch operations. The equivalent circuit of the TL PFC converter is divided into four operating states according to the switching operation, as shown in Figure 2. The state when both switches, SW₁ and SW₂, are off is shown in Figure 2a. The state when SW₁ is on while SW₂ is off is shown in Figure 2b. The state when SW₁ is off, and SW₂ is on is shown in Figure 2c. Finally, Figure 2d depicts the state when both switches, SW₁ and SW₂, are on.

The average state space equation can be derived by analyzing the operation mode determined by the duty boundary of 0.5. When the duty cycle is less than 0.5, it is defined as Mode 1. The operating sequence for Mode 1 is State 1 → State 2 → State 1 → State 3, as depicted in Figure 3a. Conversely, when the duty cycle is greater than 0.5, it is defined as Mode 2. The operating sequence for Mode 2 is State 4 → State 3 → State 4 → State 2, as shown in Figure 3b. Since the system control involves two operation modes with a duty boundary of 0.5, it is necessary to analyze their operations for both modes. The state space equations for each state are summarized in

Table 1. The summary of the state space equation for each operation states.

State 1: [SW1, SW2 OFF] $\mathrm{Operation} \mathrm{time}: (1-2d$$)Ts$ $$\begin{array}{c}{\dot{\dot{l}}}_L={\displaystyle \frac{v_{in}}{L}}-{\displaystyle \frac{\left(v_{C1}+v_{C2}\right)}{L}}\\ {\dot{v}}_{c1}={\displaystyle \frac{i_L}{C_1}}-{\displaystyle \frac{(v_{C1}+v_{C2})}{R{C}_1}}\\ {\dot{v}}_{c2}={\displaystyle \frac{i_L}{C_2}}-{\displaystyle \frac{\left(v_{C1}+v_{C2}\right)}{R{C}_2}}\end{array}$$ (1)

State 2: [SW1 ON, SW2 OFF] $\mathrm{Operation} \mathrm{time}: (d$$)Ts$ $$\begin{array}{c}{\dot{\dot{l}}}_L={\displaystyle \frac{v_{in}}{L}}-{\displaystyle \frac{v_{C2}}{L}}\\ {\dot{v}}_{c1}=-{\displaystyle \frac{\left(v_{C1}+v_{C2}\right)}{R{C}_1}}\\ {\dot{ v}}_{c2}={\displaystyle \frac{i_L}{C_2}}-{\displaystyle \frac{\left(v_{C1}+v_{C2}\right)}{R{C}_2}}\end{array}$$ (2)

State 3: [SW1 OFF, SW2 ON] $\mathrm{Operation} \mathrm{time}: (1-d$$)Ts$ $$\begin{array}{c}{\dot{\dot{l}}}_L={\displaystyle \frac{v_{in}}{L}}-{\displaystyle \frac{v_{C1}}{L}}\\ {\dot{v}}_{c1}={\displaystyle \frac{i_L}{C_1}}-{\displaystyle \frac{(v_{C1}+v_{C2})}{R{C}_1}}\\ {\dot{v}}_{c2}=-{\displaystyle \frac{\left(v_{C1}+v_{C2}\right)}{R{C}_2}}\end{array}$$ (3)

State 4: [SW1, SW2 ON] $\mathrm{Operation} \mathrm{time}: (2d-1$$)Ts$ $$\begin{array}{c}{\dot{\dot{l}}}_L={\displaystyle \frac{v_{in}}{L}}\\ {\dot{v}}_{c1}=-{\displaystyle \frac{\left(v_{C1}+v_{C2}\right)}{R{C}_1}}\\ {\dot{v}}_{c2}=-{\displaystyle \frac{\left(v_{C1}+v_{C2}\right)}{R{C}_2}}\end{array}$$ (4)

.

The state-averaging equations can be calculated by multiplying the state equations and their operation time for each Mode. The resultant state-averaging equations are the same for Mode 1 and Mode 2 and can be expressed as displayed in (5).

$$\left(\begin{array}{c}{\dot{\dot{l}}}_L\\ {\dot{v}}_{c1}\\ {\dot{v}}_{c2}\end{array}\right)=\left(\begin{array}{ccc}0& -{\displaystyle \frac{\left(1-d\right)}{L}}& -{\displaystyle \frac{\left(1-d\right)}{L}}\\ -{\displaystyle \frac{\left(1-d\right)}{C_1}}& -{\displaystyle \frac{1}{R{C}_1}}& -{\displaystyle \frac{1}{R{C}_1}}\\ -{\displaystyle \frac{\left(1-d\right)}{C_2}}& -{\displaystyle \frac{1}{R{C}_2}}& -{\displaystyle \frac{1}{R{C}_2}}\end{array}\right)\left(\begin{array}{c}{i}_L\\ v_{C1}\\ v_{C2}\end{array}\right)+\left(\begin{array}{c}{\displaystyle \frac{1}{L}}\\ 0\\ 0\end{array}\right)v_{in}$$

(5)

The state-averaging equation of Mode 1 is the same as that of Mode 2, which means that mode transition does not need to be considered when designing the controller. This means that the above equation can be applicable to the full duty range. However, since the above equation includes duty, that is, a variable that changes with time, linearization at the operating point is necessary [7,8,9,10,11]. By applying small signal perturbation for linearization at the operating point, the following linearized equation can be obtained:

$$\left(\begin{array}{c}{\widehat{i}}_L\\ {\widehat{\dot{v}}}_{c1}\\ {\widehat{\dot{v}}}_{c2}\end{array}\right)=\left(\begin{array}{ccc}0& -{\displaystyle \frac{(1-D)}{L}}& -{\displaystyle \frac{(1-D)}{L}}\\ {\displaystyle \frac{(1-D)}{C_1}}& -{\displaystyle \frac{1}{R{C}_1}}& -{\displaystyle \frac{1}{R{C}_1}}\\ {\displaystyle \frac{(1-D)}{C_2}}& -{\displaystyle \frac{1}{R{C}_2}}& -{\displaystyle \frac{1}{R{C}_2}}\end{array}\right)\left(\begin{array}{c}{\widehat{l}}_L\\ {\widehat{v}}_{c1}\\ {\widehat{v}}_{c2}\end{array}\right)+\left(\begin{array}{c}{\displaystyle \frac{(V_{c1}+V_{c2})}{L}}\\ -{\displaystyle \frac{I_L}{C_1}}\\ -{\displaystyle \frac{I_L}{C_2}}\end{array}\right)\widehat{d}$$

(6)

If assuming that capacitor $C_1$ and $C_2$ are equal in the small signal analysis equation, it can be expressed as a quadratic equation, and, thus, a simple controller design is possible. The capacitor imbalance occurs in actual applications. Therefore, the capacitor voltage balancing controller is required for the reduced quadratic equation. The balancing controller design is shown in the controller design section. The final linearized state space equation is shown as follows:

$$\left(\begin{array}{c}{\dot{\dot{l}}}_L\\ {\dot{v}}_{c0}\end{array}\right)=\left(\begin{array}{cc}0& -{\displaystyle \frac{(1-D)}{L}}\\ {\displaystyle \frac{(1-D)}{C_0}}& -{\displaystyle \frac{1}{R{C}_0}}\end{array}\right)\left(\begin{array}{c}{i}_L\\ v_{C0}\end{array}\right)+\left(\begin{array}{c}{\displaystyle \frac{1}{L}}\\ 0\end{array}\right)v_{in}$$

(7)

And the derived steady-state DC values of $V_{C0}$, $I_L$ are shown in (8).

$$I_L={\displaystyle \frac{V_{in}}{R(1-D)}},V_{C0}={\displaystyle \frac{V_{in}}{(1-D)}}$$

(8)

The input–output transfer function equation for voltage and current controller design can be obtained from the Laplace transform and is shown in the following equations from (9) to (11):

$${\displaystyle \frac{{\widehat{l}}_L(s)}{\widehat{d}(s)}}=G_1\left(s\right)={\displaystyle \frac{\frac{V_{C0}}{L}s+\frac{V_{C0}}{R{C}_{0}L}+\frac{I_L}{L{C}_0}(1-D)}{s^2+\frac{1}{R{C}_0}+\frac{1}{L{C}_0}{(1-D)}^2}}$$

(9)

$${\displaystyle \frac{{\widehat{v}}_{co}(s)}{\widehat{d}(s)}}=G_2\left(s\right)={\displaystyle \frac{-\frac{I_L}{C_0}s+\frac{V_{C0}}{L{C}_0}(1-D)}{s^2+\frac{1}{R{C}_0}+\frac{1}{L{C}_0}{(1-D)}^2}}$$

(10)

$${\displaystyle \frac{{\widehat{v}}_{c0}(s)}{{\widehat{l}}_L(s)}}=G_3\left(s\right)={\displaystyle \frac{-\frac{I_L}{C_0}s+\frac{V_{C0}}{L{C}_0}(1-D)}{\frac{V_{C0}}{L}s+\frac{V_{C0}}{R{C}_{0}L}+\frac{I_L}{L{C}_0}(1-D)}}$$

(11)

3. Double-Loop Controller Design

The configuration of the single-phase PFC controller consists of a double-loop structure, as illustrated in Figure 4. It comprises a voltage controller for regulating the DC output voltage in the outer loop and a current controller for ensuring the power factor remains close to unity by controlling the current of the AC input terminal as a sine wave in the inner loop. In single-phase PFC control, the Proportional-Integral (PI) controller cannot be directly applied to the current controller because the current waveform is sinusoidal, not DC. Conventional methods often use an instantaneous AC current controller that adopts a Proportional (P) controller. However, these methods may fail to achieve zero steady-state error and can be problematic when there are abrupt changes in the command or disturbances in the environment.

To achieve zero steady-state error, a PI current controller using DQ transformation can be applied. However, this transformation typically requires at least two sources, which poses a challenge in single-source systems. To overcome this limitation, a virtual 90-degree phase-shifted signal is created. This can be achieved by using a virtual power source or implementing a filter such as an All Pass Filter (APF) [12]. This paper explores the use of APF to facilitate single-phase DQ conversion.

The detailed control block diagram of the outer loop, regulating the output voltage, and the inner loop, controlling the inductor current, is depicted in Figure 4. The output of the voltage controller, $I_{L\_ref}$ (inductor current reference), is generated through voltage control at the DC output stage. However, in single-phase PFC, voltage ripple occurs at twice the AC input power frequency and manifests in the DC link voltage [13,14]. This ripple not only complicates voltage control but also impacts current control, posing challenges in designing single-phase PFC controllers and determining PI gain values. To address this issue, this paper proposes the use of a band-stop filter in voltage control to suppress the 120 Hz DC voltage ripple. The equation for the Band-stop filter is expressed in (12).

$$BSF={\displaystyle \frac{s^2+{{\omega }_0}^2}{s^2+Bs+{{\omega }_0}^2}}$$

(12)

From (12), the equations for the stop-band frequency, B and ${\omega }_0$, can be obtained through (13) and (14), respectively. $f_b$ represents the stop-band frequency, and $f_c$ represents the reference frequency [15].

$$f_b={\displaystyle \frac{B}{2\pi }}\to B=2\pi f_b$$

(13)

$$f_C={\displaystyle \frac{{\omega }_0}{2\pi }}\to {\omega }_0=2\pi f_c$$

(14)

By using (13) and (14), the values corresponding to each frequency can be calculated. The transformation from the s-domain (continuous) to the z-domain (discrete), is shown in (15) which is derived by substituting s with ${\displaystyle \frac{2}{T}}{\displaystyle \frac{1-z^{-1}}{1+z^{-1}}}$ in the s-domain equation and expanding it.

$$BSF\left(Z\right)={\displaystyle \frac{\left(\frac{4}{T^2}+{{\omega }_0}^2\right)+\left(-\frac{8}{T^2}+{2{\omega }_0}^2\right)z^{-1}+\left(\frac{4}{T^2}-\frac{2{\omega }_0}{2T}+{{\omega }_0}^2\right)z^{-2}}{\left(\frac{4}{T^2}+\frac{2{\omega }_0}{2T}+{\omega }_0\right)+\left(-\frac{8}{T^2}+{2{\omega }_0}^2\right)z^{-1}+\left(\frac{4}{T^2}-\frac{2{\omega }_0}{2T}+{{\omega }_0}^2\right)z^{-2}}}$$

(15)

The 120 Hz ripple can be effectively removed using a band-stop filter, as described by Equation (15). The selected parameters are $f_b$ = 9.55 [Hz] and $f_C$ = 120 [Hz]. Equation (15) has been implemented on a microcontroller, such as a Digital Signal Processor (DSP), using C-code programming. The filter can be applied to both 50 Hz and 60 Hz frequencies by adjusting the parameters of the band-stop filter (BSF). While the manuscript focuses on 60 Hz operation due to its relevance to the grid system used, the flexibility to accommodate both frequencies is noted. Adjusting the BSF parameters enables straightforward adaptation to 50/60 Hz operation.

For the design of the voltage controller, specifications are set with a phase margin of 90 degrees and a bandwidth of 50 [rad/s]. The optimal gains that satisfy these design specifications are automatically determined using the MATLAB SISOTOOL library. The transfer function of the final designed voltage controller can be expressed as shown in Equation (16).

$$G_{cv}(s)=0.2015\times {\displaystyle \frac{s+16.2}{s}}$$

(16)

The resultant Bode plot for the designed voltage controller is presented in Figure 5. It can be observed that the phase margin is 90.1 degrees, and the bandwidth is 50.2 [rad/s], meeting the specified design criteria. Therefore, the stability of the system can be confirmed through the Bode plot analysis.

In the current control configuration, an APF is used to create a virtual 90-degree phase axis, enabling the design of a single-phase DQ transformation. The APF used in the current controller is a mathematical equation that introduces a phase delay without altering the magnitude of the input signal. It became a transfer function with a magnitude of one across all frequency bands and a phase delay ranging from 0 to 180 deg. (1-pole filter). By utilizing the APF, the actual current axis I_α and the virtual current axis I_β were generated, as expressed in Equation (17) [16,17]. The DQ transformation formula based on (17) is described in (18).

In the current control configuration, an All Pass Filter (APF) is employed to generate a virtual 90-degree phase axis, facilitating the design of a single-phase DQ transformation. The APF utilized in the current controller is a mathematical equation that introduces a phase delay while preserving the magnitude of the input signal. It operates as a transfer function with a magnitude of one across all frequency bands and introduces a phase delay ranging from 0 to 180 degrees (a 1-pole filter). By utilizing the APF, both the actual current axis I_α and the virtual current axis I_β are generated, as expressed in Equation (17). The DQ transformation formula based on Equation (17) is described in Equation (18).

$$I_{\alpha }\left(k\right)=I_L$$

$$I_{\beta }\left(k\right)=0.9813·I_{\beta }\left(k-1\right)+0.9813I_L\left(k\right)-I_L\left(k-1\right)$$

(17)

$$\left[\begin{array}{c}{I}_{Ld}\\ I_{Lq}\end{array}\right]=\left[\begin{array}{cc}cos\theta & sin\theta \\ -sin\theta & cos\theta \end{array}\right]\left[\begin{array}{c}{I}_{\alpha }\\ I_{\beta }\end{array}\right]$$

(18)

Current control is achieved through the use of an APF and DQ transformation. The design specifications for the current controller are set with a phase margin of 60 degrees and a bandwidth of 4800 [rad/s]. The transfer function of the designed current controller is expressed in Equation (19).

$$G_{ci}=0.019522\times {\displaystyle \frac{s+2690}{s}}$$

(19)

The Bode plot for the current controller is presented in Figure 6. It can be observed from the plot that the phase margin is 60.8 degrees, and the bandwidth is 4820 [rad/s], meeting the specified design criteria. Therefore, the stability of the system can be confirmed through the Bode plot analysis.

The MATLAB m-file, which was used in the controller design, is shown below:

s = tf(‘s’); Vin = 310; L = 2.4 × 10−3; % L = 2.4 mh C = 2400 × 10−6;   %C = 2400 µf R = 50; D = 0.311; D1 = 1 − D; Vc = Vin/D1; IL = Vc/(R*D1); G1 = (Vc/L)*(s + 1/(R*C) + (1 − D)*IL/(Vc*C))/(s^2 + s/(R*C)+(1 − D)^2/(L*C)); G2 = −Vin/(L*C)*(−1 + L*s/(R*(1 − D)^2))/(s^2 + s/(R*C) + (1 − D)^2/(L*C)); G3 = (IL/Vc)*(L/C)*(−s + (1-D)*Vc/(L*IL))/(s + 1/(R*C) + (1 − D)*IL/(Vc*C)); Kpv = 1; Kiv = 1;    % temporarily set to 1 Gcv = Kpv*(s+Kiv)/s; %wc = 50 [rad/s], P.M = 90 [deg] Kpi = 1; Kii = 1;    % temporarily set to 1 Gci = Kpi*(s + Kii)/s; %wc = 4800 [rad/s], P.M = 60 [deg] Vref = Vin/D1; % sisotool Double-loop configuration T = sisoinit (6); T.F.Value = Vref; T.G1.Value = G1;    % current loop G1 = (iL/d) T.C2.Value = Gci;    % current controller PI = (d/ie) T.G2.Value = G3;    % voltage loop tf. = (Vc/iL) T.C1.Value = Gcv;    % voltage controller PI = (Iref/Ve) sisotool (T);

The MATLAB step response of the DC link voltage is depicted in Figure 7. As expected from the design requirements, the waveform of the DC link exhibits no overshoot. The rising time, defined as the time from 10% to 90% of the waveform, is measured as 0.0443 s, while the settling time is found to be 0.0812 s.

The capacitor balancing controller can be designed from the following equations:

$$i_{C1}=-{\displaystyle \frac{v_{c1}+v_{c2}}{R}}+i_L(1-v_{cont1})$$

$$i_{C2}=-{\displaystyle \frac{v_{c1}+v_{c2}}{R}}+i_L(1-v_{cont2})$$

(20)

From the above equations, the following relationship can be obtained:

$$i_{C1}-i_{C2}=i_L\left(v_{cont1}-v_{cont2}\right)=2∆\mathrm{d}{i}_L$$

(21)

The capacitor voltage difference equation over duty difference can then be rewritten as follows:

$${\mathrm{G}}_{∆C}={\displaystyle \frac{∆v_c\left(s\right)}{∆\mathrm{d}(s)}}={\displaystyle \frac{2}{sC}}{i}_L$$

(22)

where, $∆v_c\left(s\right)=v_{c1}-v_{c2}$.

The closed-loop transfer function of the capacitor voltage difference is given as follows:

$${\displaystyle \frac{∆v_c\left(s\right)}{∆v_{c_{ref}}(s)}}={\displaystyle \frac{\frac{2k_p}{\mathrm{C}}{i}_L}{s+\frac{2k_p}{\mathrm{C}}{i}_L}}$$

(23)

where, $∆v_{c_{ref}}\left(s\right)=0$.

The controller configuration of the balancing controller is illustrated in Figure 8a, while its real implementation is depicted in Figure 8b. The controller gain $K_p$ is set to 0.1 based on the design using MATLAB SISOTOOL.

4. Simulation

The controller was designed using the parameter values shown in

Table 2. Controller system parameter.

Parameter	Value
$\mathrm{Input} \mathrm{Voltage} (V_{in}$)	$310 \mathrm{V}$
$\mathrm{Output} \mathrm{Voltage} (V_{dclink}$)	$450 \mathrm{V}$
$\mathrm{Inductance} (I_L$)	$2.4 \mathrm{m}\mathrm{H}$
$\mathrm{Capacitance} (C_1,C_2$)	$2400 \mathsf{\mu }\mathrm{F}$
$\mathrm{Resistance} (R$)	$50 \mathrm{\Omega }$
$\mathrm{Switching} \mathrm{frequency} (f_s$)	$20 \mathrm{K}\mathrm{H}\mathrm{z}$

, and the controller design was verified by the PSIM simulation.

Figure 9 displays the waveforms of the AC input voltage and AC current from the double-loop controller. It is evident that the power factor (PF) was stably controlled at 0.9932, which is very close to unity.

In Figure 10, the waveforms of the voltage step-up from 450 V to 550 V are presented. Both the output voltage and current are observed to be stably controlled in the boosting section. The actual voltage waveform closely matches the design requirements, except for the 120 Hz ripple components, as shown in Figure 10.

The control performance for the load variation is shown in Figure 11. This waveform demonstrates the control performance when the load resistance is changed from 25 Ω to 50 Ω and back. Comparing Figure 9 and Figure 10 confirms that the control remains stable even after load changes.

The waveforms of the balancing controller are depicted in Figure 12. Capacitors C₁ and C₂ are set to 1200 [µF] and 2400 [µF], respectively. The difference in capacitance results in a voltage difference between the capacitors, as shown in Figure 12a. This imbalance can be controlled using the balancing controller, the waveform of which is illustrated in Figure 12b.

5. Experiments

The hardware is constructed based on the simulation environment. The Texas Instruments’ 320F28069 DSP is utilized for the micro-controller, and the circuit components used in the experiment are configured to match the values presented in Table 1. The detailed setup of the experiment is depicted in Figure 13. While single-phase AC power at 220 V is used in the PSIM simulation, due to limitations in the experimental system’s power, a reduced voltage rating of 110 V is employed during the experiments.

First, the step-up and step-down control for output voltage response characteristics are depicted in Figure 14 and Figure 15, respectively. Figure 14 illustrates the result of boosting the output voltage from 150 V to 210 V, with both voltage and current stably controlled without overshoot. Similarly, Figure 15 displays the waveform resulting from stepping down the output voltage from 210 V to 150 V, where both voltage and current are observed to be stably controlled without overshoot.

Figure 16 shows the waveform when changing the load resistance from 50 Ω to 25 Ω, and Figure 17 shows the waveform when changing it from 25 Ω to 50 Ω. In both cases, it was observed that the voltage was stably controlled. However, with regard to the current, fluctuations were initially observed, but the control stabilized within a short period of time.

The waveforms obtained through the actual experiment closely match the PSIM simulation results, confirming the theoretical validity of the proposed modeling and controller design through experimentation.

6. Conclusions

The paper proposes a double-loop controller design technique to enhance the modeling of a 3-level power factor correction (PFC) converter. The research aims to address challenges encountered in existing single-phase PFC circuits, particularly concerning the presence of a 120 Hz ripple voltage. Prior studies have not adequately addressed double-loop controller design or voltage ripple rejection in this context. Therefore, this paper presents a novel approach by applying a 3-level structure to achieve these goals.

The proposed technique involves configuring the obtained state space expression of the transfer function to be applicable across the full duty range. Subsequently, a double-loop controller is designed using MATLAB SISOTOOL. To evaluate the effectiveness of the proposed controller, verification is conducted through PSIM simulation. Moreover, the proposed controller is implemented in practice, and the efficacy of the system design is confirmed through experimental validation.

The primary contribution of this paper is demonstrating the controllability of the double-loop controller for a three-level PFC converter under varying operating points. This highlights the capability of the proposed controller to maintain operation across the entire duty cycle range, achieving unified control. This achievement distinguishes our work, as previous research has not explored this comprehensive aspect.