Operational Amplifiers Defect Detection and Localization Using Digital Injectors and Observer Circuits

Abstract

Operational amplifiers (op amps) are fundamental blocks that find wide application both as stand-alone devices and as crucial blocks embedded in various Systems on Chips (SoCs). Achieving high defect coverage, as well as performing defect localization in these circuits, has proven to be a difficult/expensive task, even with sophisticated testing circuitry. The ISO 26262 standard for functional safety (FuSa) includes the stringent requirement that an automotive IC must have a very high defect coverage. This reinforces the need to ensure the functionality of analog and mixed (AMS) circuits, especially in mission critical applications. This paper presents an all-digital op amp defect detection, diagnosis, and localization method that can be used both for production and in-field tests and discusses various implementation of the proposed method. We validated our results using extensive transistor-level simulations of multiple op amp architectures using TSMC 180 nm technology. Across op amp architectures and multiple implementation approaches, we achieved a worst-case and best-case defect coverage of 94.5% and 99%, respectively. Furthermore, in this work, we also propose a defect diagnosis and localization strategy using recorded bit streams from states of digital injectors and detectors.

1. Introduction

The increase in the demand for advanced features and functionalities, among several other factors, has led to a rapid increase in the level of integration of semiconductor chips into applications in the automotive, space, health, and other mission critical industries. On the other hand, the extensive integration of these chips also increases their complexity and can introduce new points of failure. The development of cost-efficient novel defect detection strategies is becoming one of the hot topics in the semiconductor industry [1]. Defect detection is a multifaceted problem. On one hand, the ISO 26262 standard [2] for functional safety recommends that an automotive IC have a high defect coverage (>90%). However, rigorous testing schemes require a long testing time, thereby significantly impacting the overall test cost [3] and invariably also increasing the production cost. Furthermore, most of the failures in ICs reported in customer returns are in-field ICs that have failed due to latent defects [4], emphasizing the significance of developing testing schemes that can be implemented for in-field testing. In addition to this, once latent defects or any form of defects are detected, it is crucial to locate the source of the defect to improve future circuit designs and make them more reliable.

The main components of commonly used IP blocks on an SoC are AMS circuits, digital circuitry, and memory logic. Due to the relative ease of defect diagnosis in digital circuits, coupled with extensive research backed by unifying standards, defect detection in digital circuits has made significant progress [5]. As a result, digital circuits are responsible for only 20% of reported failures in ICs, even though they make up 80% of all systems [5,6]. This demonstrates the significant role that AMS defect detection strategies must play in improving overall IC reliability. Op amps represent one of the most versatile blocks in AMS ICs and possibly the most commonly used [7], making the addressing of defect detection concerns in them a pressing need. In literature, several op amp defect detection methods have been proposed to solve these challenges.

In [8,9], the authors have proposed defect testing frameworks that reduce the simulation test time and save test costs. In ref. [8], the authors achieve time savings in simulations by sweeping a global control variable and, as a result, avoiding the repetitive work of generating a netlist for each defect. Refs. [10,11] also proposed methods to group/cluster defects in an analog circuit and consequently reduce the number of test simulations and the test time. Others [12,13] also utilize the multi-site testing capabilities of modern automated test equipment (ATE), where numerous devices are simultaneously tested on a single board to reduce the test time. Recently, several design for test (DFT) and built-in self-test (BIST) methods [1,7,9] have been proposed as strategies to ensure the continued reliability of ICs through online health monitoring. Several op amp defect detection methods [3,14,15,16,17,18,19,20] have also been proposed in literature. In refs. [14,15,16], an op amp circuit under test (CUT) is converted to an oscillator using passive networks for defect testing. Refs. [17,18] proposed op amp defect testing by monitoring quiescent and/or transient supply current while [19,20] also proposed a method to test op amps through a DC voltage sweep.

This paper, which is a further development of the concept introduced in [7], presents a simple defect-oriented testing technique for op amp defect detection, diagnosis, and localization. The major contributions in this paper are as follows:

• This manuscript provides a more extensive explanation of Intentional Offset Injection (IOI) op amp defect detection and shows, by way of analytical formulas, how to realize robust testing circuitry.
• We demonstrate how to apply intentional offset injections to all possible offset injection sites for a given op amp architecture and validate with simulation results.
• In this manuscript, we discuss a novel defect localization technique for op amps using a binary sequence obtained from the state of the digital injectors and detectors employed in our method after testing.

The rest of the paper is organized as follows. In Section 2, we provide clarity on certain defect terminologies used throughout this paper and in literature, along with a review of existing op amp defect detection techniques. We also present our defect model. In Section 3, we discuss our proposed method of using purely digital testing circuitry as a control and an observer circuit to detect, diagnose, and localize defects in the op amp, Widlar reference, and bias circuitry. Section 4 presents the simulation results for two circuits under test (CUTs), while Section 5 outlines our conclusions.

2. Literature Review

2.1. Defect Terminology Review

• A fault is an unexpected change in a specified performance of a primitive circuit or circuit module that is not within the circuit’s specification limits [21].
• A defect is an unintended physical change in the manufactured circuit that causes a difference between the fabricated circuit and its layout. Defects are of two types: hard and soft defects.
• A soft defect, also called a parametric defect, does not affect the circuit topology but translates to variations in the component parameters that affect its output. They result from imperfections in IC fabrication, causing variations in oxide thickness, substrate doping, threshold voltage, mobility, and transistor width [14].
• Hard (catastrophic) defects, on the other hand, are those that change circuit topology. They are generally introduced by local defect mechanisms such as impure particles on the wafer surface, defects in oxide, dust particle interaction during masking, which blocks the exposure, etc. Hard defects usually result from short and open defects in circuit components. The defect detection techniques presented in this work primarily focus on catastrophic defects, as they make up about 80% of observed analog faults [20].
• The defect universe refers to all reasonably likely defects that can be algorithmically defined, excluding those in unused circuitry.
• The defect model is an equivalent circuit for a defect in the context of a circuit simulator. In this work, the defect models for testing defects are in line with P2427 standards [21].
• The defect coverage is the weighted percentage of defects detected by tests applied to the circuit’s ports as a fraction of all defects in the circuit’s defect universe. Although it is not the only metric, a high defect coverage is one of the hallmarks of a good defect detection and diagnosis strategy.

$$\mathrm{\%}\mathrm{D}\mathrm{e}\mathrm{f}\mathrm{e}\mathrm{c}\mathrm{t} \mathrm{C}\mathrm{o}\mathrm{v}\mathrm{e}\mathrm{r}\mathrm{a}\mathrm{g}\mathrm{e}={\displaystyle \frac{\mathrm{W}\mathrm{e}\mathrm{i}\mathrm{g}\mathrm{h}\mathrm{t}\mathrm{e}\mathrm{d} \mathrm{t}\mathrm{o}\mathrm{t}\mathrm{a}\mathrm{l} \mathrm{n}\mathrm{u}\mathrm{m}\mathrm{b}\mathrm{e}\mathrm{r} \mathrm{o}\mathrm{f} \mathrm{d}\mathrm{e}\mathrm{f}\mathrm{e}\mathrm{c}\mathrm{t}\mathrm{s} \mathrm{d}\mathrm{e}\mathrm{t}\mathrm{e}\mathrm{c}\mathrm{t}\mathrm{e}\mathrm{d}}{\mathrm{A}\mathrm{l}\mathrm{l} \mathrm{d}\mathrm{e}\mathrm{f}\mathrm{e}\mathrm{c}\mathrm{t}\mathrm{s} \mathrm{i}\mathrm{n} \mathrm{c}\mathrm{i}\mathrm{r}\mathrm{c}\mathrm{u}\mathrm{i}\mathrm{t}{\mathrm{s}}^{\mathrm{’}}\mathrm{s} \mathrm{d}\mathrm{e}\mathrm{f}\mathrm{e}\mathrm{c}\mathrm{t} \mathrm{U}\mathrm{n}\mathrm{i}\mathrm{v}\mathrm{e}\mathrm{r}\mathrm{s}\mathrm{e}}}\times 100$$

• Defect localization is the mapping out of the physical region of the circuit where the defect occurred.
• Defect collapsing comprises grouping defects that have the same effect. Defect collapsing serves as a good basis to reduce the amount of defect testing simulation by simulating a few samples in each cluster.

2.2. Defect Model

The defect detection strategy presented in this paper focuses on short and open hard defects. In accordance with the model prescribed in P2427 Standards [21], we test the six common transistor defects (Drain Open, Source Open, Gate Open, Gate-Drain Short, Gate-Source Short, Drain-Source Short) shown in Figure 1 and Figure 2, along with open and short defects in passive elements (resistors and capacitors), shown in Figure 3. Although we considered only catastrophic defects, to ensure robustness, we tested our method with strong shorts (1 Ω), as well as intermediary shorts (10 Ω) and light shorts (100 Ω). For open defects, resistors of 5 MΩ (light open), 50 MΩ (intermediate open), and 500 MΩ (strong open) are used. These defects are injected into our circuit under test (CUT) under the single-fault assumption [17]. For detailed information on the defect models used in this manuscript, readers can refer to reference [9].

2.3. Op Amp Defect Testing Methods in Literature

Several defect testing strategies for op amps have been presented in literature over the years [3,14,15,16,17,18,19,20]. In this subsection, we discuss two of the op amp defect testing techniques that have been proposed.

2.3.1. Oscillation Test Methodology (OTM)

OTM involves converting a CUT into an oscillator using either external “RC” components (for production testing) or internal “RC” components (for built-in self-test approach). The oscillation frequency of the circuit is then compared to an upper and lower frequency threshold expected in a defect-free circuit (herein after referred to as a golden circuit) based on process and mismatch variations. If the measured frequency is within this threshold, then the circuit is considered to have no defect; otherwise, it is characterized as defective. References [14,15,16,19] have all proposed op amp defect detection based on OTM. A drawback to using this technique for op amp defect detection is that it requires area-intensive resistors and capacitors to convert CUT into an oscillator. Also, OTM is a transient-based test scheme and, as such, requires more simulation time. The long test time coupled with the area-intensive testing circuitry needed to execute OTM make it an expensive test method. We present an op amp defect detection method based solely on DC parametric sweep simulations. Our proposed method requires a few transistors and digital CMOS inverters, which take up a small area compared to resistors and capacitors.

2.3.2. IDDQ and IDDT Testing

In [17,18,22], the authors presented op amp defect detection methods based primarily on monitoring the variations in the transient and/or quiescent supply current of a CUT. IDDQ and IDDT are widely used defect testing techniques discussed in literature. However, the reported results suggest that to achieve a high coverage (92%, as presented in [17]), both transient (IDDT) and quiescent (IDDQ) current measurements must be implemented. Meeting this strict requirement demands the use of intricate testing circuitry, which may not be preferable. Moreover, the need for transient current testing prolongs the defect simulation time, significantly adding to the test cost. Our approach relies primarily on DC testing, which reduces the simulation time required and achieves higher defect coverage.

3. Proposed Testing and Localization Technique

In this section, we discuss how we use injector circuits to control an op amp into a region of operation where the behavior of a defective circuit can easily be distinguished from the golden circuit. In ref. [7], we introduced Intentional Offset Injection (IOI), Widlar reference mismatch injection, and detector circuits for detecting defects in op amps. However, in this paper, we expand on this concept and discuss the various ways in which a designer can utilize this simple and effective tool for defect detection and localization. We also present analytical formulas to back this technique.

3.1. Intentional Offset Injection (IOI)

The main concept of IOI lies in the open-loop transfer function of an op amp, as shown in Figure 4. We define the region bounded vertically by ${Vos}_{flt,max}$ and ${Vos}_{flt,min}$ and horizontally by $V_{OLmax}$ and $V_{OLmin}$ as the region of operation for a golden circuit, factoring in process and mismatch variations. During the test phase, the IOI testing circuit is used to inject either a positive or negative offset, which is greater than the op amp’s natural (systematic and random) offset and simultaneously observe the op amp’s output with two inverter circuits following one another. In the golden circuit, when a positive offset is injected, the output of the op amp is stuck high, and when a negative offset is injected, the output of the op amp is stuck low. However, through the action of a defect, the op amp offset may be stuck below ${Vos}_{flt,min}$ or stuck above ${Vos}_{flt,max}$ regardless of the offset (positive or negative) injected, deviating from the truth table for the IOI method.

Table 1. IOI truth table.

${\mathit{V}}_{\mathit{O}\mathit{S}\_\mathit{N}\mathit{E}\mathit{G}}$	${\mathit{V}}_{\mathit{O}\mathit{S}\_\mathit{P}\mathit{O}\mathit{S}}$	${\mathit{V}}_{\mathit{O}\mathit{U}\mathit{T}\_\mathit{D}\mathit{I}\mathit{G}}$	${\mathit{V}}_{\mathit{O}\mathit{U}\mathit{T}\_\mathit{D}\mathit{I}\mathit{G}}\mathbf{}$ $\mathbf{for} \mathbf{DS} \mathbf{Short} \mathbf{of} {\mathit{M}}_{\mathit{F}13}$
$0$	$1$	$1$	$0$
$1$	$0$	$0$	$0$

depicts the truth table for IOI.

For a given op amp topology, there are multiple offset contributing sources, but the effects in some areas are more dominant. For instance, in the folded cascode op amp shown in Figure 5, the dominant offset contributing parts are the input differential pairs $(M_{F2},M_{F3})$, cascode-stage top pmos pair $(M_{F4},M_{F5})$, and cascode-stage bottom nmos pair $(M_{F10},M_{F11})$. Similarly, for the telescopic cascode architecture shown in Figure 6, the input differential pairs $(M_{T2},M_{T3})$ and the bottom nmos pair $(M_{T8},M_{T9})$ are the dominant sources of offset. These are all points at which we can intentionally inject offset for defect detection with the IOI method.

The op amp’s offset after fabrication is made up of a systematic part and a random part. The random offset is a function of several random process parameters $(\mu , C_{ox},V_{th},etc)$. This makes the offset after fabrication nearly impossible to predict, but its distribution can be accurately predicted. The randomness in the offset results from mismatch in the op amp’s input pair drain current [23]. For a given folded cascode architecture, the offset after fabrication can be estimated using (1) [23] and its variance deduced from (1) is shown in Equation (2).

$$V_{OS}\approx ∆V_{th\mathrm{2,3}}+{\displaystyle \frac{g_{m\mathrm{4,5}}}{g_{m\mathrm{2,3}}}}∆V_{th\mathrm{4,5}}+{\displaystyle \frac{g_{m\mathrm{10,11}}}{g_{m\mathrm{2,3}}}}∆V_{th\mathrm{10,11}}+{\displaystyle \frac{I}{g_{m\mathrm{2,3}}}}\left({\displaystyle \frac{∆{\beta }_{\mathrm{2,3}}}{{\beta }_{\mathrm{2,3}}}}+{\displaystyle \frac{∆{\beta }_{\mathrm{4,5}}}{{\beta }_{\mathrm{4,5}}}}+2{\displaystyle \frac{∆{\beta }_{\mathrm{10,11}}}{{\beta }_{\mathrm{10,11}}}}\right)$$

(1)

$${\sigma }_{V_{OS}}^2={\sigma }_{∆V_{th\mathrm{2,3}}}^2+{\left({\displaystyle \frac{\raisebox{1ex}{$g_{m\mathrm{4,5}}$}\!\left/ \!\raisebox{-1ex}{$I_{D\mathrm{4,5}}$}\right.}{\raisebox{1ex}{$g_{m\mathrm{2,3}}$}\!\left/ \!\raisebox{-1ex}{$I_{D\mathrm{4,5}}$}\right.}}\right)}^2{\sigma }_{∆V_{th\mathrm{4,5}}}^2+{\left(2{\displaystyle \frac{\raisebox{1ex}{$g_{m\mathrm{10,11}}$}\!\left/ \!\raisebox{-1ex}{$I_{D\mathrm{10,11}}$}\right.}{\raisebox{1ex}{$g_{m\mathrm{2,3}}$}\!\left/ \!\raisebox{-1ex}{$I_{D\mathrm{2,3}}$}\right.}}\right)}^2{\sigma }_{∆V_{th\mathrm{10,11}}}^2+{\left({\displaystyle \frac{1}{\raisebox{1ex}{$g_{m\mathrm{2,3}}$}\!\left/ \!\raisebox{-1ex}{$I_{D\mathrm{2,3}}$}\right.}}\right)}^2\left({\sigma }_{{\displaystyle \frac{∆{\beta }_{\mathrm{2,3}}}{{\beta }_{\mathrm{2,3}}}}}^2+{\sigma }_{{\displaystyle \frac{∆{\beta }_{\mathrm{4,5}}}{{\beta }_{\mathrm{4,5}}}}}^2+4{\sigma }_{{\displaystyle \frac{∆{\beta }_{\mathrm{10,11}}}{{\beta }_{\mathrm{10,11}}}}}^2\right)$$

(2)

For this analysis, assume $I=I_{D\mathrm{2,3}}=I_{D\mathrm{4,5}}=0.5I_{D\mathrm{10,11}}$. It is important to remember that in MOS technology, the variance of a process parameter $∆p$, between two identical adjacent transistors, reduces inversely with the gate area and is shown in (3) [24]. By using (3), we can accurately determine the variance of both the threshold voltage $(∆V_{th})$ and the transconductance parameter $∆\beta$ and, by extension, the variance of the op amp’s post-fabrication offset. Similar analysis can be performed for other op amp topologies. By estimating the standard deviation, we can determine the aspect ratio $(W/L)$ of the IOI testing transistors to ensure that for a certain yield level, we can guarantee that IOI will inject positive and negative offset.

$${\sigma }_{∆p}={\displaystyle \frac{A_p}{\sqrt{A}}}$$

(3)

3.2. Compensation Network

For defect detection in the compensation network, we use the simple rise and fall time introduced in [3]. The main idea in this method is that an open defect in a compensation network can lead to much lower rise/fall times compared to a defect-free op amp. This reduction in rise/fall times is detected using simple digital control and monitor circuits. This method is explained more elaborately in Results (4.1.2).

3.3. Widlar Mismatch Injection

We introduced Widlar mismatch injection in [7] to detect defects in the Widlar current reference and the bias circuit. The basic principle in the Widlar mismatch injection is to intentionally skew the current mirror ratio in the Widlar reference during the test phase to set it into a certain operating condition where the action of a defect is easily detected. From Figure 6, we can see that there are multiple current mirrors, each of which is a potential injection site for Widlar mismatch injection. However, considering $M_{W1}$ and $M_{W2}$ is the first point of the signal path, makes it the best skewing point. During the test phase, the source of the transistor $M_{WID}$ (blue in Figure 6) is connected to $VDD$ to alter the current mirror ratio and observer circuit are used to monitor the bias voltage $Vbp,Vbn$, and $Vpt$. During normal operation, $M_{WID}$ is turned off to restore the current mirror ratio. As such, the testing circuit has no effect on the op amp’s operation.

3.4. Detectors

In our proposed defect detection and localization approach, we use the simple digital CMOS inverters and digital window comparators introduced in [7]. A CMOS inverter produces an output signal opposite to the input signal by comparing it against its switching threshold. The switching threshold of an inverter is determined by the aspect ratios of the nmos and pmos transistors. Increasing the aspect ratio of the pmos increases the switching threshold, and vice versa. Similarly, increasing the aspect ratio of the nmos reduces the inverters switching threshold, and vice versa. These inverters are designed such that the switching threshold is around the mid-point of $V_{DD}$ and $V_{SS}$ at a typical corner. In our defect testing setup, we place two inverters to directly follow each other (Figure 6) at the output of the op amp to convert analog signals that are close to $V_{DD}$ to digital ‘1’ and the analog signals that are close to $V_{SS}$ as digital ‘0’.

The second detector implemented in our testing circuitry is the digital window comparator shown in Figure 7. Unlike an analog window comparator that requires two references, in the digital window comparator, an analog input signal is compared to two switching thresholds, $V_{TH}$ and $V_{TL}$, of the $H_{INV}$ and $L_{INV}$ inverters, respectively. If the signal lies within the thresholds, then the output from the XOR will be a digital high; otherwise, it will be a digital low (see

Table 2. Truth table of digital window comparator.

${\mathit{V}}_{\mathit{I}\mathit{N}\_\mathit{W}\mathit{C}}$	${\mathit{V}}_{\mathit{O}\mathit{U}\mathit{T}\_{\mathit{L}}_{\mathit{I}\mathit{N}\mathit{V}}}$	${\mathit{V}}_{\mathit{O}\mathit{U}\mathit{T}\_{\mathit{H}}_{\mathit{I}\mathit{N}\mathit{V}}}$	${\mathit{V}}_{\mathit{O}\mathit{U}\mathit{T}\_\mathit{W}\mathit{C}}$
0$<V_{IN\_WC}<V_{TL}$	$1$	$1$	$0$
$V_{TL}<V_{IN\_WC}<V_{TH}$	$0$	$1$	$1$
$V_{IN\_WC}>V_{TH}$	$0$	$0$	$0$

).

3.5. Proposed Defect Localization Method

As has already been emphasized, the defect detection strategy presented in this paper focuses on short and open hard defects. Short defects create an additional conductive electrical path between two (or more) nodes in the defect-free netlist, whereas open defects break a connection between two (or more) terminals of one or more circuit elements in the defect-free netlist. Due to the difference in their impact on the circuit, our proposed approach investigates defect localization in short defects and open defects separately.

3.5.1. Localization Approach for Short Defects

The proposed defect detection and localization method discussed in this paper implores two injectors and four detector circuits. Considering their digital nature, detectors can have only two different outputs, a ‘1’ and a ‘0’. For the digital window comparator, an output high depends solely on the placement of the window. For each of the injector controls (IOI and Widlar mismatch), each detector outputs a 2-bit binary made of any combinations of 0s and 1s. Thus, for both control injections, each detector records a 4-bit binary stream. Consequently, at the end of the testing phase, for four detectors, we obtain a 16-bit binary number. These 16-bit binary streams correspond to unique decimal values, and all the defects that map to these values are clustered together and can be used to point out where defect occur in the circuit. This information can also be used to reduce the test time by testing a few samples from individual clusters, as opposed to testing all defects in the defect universe for subsequent defect testing.

3.5.2. Localization for Open Defect

An open defect $\left(f_n\right)$, leads to a high impedance, breaking the connection between two or more nodes. Consequently, the current in these high-impedance paths approaches zero. To accurately capture this information for the purpose of localization, we monitor currents on $k$ selected branches $\left(B\right)$ during the instance of an open defect. These currents, $I_{ki}$, are compared to an upper and lower current threshold that can flow through the branch in a golden circuit. A digital ‘$1$’ is generated for a current within this threshold and a digital ‘$0$’ is generated for the opposite case. Like the short defect case, each current branch generates a 4-bit binary stream at the end of testing and a $4k$-bit binary stream for all k monitored branches. All defects that have the same decimal value signature for the $4k$-bit binary stream are clustered together. A simple algorithm depicting the explanation is shown in Algorithm 1. The upper and lower current thresholds for each monitored branch in a defect-free case are obtained through Monte Carlo simulations involving process and mismatch variations.

Algorithm 1: open defect clustering and localization

Open defect list:  $F_0=\{f_1,f_2,f_3,\dots ,f_n\}$ Control injector states: $S_0=\{s_1,s_2,s_3,s_4\}$ Branches to monitor:  $B=\left\{b_1,b_2,b_3,\dots {,b}_k\right\}$ for each defect $f_n$ in defect list:      Carry out defect simulation and obtain branch current for all 4 states.      for each element $b_k\in B$:          for all 4 states: generate 4- bit binary.                          If node current, $I_{ki}$ is within limit $I_{ki,upper}$ and $I_{ki,low}$then;                         Bit = 1                 Else:                                 Bit = 0 Compute Decimal equivalence $D_f$ of 4k-bit binary streams due to defect $f_n$  for all $f_n\in$ $F_0$ do               If they have the same, $D_f$ then;                       place in one group.

4. Defect Simulation Results

In this section, we present extensive transistor-level simulation results validating the proposed op amp defect detection and localization technique using two CUTs: a two-stage folded cascode amplifier and a two-stage telescopic op amp. Multiple op amp defect detection techniques [14,25] presented in literature are tested against the simple five-transistor differential amplifier followed by a common-source (CS) stage and, as such, do not include defect detection in cascode transistors, which are common to several high-performance op amp topologies. As discussed in Section 3.1, for a particular op amp topology, there are multiple sites for offset injection that a designer can select. To show the universality of the proposed method, we present results for all IOI sites for a given op amp topology. All designs were done using 1.8V I/O transistors in TSMC 180 nm technology.

4.1. Simulation Results for Telescopic Op Amp

Figure 6 shows the complete schematic of a two-stage telescopic op amp, while Figure 8 shows the frequency response of the amplifier in a typical corner. The systematic offset is $3.06 \mathsf{\mu }\mathrm{V}$, and its standard deviation is $1.28 \mathrm{m}\mathrm{V}$. During normal operation, the offset injection switches $M_{IO{I}_{POS}}$ and $M_{IO{I}_{NEG}}$ are opened. Similarly, the drain of $M_{WID}$ is grounded to ensure a mirror ratio of 1:1 for $M_{W1}$ and $M_{W2}$. As a result, the testing circuit has a negligible effect on the normal operation of the op amp and consumes negligible power.

4.1.1. Defect Detection in Telescopic Op Amp (Main Structure)

During defect detection, the op amp is set into an open-loop configuration, while $V_N$ and $V_P$ are also set to a common mode voltage, $V_{CM}$. By setting either $V_{O{S}_{NEG}}$ or $V_{O{S}_{POS}}$ high to close switches $M_{IO{I}_{NEG}}$ and $M_{IO{I}_{POS}}$, respectively, the matching of the differential pair $(M_{T2},M_{T3})$ is skewed to introduce offset. As has already been discussed, when both input voltages $(V_N$ and $V_P)$ are set to some common-mode voltage, any injected offset should be amplified and should produce an appropriate output. Specifically, injecting a positive offset should result in a ‘1’ at $V_{OU{T}_{DIG}}$, and injecting a negative offset should result in a ‘0’ at $V_{OU{T}_{DIG}}$. However, under the presence of a defect, say, DS short of $M_{F13}$, the output of the amplifier is drawn closer to $V_{SS}$, setting the $V_{OU{T}_{DIG}}$ to a logical ‘0’. This situation persists regardless of a positive or negative injected offset, violating the truth table.

The explanation provided above is the same for IOI through other sites. Using the single-fault assumptions [7,17], we injected all defects in the defect universe based on the defect models presented in Section 2. For the 11 transistors in the main amplifier, we injected 66 defect cases. The results show a high coverage, 66/66 (100%) and 63/66 (95%), for offset injection through the differential pair and bottom nmos pair, respectively.

Table 3. Injection point coverage summary table for IOI in telescopic op amp.

Injection Site	Coverage	Undetected	Detected with Comparator
$M_{T2}{,M}_{T3}$	$66/66$	$0$	$1$
$M_{T8},M_{T9}$	$63/66$	$3$	$1$

provides a summary of the results for IOI for all injection sites.

4.1.2. Defect Detection in Compensation Network

The main purpose of the compensation network is to keep the op amp stable, with little to no oscillatory behavior. The capacitor Cc and the nulling resistor Rz in Figure 6 form the compensation network. In this work, to detect the defects in the compensation network (Cc, Rz), we use a similar rise/fall time-based method, presented in [3]. In DC, as a capacitor behaves like an open circuit as such, it is not possible to test the functioning of a capacitor with just DC simulations alone. Using a simple bitstream-based test, as tabulated in

Table 4. Truth table for defect detection in a compensation network.

				Defect-Free	Open Defect in Compensation Network
State	Time	$V_{neg}$	$V_{pos}$	$V_{out\_dig}$ expected	$V_{out\_dig }$	$V_{out\_dig }$
					Case 1	Case 2
Intrinsic Offset	Bit0	0	0	X	L	H
Positive Offset	Bit1	0	1	H	H	H
Intrinsic Offset	Bit2	0	0	H	L	H
Negative Offset	Bit3	1	0	L	L	L
Intrinsic Offset	Bit4	1	1	L	L	H

, we can test the defects in the compensation network.

The fundamental idea with this method is that when the compensation network has no defects; the rise/fall time of the operational amplifier is high as compared to the op amp with defects in the compensation network. The fall time for a defect-free op amp is way higher than an op amp with open defects in the compensation network. Using this information, if we keep the bit width of the bitstream less than $T_{delta}$, then the defects in the compensation network are detected where $T_{delta}$ is defined as the difference between the delay of a defect-free device and that of a device with an open defect in the compensation network. This is shown in Figure 9. For our CUT, $T_{delta}=64 \mathsf{\mu }\mathrm{s}$. The truth table in Table 4 is tested by setting $T_{bit}=10 \mathsf{\mu }\mathrm{s}$, which is nearly $(1/6)th$ of $T_{delta}$. As shown in Figure 10, the open defects in the compensation network are detected at Bit 3. By performing this test, open defects in Rz and Cc, as well as short defects in Cc, are detected. The only defect that is not detected is a short defect in Rz. The reason for this is that, although a short defect in Rz is a hard defect, the op amp still retains the properties on the compensation, making it an undetectable defect.

4.1.3. Defect Detection in Widlar Reference and Current Bias Circuit

For defect detection in the Widlar reference and bias circuit, we apply the Widlar reference mismatch injection while we monitor the three bias voltages: $Vbp,Vbn$, and $Vpt$. We monitor these node voltages using the digital window comparator. The digital window comparator $Vpt\_wc$ is designed such that the bias voltage $Vpt$ of the golden circuit lies within the window during both control injections, even with its process and mismatch variations. The digital window comparator $Vbn\_wc$ is designed such that the bias voltages $Vbn$ lies in the window during IOI and lies outside the window during Widlar mismatch injection for all process and mismatch variations, while the digital window comparator $Vbp\_wc$, on the other hand, is designed such that during IOI bias voltage, $Vbp$ lies outside the window, and it lies within the window during Widlar mismatch injections.

Table 5. Digital output state of detectors for a golden circuit.

Detector	Positive IOI	Negative IOI	Mismatch + Positive IOI	Mismatch + Negative IOI
$Vpt$	1	1	1	1
$Vbn$	1	1	0	0
$Vbp$	0	0	1	1
$V_{OUT\_DIG}$	1	0	1	0

summarizes this explanation and shows the digital output state expected from the window comparator for a golden circuit.

During this test phase, we skew the current mirror ratio of $M_{W1}$ and $M_{W2}$ in the Widlar reference by connecting the drain of transistor $M_{WID}$ to $V_{DD}$. Like the case of the main amplifier, we injected defects under the single-fault assumption. For eight transistors and one resistor, we injected 46 defects and obtained a defect coverage of 100%. To ensure robustness and prevent false fails, we performed 200 Monte Carlo simulations of node voltage mismatch and process variations. We also performed 200 Monte Carlo simulations with mismatches and process variations for the transfer characteristics of detectors. Simulation results showing node voltages accurately captured in corresponding windows, regardless of these mismatches and process variations, are shown in Figure 11, Figure 12 and Figure 13.

For the complete op amp and Widlar reference bias circuit, we obtained a coverage of 97% and 99% for IOI injection through a differential pair and bottom nmos pair, respectively.

4.1.4. Defect Localization and Clustering in Telescopic Op Amp

As already discussed in Section 3, the proposed method for defect localization and clustering splits the defect universe into open defects and short defects based on their impact on the op amp. For the localization and clustering of short defects we use the digital states of detectors to form a 16-bit binary value. All short defects that have equivalent 16-bit binary signature are collapsed into a single cluster. Based on the states of the truth tables presented in table detectors, the binary signature of the golden circuit is obtained as “1111110000111010”.

Table 6. Telescopic op amp short defect localization results.

Cluster	Defects in Cluster	Cluster	Defects in Cluster
1	${GD}_{MT5},{GD}_{MT11}$	10	${GD}_{MT4}$
2	${GS}_{MT5}$	11	${GS}_{MW7},{DS}_{MW7},{GD}_{MW8},$ ${DS}_{MW8}$
3	${DS}_{MW1},{DS}_{MW5}$	12	${GS}_{MT4}$
4	${GD}_{MW5}$	13	${GS}_{MT6}$
5	${GS}_{MT1},{GS}_{MT11},{GS}_{MW1},$ ${GS}_{MW2},{DS}_{MW2},{GS}_{MW3},$ ${DS}_{MW3},{GS}_{MW4},{GS}_{MW5}$	14	${DS}_{MW4}$
6	${GS}_{MT2}{,DS}_{MT2},{GD}_{MT3},$ ${GS}_{MT3},{DS}_{MT4},{DS}_{MT7},$ ${DS}_{MT9},{DS}_{MT11},{GS}_{MT10}$	15	${DS}_{MT1},{GD}_{MT2},{DS}_{MT3},$ ${DS}_{MT5},{DS}_{MT6},{GD}_{MT7},$ ${GD}_{MT8},{GS}_{MT8},{DS}_{MT8},$ ${GD}_{MT9},{GS}_{MT9},{DS}_{MT10}$
7	${GD}_{MW1},{GD}_{MW4}$	16	${GS}_{MT6},{GS}_{MW6},{DS}_{MW6},$ ${GS}_{MW8}$
8	${GD}_{MT1}$	17	${GD}_{MT6}$
9	$R_{W,SHORT}$	18	${GD}_{MT11}$

${GD}_X=$ gate drain short, ${DS}_X=$ drain source short, ${GS}_X=$ gate source short.

summarizes the cluster results for short defects in the Telescopic op amp and Widlar reference and current bias circuit for the highest defect coverage results. Localization results for the compensation network are not presented, as they provide unique signatures based on the test approach used.

For open defect localization, we apply the method described in Algorithm 1. We monitored currents in branches $I_{TB1}-I_{TB3}$ in the telescopic op amp and $I_{WB1}-I_{WB4}$ in the Widlar reference and current bias circuit. Based on this, we generated the binary signature of each defect injected. The simulation results for open defects with the same binary signatures clustered together are summarized in

Table 7. Telescopic Op amp open defect localization results.

Cluster	Defects in Cluster	Cluster	Defects in Cluster
1	${GO}_{MT1},{DO}_{MT1},{SO}_{MT1},$ ${GO}_{MT3},{DO}_{MT3},{SO}_{MT3}$	7	${GO}_{MT10},{DO}_{MT10},{SO}_{MT10},$ ${GO}_{MT11},{DO}_{MT11},{SO}_{MT11}$
2	${GO}_{MT2},{DO}_{MT2},{SO}_{MT2}$	8	${GO}_{MW6},{DO}_{MW6},{SO}_{MW6}$
3	${GO}_{MW1},{DO}_{MW1},{SO}_{MW1}$	9	${GO}_{MW2},{DO}_{MW2},{SO}_{MW2}$
4	${GO}_{MW7},{DO}_{MW7},{SO}_{MW7},$ ${GO}_{MW8},{DO}_{MW8},{SO}_{MW8}$	10	${GO}_{MW4},{DO}_{MW4},{SO}_{MW4},$ $R_{W\_OPEN}$
5	${GO}_{MW5},{DO}_{MW5},{SO}_{MW5}$	11	${GO}_{MW3},{DO}_{MW3},{SO}_{MW3}$
6	${GO}_{MT3},{DO}_{MT3},{SO}_{MT3},$ ${GO}_{MT5},{DO}_{MT5},{SO}_{MT5},$ ${GO}_{MT6},{DO}_{MT6},{SO}_{MT6},$ ${GO}_{MT7},{DO}_{MT7},{SO}_{MT7},$ ${GO}_{MT8},{DO}_{MT8},{SO}_{MT8},$ ${GO}_{MT9},{DO}_{MT9},{SO}_{MT9}$	12

${GO}_X=$ gate open defect, ${DO}_X=$ drain open defect, ${SO}_X=$ source open defect.

.

From the diagnosis results, we realize that multiple defects can have the same defective signature. In some cases, this is because the defect involves the same nodes. For instance, gate source shorts on any of transistors $M_{T8}$ and $M_{T9}$ involve a short between the same two nodes and can be expected to be clustered together. In other cases, defects are clustered together because the chain of signal propagation following the incident of a defect has the same effect on the op amp. For instance, an open defect on any of the terminals of transistors $M_{T10}$ and $M_{T11}$ results in a high-impedance path at the op amp’s second stage, causing the second stage to shut down. Correspondingly, all such defects are clustered together.

4.2. Defect Coverage and Localization Simulation Results for Folded Cascode Op Amp

4.2.1. Defect Detection in FCA

Figure 5 shows the complete schematic of a two-stage folded cascode amplifier. The Widlar current reference and bias circuitry is as shown in Figure 6. Figure 14 shows its frequency response. Like the telescopic op amp, for defect detection in the main amplifier, we apply the IOI method. However, unlike for a Telescopic op amp, there are three sites of possible injection ($M_{F2}$ and $M_{F3}$, $M_{F4}$ and $M_{F5}$, and $M_{F10}$ and $M_{F11}$) for this op amp, any of which can be selected, based on the preference of the designer, for IOI defect testing. For the estimated variance of offset using (2), we size the aspect ratio for IOI testing transistors to guarantee that positive and negative offset is injected, ensuring a robust defect detection technique. The 500 Monte Carlo simulations of mismatch and process variations depicting this for a 3-sigma yield is shown in Figure 15.

For the 13 transistors in the main amplifier and 6 defects per transistor, we injected defects from our defect universe, following the single-fault assumption. The simulation results depict a high coverage of 72/78 (92%), 73/78(94%), and 77/78 (99%), for off-set injection through the top pmos pair in the cascode stage, the bottom nmos pair in the cascode stage, and the differential pair, respectively. This is summarized in

Table 8. Injection point coverage summary table for IOI in FCA.

Injection Site	Coverage	Undetected	Detected with Comparator
$M_{F2}{,M}_{F3}$	$77/78$	$1$	$2$
$M_{F4},M_{F5}$	$73/78$	$5$	$2$
$M_{F10},M_{F11}$	$72/78$	$6$	$2$

. The procedure and simulation results for defect detection in the compensation network, the Widlar reference and current bias circuit, is as outlined in the previous subsection. The final coverage results for complete op amp and all biasing circuit are 95%, 94.5%, and 98% for IOI injection through the top pmos pair, bottom nmos pair, and differential pair, respectively.

4.2.2. Defect Localization in FCA

For defect localization and clustering in the telescopic op amp, we implemented a similar approach to that used inthe telescopic op amp. However, in this architecture, the current branches $I_{FB1}-I_{FB7}$ in the main amplifier and $I_{WB1}-I_{WB4}$ were monitored to obtain the binary signatures of individual defects. The simulation results for short and open defect localization and clusters are presented in

Table 9. Short defect localization results for FCA.

Cluster	Defects in Cluster	Cluster	Defects in Cluster
1	${GD}_{MF6}$	11	${GS}_{MF8},{{GS}_{MF9},GS}_{MW6},{DS}_{MW6},$ ${GS}_{MW8}$
2	${GD}_{MF7}$	12	${GD}_{MF12}$
3	${DS}_{MW1},{DS}_{MW5}$	13	${DS}_{MF8},{GD}_{MF10}$
4	${GD}_{MW5}$	14	${GS}_{MF7}$
5	${GS}_{MF1},{GD}_{MF4},{GS}_{MF4},$ ${GS}_{MF5},{GS}_{MF12},{GS}_{MW1},$ ${GS}_{MW2},{DS}_{MW2},{GS}_{MW3},$ ${DS}_{MW3}$$, {GS}_{MW4}, {GS}_{MW5}$	15	${GS}_{MF2}{,GD}_{MF3},{GS}_{MF3},$ ${DS}_{MF3},{DS}_{MF4},{DS}_{MF6},$ ${DS}_{MF11},{DS}_{MF12},{GS}_{MF13}$
6	${GS}_{MF2},{DS}_{MF2},{DS}_{MF6},$ ${DS}_{MF7},{GS}_{MF9}, {GS}_{MF10},$ ${DS}_{MF10},{GD}_{MF11},{GS}_{MF11}$ ${{GD}_{MF13},DS}_{MF13}$	16	${GS}_{MW7},{DS}_{MW7},{GD}_{MW8},$ ${DS}_{MW8}$
7	${GD}_{MW5}$	17	${GS}_{MF6}$
8	${GD}_{MW1,}{GD}_{MW4}$	18	$R_{W,SHORT}$
9	${GD}_{MF4}$	19	${GD}_{MF8}$
10	${GD}_{MF5}$	20	${DS}_{MF9}$
Undetected	${DS}_{MF6}$

${GD}_X=$ gate drain short, ${DS}_X=$ drain source short, ${GS}_X=$ gate source short.

and

Table 10. Open defect localization results for FCA.

Cluster	Defects in Cluster	Cluster	Defects in Cluster
1	${GO}_{MF1},{DO}_{MF1},{SO}_{MF1}$	9	${GO}_{MF2},{DO}_{MF2},{SO}_{MF2}$
2	${GO}_{MF3},{DO}_{MF3},{SO}_{MF3},$ ${GO}_{MF11},{DO}_{MF11},{SO}_{MF11}$	10	${GO}_{MF4},{DO}_{MF4},{SO}_{MF4},$ ${GO}_{MF6},{DO}_{MF6},{SO}_{MF6}$
3	${GO}_{MF10},{DO}_{MF10},{SO}_{MF10}$	11	${GO}_{MF8},{DO}_{MF8},{SO}_{MF8}$
4	${GO}_{MF5},{DO}_{MF5},{SO}_{MF5},$ ${GO}_{MF7},{DO}_{MF7},{SO}_{MF7},$ ${GO}_{MF9},{DO}_{MF9},{SO}_{MF9}$	12	${GO}_{MF12},{DO}_{MF12},{SO}_{MF12},$ ${GO}_{MF13},{DO}_{MF13},{SO}_{MF13}$
5	${GO}_{MW1},{DO}_{MW1},{SO}_{MW1}$	13	${GO}_{MW2},{DO}_{MW2},{SO}_{MW2}$
6	${GO}_{MW3},{DO}_{MW3},{SO}_{MW3}$	14	${GO}_{MW4},{DO}_{MW4},{SO}_{MW4},$ $R_{W\_OPEN}$
7	${GO}_{MW5},{DO}_{MW5},{SO}_{MW5}$	15	${GO}_{MW6},{DO}_{MW6},{SO}_{MW6}$
8	${GO}_{MW7},{DO}_{MW7},{SO}_{MW7}$	16	${GO}_{MW8},{DO}_{MW8},{SO}_{MW8}$

${GO}_X=$ gate open defect, ${DO}_X=$ drain open defect, ${SO}_X=$ source open defect.

, respectively.

5. Conclusions

We discussed a simple, high-coverage, and robust op amp digital defect detection method and showed, by means of analytical simulations, how to accurately size-test transistors to ensure robust performance across process and mismatch variations. We also introduced a novel defect localization approach using digital states of control and observer circuits in our method. The proposed method was validated with two CUTs. For the folded cascode amplifier, it achieved a worse case coverage of 94.5% and a best-case coverage of 98%. For the telescopic op amp, the proposed method achieved a worst-case coverage of 97% and a best-case coverage of 99%. Our proposed method is low-cost and time-efficient, as it is primarily based on DC simulations. Information obtained from localization can be used for failure analysis tests on part returns and also to help in redundant circuit planning. Moreover, the clustering information generated can help to further reduce the relatively small total simulation/test time of this method in comparison with other methods by simulating few samples from each cluster. Owing to the digital nature of the proposed testing circuitry, it can also easily be implemented with existing digital testing infrastructure, like IJTAG, on an SoC.. Furthermore, the proposed method can also be integrated as part of power-on testing and online health monitoring procedures, thereby ensuring continuous reliability during the IC lifetime. In future work, we are investigating approaches to reduce defects in a single cluster by introducing more digital markers to increase the digital signature of an injected defect.