FPGA-Based Multi-Channel Real-Time Data Acquisition System

Abstract

Data acquisition systems that receive analog signals, convert them to digital, and perform signal processing are used in a variety of systems that use acoustics, radar, sonar, indoor localization, and navigation. The previous systems, such as NI USRP-RIO, are expensive to build, and the number of signals a single device can receive is limited to between two and four. In order to receive more channels of signals, multi-channel data acquisition systems using ADCs operating at tens of MSPS have been proposed. However, these systems require additional processing time because data acquisition and signal processing are performed on different devices. In this paper, we propose a multi-channel data acquisition system using a 16-channel ADC that can support up to 100 MSPS. In particular, to reduce unnecessary signal transmission time, we propose a one-chip structure where all processes are performed on a single chip. Also, we propose a data acquisition system that applies pipelining techniques to enable real-time processing. To verify the proposed system, we used TI ADS52J90 and a Kintex UltraScale KCU105 evaluation board, and confirmed that it is possible to receive and process all channels simultaneously. Furthermore, it is possible to configure a real-time system by adjusting the speed of the signal-processing operation and the speed of the communication interface. Therefore, the proposed system is expected to reduce the cost of system construction by performing signal reception and processing with a single chip, and to reduce the time required for overall signal processing.

1. Introduction

The data acquisition system that receives analog signals, converts them to digital, and then performs signal processing is used in various systems such as acoustic, radar, sonar, indoor localization, and navigation [1,2,3,4]. In particular, systems such as blind source signal separation, audio beam and image processing require the reception and processing of many signals, making multi-channel synchronous data acquisition essential [5]. These systems need to receive data about signals received on multiple channels in a way that does not distort the frequency and magnitude of the signals and the phase relationships between different signals [6,7]. However, existing systems are expensive to build using equipment such as NI USRP-RIO, and the number of signals that can be received by a single instrument is limited to between two and four [8,9]. To improve these systems, several studies have been proposed for multi-channel data acquisition systems that use ADCs (Analog to Digital Converters) capable of multi-channel processing and operating at tens of MSPS to receive multiple signals [10,11,12,13,14,15]. Depending on the target application, these systems receive the ADC results from an FPGA (Field Programmable Gate Array) and perform various computations on the received data using ARM cores or DSPs (Digital Signal Processors) [6,12]. However, in the previous systems, the sampling rate is low when the number of channels is large, and the number of channels that can be received is small when the sampling rate is high [5,6,7,8,9,10,11,12]. Moreover, the signals received from the ADC need to be transmitted back to the ARM core or DSP to process the computation for the application, increasing the time required for signal processing [6,12].

In this paper, we propose a multi-channel data acquisition system that supports a high sampling rate. The system reduces unnecessary signal transmission time by constructing data acquisition and processing on one chip. Additionally, it achieves real-time operation by applying pipelining techniques [16]. To implement the proposed system, an evaluation board equipped with the ADS52J90 from Texas Instruments (TI) [17] is used for the ADC, and the Kintex UltraScale KCU105 evaluation board [18] from Xilinx is used for the FPGA.

We want to emphasize that this paper does not claim to achieve state-of-the-art performance compared to commercial products [19,20], but rather aims to present a methodology for implementing a multi-channel real-time data acquisition system using FPGA. Commercial products typically do not provide internal source codes, making it difficult for users to modify or adapt the design to their systems without the company’s support. In contrast, the proposed design methodology allows for custom-designed data signal processing, giving users the flexibility to implement the necessary signal processing functions. For example, various types of filtering, simple AI computations, and signal processing can be incorporated within the DSP block. As commercial products do not offer the desired functions, users may need to purchase different products. Additionally, upgrading from low/mid-range products to high-end systems often requires purchasing additional high-end products. In summary, the strength of the proposed design methodology lies not in necessarily offering better signal processing functions than commercial products but in its flexibility.

The remainder of this paper is organized as follows: Section 2 analyses the specifications of the ADS52J90 [21] for use in the system configuration. Section 3 describes the structure of the proposed multi-channel data acquisition system, and Section 4 describes the design method of the real-time data acquisition system. Section 5 shows the experimental results using the ADS52J90 [17] and KCU105 evaluation board [18], and Section 6 concludes the paper.

2. Background

To construct an FPGA-based data acquisition system, an ADC that receives analog signals is essential. An ADC is a device that receives an analog signal, samples the input signal with a sampling clock, and outputs digitized data. Most data acquisition systems use commercially available ADCs [10,11,12,13,14,15]. Many commercial ADCs support more than one resolution, number representation, and data rate [21]. Therefore, in order to use ADCs, data acquisition system designers have to analyze the specifications of the ADCs they want to use in detail. This paper focuses on the specification of the TI ADS52J90 chip [21] that will be used in the proposed system.

The output of the ADS52J90 is synchronized to the frame clock denoted as FCLK on a sample-by-sample basis. The number of bits in a sample is determined by the resolutions, and all the data that make up one sample are output during one cycle of the FCLK. The data of one sample are synchronized bit by bit to the bit clock, denoted as BCLK, and output at a double data rate (DDR). The advantage of DDR is that data are updated on both the rising and falling edges of the reference clock, which allows for data to be transmitted twice as fast as SDR (Single Data Rate), where data are updated only once on either edge [22].

The ADS52J90 supports DDR LVDS (Low Voltage Differential Signaling) and JESD204B as digital output interfaces. LVDS is noise tolerant and can communicate at 1 Gbps, while JESD204B has a deterministic latency but can support communication at 12.5 Gbps, which is faster than LVDS [23]. Data output from the output interface consists of 10-bit, 12-bit and 14-bit resolution, depending on the sampling rate that the ADC can accept. The 10-bit resolution supports up to 100 MSPS, while the 12-bit and 14-bit resolutions support 80 MSPS and 65 MSPS, respectively. In addition, the bit order of the output data can be set to LSB first or MSB first, and the data rate can be selected by the ADC user between 1× and 2×. In the 1× case, all LVDS pairs are active and each pair outputs the results of one ADC. The 2× data rate mode causes the LVDS interface to run at twice the speed.

Figure 1 shows the output waveform along with FCLK and BCLK when a 10-bit resolution capable of 100 MSPS is selected, data are output LSB first, and the data rate is 1×. In this paper, we design hardware that operates the ADC with the settings shown in Figure 1, and receives the data from the FPGA and processes the signal.

3. Multi-Channel Data Acquisition System

In this paper, we propose a multi-channel data acquisition system that can receive 16 channels of signals simultaneously, supports up to 100 MSPS for each channel, and handles both reception and processing in one FPGA. Figure 2 shows a block diagram of the proposed system, which consists of an ADC part that receives analog signals, a data acquisition part that receives signals from an FPGA, a signal-processing part that processes the received signals, and a communication interface part that connects the system to a PC or other system. Since this paper uses Xilinx FPGAs to design the system, it is assumed that the Xilinx hardware design tool, Vivado Design Suite, is used for hardware design [24].

3.1. ADC

The ADC part in Figure 2 includes the input of the analog signal and the connection of the ADC output to the FPGA. Depending on the operating settings of the ADC stored in the ADC registers of Figure 2, its output shape varies, which affects the hardware design of the signal receiver in the FPGA. For this reason, settings such as resolution, output interface, and data rate of the ADC are mostly passed from the FPGA to the ADC. The interface to transmit the ADC settings is most often SPI, and the settings are described in detail in the user guide [21]. Some ADCs, such as the ADS52J90 [21] used in this paper, allow for a connection to a PC and configuration from the PC in addition to SPI. A GUI program for the PC is provided by TI, which enables users to set the output interface and resolution of the ADC [21]. If using a PC to set up the ADC, use TI GUI to set the ADC output interface, resolution [21].

After the ADC setup is complete, the input analog signal and sampling clock need to be connected to the ADC. The analog inputs are applied using any device capable of generating waveforms, which is connected to the SMA connector on the input signal port on the ADC evaluation board [17]. The sampling clock is similarly configured with a port on the evaluation board with an SMA connector to apply the clock signal [17]. In order to generate sampling clocks of different frequencies without additional equipment, the proposed system generates sampling clocks in the FPGA and connects to the ADC. As shown in Figure 2, Xilinx Clocking Wizard IP [25] is used to generate the sampling clock of the desired frequency in the FPGA by clock dividing when the input clock is determined. When using the Xilinx evaluation board, the Clock Wizard IP [25] is capable of generating a sampling clock of the desired frequency using the output of a crystal oscillator on the board as a source. The sampling clock has to be made into a single-ended signal so that it can be connected to the ADC via the SMA connector.

3.2. Data Acquisition

The data acquisition part uses the Data Capture module to convert the data passed through the LVDS interface to be stored in memory on a sample-by-sample basis. The Data Capture module consists of the input buffer, which receives the differential signal, DDR register, which receives the serial signal delivered to the DDR, shift register which outputs the output of the DDR register as one sample, and Address Generator, which creates memory-related signals.

The IBUFDS, which takes in differential signals and converts them to single-ended signals, has an instance format in the HDL library provided by Xilinx [26]. All data signals, including FCLK and BCLK, are differential signals and thus required to be received through IBUFDS [26].

However, for FCLK and BCLK, the fanout of these two clocks is high because they are clocked into most of the logic used to receive the signals of all channels. Therefore, it is effective to use a Clocking Wizard IP [25] that supports phase alignment for FCLK and BCLK to tolerate the high fanout. In this case, clock trees are required for FCLK and BCLK to synchronize the clocks of all data capture logic, and the clock tree can be created using the ‘create_clock’ command of the XDC (Xilinx design constraint) command [27].

For the signal-processing part, the data received during one FCLK cycle need to be reconstructed into a single sample. Since the data are transmitted to DDR in synchronization with FCLK and BCLK, these are stored in a DDR register that capture DDR data. Unlike typical registers, DDR registers capture values on both the rising and falling edges of the clock. For Xilinx UltraScale, one of Xilinx HDL libraries, IDDRE1, which outputs two bits of data per clock, can be used to select the timing of outputting the results captured at each edge of the clock [28].

The results of the DDR register need to be stored in the shift register to make one complete sample. At this time, data are transmitted in synchronization with FCLK and BCLK, as shown in Figure 3b; so, a signal that synchronizes FCLK and BCLK is absolutely necessary in the shift register.

The sample-by-sample data must then be stored in on-chip memory for later use in signal processing. Xilinx FPGAs have on-chip memory in the form of block RAM (BRAM) [29]. To store data in BRAM, not only data but also memory address (ADDR), BRAM enable signal (EN), and write enable signal (WE) are required; so, the Address Generator must create all of these signals. As with the shift register, these signals must be created using the synchronization information of FCLK and BCLK to avoid data distortion.

3.3. Signal Processing

Most system-receiving signals require some kind of signal processing such as FFT, IIR filter, and Kalman filter, etc. Traditionally, digital signal-processing operations can be performed using DSP devices or ARM cores as in conventional systems [10,11,12,13,14,15], but it is also possible to perform operations using hardware in FPGAs. In this paper, the FFT (Fast Fourier Transform) operation, which is most used in digital signal processing, and the operators for amplitude and phase of FFT results are implemented in hardware, as shown in Figure 4. The amplitude and phase of the FFT result are calculated using (1) and (2), respectively.

$$Amplitude=\sqrt{{(\mathrm{Re})}^2+{(\mathrm{Im})}^2},$$

(1)

$$Phase={\tan }^{-1}\left({\displaystyle \frac{\mathrm{Im}}{\mathrm{Re}}}\right).$$

(2)

All operators for signal processing such as FFT and (1) and (2) can be designed and implemented directly, but it is also possible to design them using the IP provided by Xilinx.

In this paper, a signal-processing operator is designed using Xilinx IP as shown in Figure 4. FFT IP [28] is used for FFT operation. The FFT input requires reading data from the BRAM where the data acquisition results are stored. Therefore, an Address Generator is essential to create ADDR, WE, and EN signals necessary for reading data from the memory. The square root calculation of amplitude and arc tan calculation of phase are implemented using CORDIC (Coordinate Rotation Digital Computer) IP [30] to calculate a CORDIC-based algorithm. Finally, once the signal processing is complete, the data can be stored in a memory such as BRAM [29] with the signals for BRAM that were generated by Address Generator, which can be used to send the data to other systems.

It is important to note that all operations in the signal-processing section operate with the FPGA system clock denoted as SYSCLK, not FCLK or BCLK. Therefore, even if FCLK or BCLK are used to store the data acquisition results in BRAM, the SYSCLK is used to read them.

3.4. Communication Interface

Since the signal-processing results need to be transmitted to a PC or another system, it is essential to establish a communication interface to connect the two systems and to develop a core system to control this interface.

In traditional systems, communication interfaces such as UART [31], I2C [32], and SPI [33] are commonly used. Additionally, for high-speed communication, interfaces like Ethernet [34] and USB [35] can be established and utilized. Xilinx provides these communication interfaces in the form of IP cores [36,37], all of which connect to other modules via the AXI interface [38]. While it is possible to use an ARM core for the core system, one can also utilize the MicroBlaze IP [39], a softcore that emulates the functions of the core system provided by Xilinx. MicroBlaze [39] is connected to various IPs through the AXI Interface [38], and by designing software to control these IPs, it manages various peripherals connected to MicroBlaze [39]. Note that to transmit the signal-processing results via the communication interface through MicroBlaze [39], the memory storing the signal processing results should be designed as dual-port memory, with the two ports connected to the signal-processing part and the AXI interface [38] through the AXI BRAM controller [40], respectively.

If the communication interface, BRAM for storing the signal-processing results, and MicroBlaze [39] are all designed to connect via the AXI interface [38], the next step is to design the software to operate the peripherals on MicroBlaze [39]. In the system illustrated in Figure 2, software is required to read the results from the memory where the signal-processing results are stored and transmit the data using the communication interface. The software design is carried out using the Xilinx Vitis IDE, and it is possible to design the operating software in C and C++ languages utilizing the APIs provided for the IPs [41].

4. Real-Time Data Acquisition System

The operation of the data acquisition system designed in Section 3 can be represented by a timing diagram as shown in Figure 5a, where T_recv, T_proc, and T_itf represent the time required for data acquisition, signal processing, and interface, respectively. According to the timing diagram in Figure 5a, it takes T_Nsamp to receive, process, and send the data of N_samp to the PC, and T_Nsamp is determined by (3) as the sum of the times of T_recv, T_proc, and T_itf.

$$T_{Nsamp}=T_{recv}+T_{proc}+T_{itf},$$

(3)

In this case, after receiving N_samp data, the data processed by the ADC during T_proc and T_itf cannot be processed by the FPGA. That is, since the received data is not processed continuously over time, designing a real-time data acquisition system is not feasible. For a real-time data acquisition system, data acquisition should continue uninterrupted during T_proc and T_itf. Therefore, to enable the real-time operation of the proposed system, a multi-channel data acquisition system design applying a pipelining technique [39], as shown in Figure 5b, is proposed. By applying the pipelining technique [39], T_Nsamp is as shown in (4).

$$T_{Nsamp}=3\times \max (T_{recv},T_{proc},T_{itf}).$$

(4)

Hence, the time for a real-time data acquisition system is determined by the longest duration among T_recv, T_proc, and T_itf; so, it is necessary to understand how each time is determined.

First, the time required for the data acquisition stage, T_recv, is determined by (5) with the number of samples, N_samp, that need to be received from the ADC and the sampling period, T_samp, where F_samp denotes the sampling frequency. In this context, T_recv becomes longer as the number of samples required for signal processing at one time increases or as the sampling frequency decreases.

$$T_{recv}=T_{samp}\times N_{samp}={\displaystyle \frac{N_{samp}}{F_{samp}}},$$

(5)

Generally, the signal-processing algorithm that needs to be computed on the FPGA is predetermined, and accordingly, N_samp is determined. Since F_samp and N_samp are determined by the system requirements, T_recv is calculated based on the requirements when designing the system.

The time required for the signal-processing stage T_proc, utilizing algorithms such as FFT, is determined by the operation period of the signal-processing circuit T_oper, and the number of required clock cycles N_cc as depicted in (6), where F_oper represents the operating frequency.

$$T_{proc}=T_{oper}\times N_{CC}={\displaystyle \frac{N_{CC}}{F_{oper}}},$$

(6)

The number of required clock cycle N_cc increases with the complexity of signal-processing operations and the number of samples N_samp used in the computation. To enable real-time computation under these conditions, it is essential to apply parallel processing to reduce N_cc. The relation between parallel factor P for parallel processing and N_cc is described in (7).

$$N_{CC}=N_{samp}/P,$$

(7)

Additionally, the T_oper or F_oper are determined by the system requirements or by time limit requirements.

Finally, T_itf is the time required for all the signal-processing results of the first received N_samp to be transmitted to the PC. If the communication interface and its speed are determined, T_itf is determined by (8).

$$T_{itf}={\displaystyle \frac{N_{bit}}{S_{itf}}}$$

(8)

If the communication interface is fixed but the system designer determines the communication rate S_itf, T_itf and N_bit can be used to determine the transmit rate S_itf, where N_bit is the number of transmitted bits. In this case, T_itf should not be longer than T_recv to ensure pipelining is feasible.

In general, the signal-processing algorithms that need to be computed on the FPGA are determined, and the N_samp is determined accordingly. The determined N_samp is described in the system requirements along with F_samp. Therefore, when designing the system, T_recv is calculated based on the requirements.

Additionally, designing a well-balanced system that minimizes the differences between T_recv, T_proc, and T_itf can increase efficiency, making it possible to develop a highly efficient real-time data acquisition and processing system.

5. Experimental Results

To verify the system designed in this paper, we configured the setup as shown in Figure 6 using the TI ADS52J90 evaluation board [17] and Xilinx Kintex UltraScale KCU105 evaluation board [18]. The connection between the two boards is established using an ADC-FMC connector. The ADC settings are configured via a GUI connected to a PC, with the output set to LVDS interface, and the configuration is set to a 10-bit resolution supporting up to 100 MSPS. The system design requirements are assumed to consist of the following four requirements for the purpose of system design.

• Sampling rate (F_samp): 50 MSPS.
• Input signal frequency: 5.15186 MHz (determined by coherent sampling [42]).
• Input signal amplitude: 1.5 Vpp.
• The number of samples for FFT(N_samp): 128.

Accordingly, the input signal is provided using a waveform generator, generating a sine wave with the frequency and amplitude specified by the system requirements. The sampling clock for the ADC is generated and applied by the FPGA at 50 MHz. There are four clock sources to operate the proposed system. The frequency of the four clock sources for the system is summarized in

Table 1. The frequency of clock sources on the system.

Clock	Frequency
Sampling clock	50 MHz
FCLK	50 MHz
BCLK	250 MHz
System clock	200 MHz

. The FFT in the signal-processing part is designed with a pipelined structure [43], requiring a total of 488 clock cycles (cc) to complete the operations. To reduce the number of bits transmitted to the PC, the system is implemented to only transmit the amplitude and phase at the peak point of the FFT to the PC.

To proceed with the design of a multi-channel real-time data acquisition system using the design requirements, it is necessary to calculate T_recv, T_proc, and T_itf using Equations (5)–(7). Given that F_samp and N_samp are 50 MSPS and 128, respectively, T_recv is calculated to be 2.56 μs using (5). The signal-processing unit design results show that a total of 488 clock cycles (cc) are required, and to ensure uninterrupted signal reception, T_proc needs to be equal to or shorter than T_recv. Applying this to (6), it is derived that F_oper needs to be at least 191 MHz. Finally, to calculate T_itf using (7), the number of bits to be transmitted, N_bit, need to be known. Since only the 32-bit amplitude and 32-bit phase for each channel are transmitted, N_bit for 16 channels is 1024 bits. Similar to T_proc, T_itf needs to be shorter than T_recv. Applying this to (7), a transmission rate of at least 400 Mbps is required. Therefore, this proposed system is designed to transmit data to the PC using an Ethernet communication [36] and to implement UART for debugging the system [37].

The hardware designed for 16 channels is implemented on the FPGA as shown in Figure 7, with hardware utilization detailed in

Table 2. Hardware utilization of the multi-channel real-time data acquisition system.

Resource	Utilization		Available
LUT	110,654	45.65%	242,400
LUTRAM	13,488	11.96%	112,800
FF	147,688	30.46%	484,800
BRAM	155.5	25.92%	600
DSP	483	25.16%	1920
IO	171	32.88%	520
BUFG	40	8.33%	480
MMCM	3	30.00%	10
PLL	3	15.00%	20

. However, since the evaluation board used for validation can only verify up to 12 channels simultaneously, the actual results are validated for channels 1 through 12. Upon transmitting the data acquisition results via Ethernet to the PC and verifying them, it is confirmed that the proposed system simultaneously receives data for 12 channels. Figure 8 shows the result of all 12 channels receiving a 1.5 Vpp sine wave. The result transmitted to the PC through the communication interface is the result of performing the calculation using the signal-processing circuit of Figure 4, and only the amplitude and phase of the FFT peak point are transmitted. The FFT peak is the point corresponding to 5.15186 MHz, which is the frequency of the input signal, and is the 14th value among the FFT calculation results. Additionally, multi-channel real-time data acquisition results are confirmed to be delivered to the PC via Ethernet communication at a speed of 1.2 Gbps. Note that we made the project in this paper available as an open-source platform, and it can be provided upon request [44].

6. Conclusions

In this paper, we propose a multi-channel data acquisition system using a 16-channel ADC capable of supporting up to 100 MSPS. In particular, we aim to reduce unnecessary signal transmission time by constructing an FPGA-based system that performs both data acquisition and processing on a single FPGA chip. Furthermore, we propose a real-time system with pipelining [16] and demonstrate that by implementing well-balanced pipelining, it is possible to design an optimal multi-channel real-time signal reception system without wasted time.

The proposed system enables data acquisition and processing to be performed on a single chip, thereby reducing the cost of system construction. In addition, the application of the proposed multi-channel real-time signal acquisition system to applications requiring real-time image processing is expected to result in a highly efficient design compared to existing studies [5,6,7,8,9,10,11,12].