FPGA-Based Multi-Channel Real-Time Data Acquisition System

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

Although the manuscript titled “FPGA-based multi-channel real-time data acquisition system” by S. Choi et al. falls within the scope of this journal, I do not recommend its publication for the following reasons.  

The primary issue is the lack of novelty in this work. There are commercial systems available that demonstrate similar or even much more advanced capabilities. For example, the microwave platform system manufactured by Intermodulation AB (https://intermod.pro/products/microwave-platforms) and the MCL1-540 system by Synktek AB. The latter possesses a somewhat reduced bandwidth, however, features much ADC resolution. This minimises the real difference in data transfer and processing rates. The only potential advantage of the system described in this manuscript is probably its lower cost. However, this advantage is negligible if the system cannot be reproduced by the readers with information provided in the manuscript (see my concluding comments). Furthermore, most of the important digital design in the present system relies on existing Xilinx IPs, and the signal processing methods used are well known, further diminishing the novelty of this work.

Secondly, there are various technical issues with the manuscript:

·       In lines 112 – 114, the authors claim that ADC settings can be passed on from the FPGA to the ADC, but this is not illustrated in Fig. 2. Additionally, they claim that the sampling clock is generated in the FPGA and passed to the ADC in lines 124 – 127, yet Fig. 2 shows the clock signal flowing in the opposite direction.

·       The methodology in section 4 is not unique, and its discussion is confusing and somewhat misleading. Eqns. (5) and (6) are not fully independent. The number of samples affects the number of clock cycles required for signal processing; in other words, N_samp and N_cc are related through the DSP routine used.

·       The statement “…to ensure uninterrupted signal reception, T_proc should not be shorter than T_recv” is incorrect. For a real-time system, the signal processing time needs to be shorter than the data acquisition time.

·       Fig. 8 is difficult to understand. Including data from 12 different channels does not automatically prove that the authors have successfully built a real-time sampling system, as it is unclear if the data were synchronously sampled without gaps. Systematic evaluation is necessary including assessing ADC nonlinearity, timing accuracy,  and phase error, etc.

To conclude, I suggest the authors revise the manuscript according to the comments above and consider publishing their results as an open-source project. This approach could significantly improve the impact of their work.

Comments on the Quality of English Language

Some minor typos must be corrected.

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This paper presents a streamlined data processing process to extract amplitude and phase of acquired signals. While the idea is interesting, it does not show the strength of the method very well. The use of FFT as an example for the signal processing reduces the interest, since any oscilloscope will be able to do the same thing than what the authors present. I would agree that good oscilloscopes are expensive and bulky, but cost is a relative thing if one accounts for the time to develop a new system versus buying one that does the job from the start.

The concept would be more interesting with a custom signal processing. The use of the FFT as an example is fair but it should be emphasized that other processes can be done. One consequence of the FFT choice is that the FPGA programming is simply a set of AMD(Xilinx) IPs put together, which reduces the originality of the method proposed here.

Whether there is interest for this paper in the journal is up to the editor, however, value aside, there are things that needs to be fixed before publication. Specifically:

- During most of the paper, the authors insists that the ADC can go up to 100MSPS, however, for the demonstration they use only 50MSPS. Why is this? if there is any justification to go slower than the max available, this should be mentioned.

- In the experimental result section, there is no mention of what signal was sent to the ADC. As a result, no one can say if the results shown in Figure 8 are correct or not. There is a label on the Y axis that says "amplitude", so I assume that it is the amplitude of the FFT computed by the FPGA since the authors say that only the amplitude and phase are sent to the computer. However, there is a '0' halfway up the Y axis, so it cannot be the FFT amplitude since this is always positive. There is no scale on the Y axis, so it is hard to decide what this represents.

- The authors make it sounds like only one 32-bit amplitude and one 32-bit phase per signal processed is being sent to the PC. If that is the case, are those the values at a given frequency or at the maximum frequency? there is no mention of this either

- Unless I missed it, the authors do not specify the frequency of the clock used to drive the FPGA; this would be helpful too, to see where the speed limitation of such a system is: ADC speed, FPGA, Ethernet link...

- on line 287, the authors say that "Tproc should not be shorter than Trecv". I believe they meant the opposite so that the data can be processed before the next set is available

- On line 178, it should be figure 4, not figure 6.

Overall, there are some minor mistakes that could be attributed to a lack of review before sending, but there are also missing data (e.g. waveform used in the experimental part) and missing information (e.g. what part of the FFT spectrum is sent to the PC). As a result, I cannot recommend publishing this paper without corrections.

Comments on the Quality of English Language

Overall, this paper is understandable, but there are a few places where the English needs to be fixed:

Line 73: "in this paper, TI ADS52J90 chip is analyzed the specification of the chip because this chip is used to configure the proposed system" should be something like " this paper focuses on the specification of the TI ADS52J90 chip that will be used in the proposed system".

Line 102, 109 and maybe others. Analog is more common than analogue when it comes to electronics

Line 143 "all data signals, including FCLK and BCLK, are differential signals and is required to receive through IBUFDS" should be "all data signals, including FCLK and BCLK, are differential signals and thus required to be received through IBUFDS"

Line 169 'Most signal receiver systems require some of digital signal processing" should be "Most system receiving a signal require some kind of signal processing"

Line 216, use "section" rather than "chapter".

 

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

While I appreciate the authors’ efforts in revising the manuscript, I regret to say that the revised manuscript still does not address my key comments and falls short of the requirements for publication.

Firstly, the authors have not provided sufficient evidence to support the novelty of their work. In their response, they compared their work to several commercial FPGA-based lock-in amplifiers I mentioned, but their analysis is unconvincing. All the lock-in amplifiers I cited use FPGA-based designs, where signal processing routines run on the FPGAs. Therefore, the authors’ claim that “since the signal processing algorithms are implemented directly in the FPGA, there is no limitation of the signal processing algorithm” is not a unique feature of their work. Additionally, all these commercial lock-in amplifiers incorporate advanced signal processing functions. For instance, the Presto-16 microwave platform by Intermodulation Products AB can demodulate at 192 frequencies simultaneously, whereas the system described in the manuscript only performs basic amplitude and phase analysis using FFT (see Figure 4). The authors’ assertion that “…existing lock-in amplifiers…do not support or have limited signal processing functions” is largely inaccurate. Furthermore, it is unclear why the authors believe their design is unique in suggesting that “if the system proposed in this paper is applied to a high-spec FPGA, it is possible to design a data acquisition platform that can apply a larger number of channels and signal processing algorithms”. In comparison, the Presto-16 microwave platform can sample 16 channels at 2.5 GS/s with a 14-bit resolution, far surpassing the capabilities of the system described in the manuscript (see lines 86 – 88). Last but not least, the authors highlight their pipelined design as a key novelty of the present work, yet pipelining is a common DSP technique and should not be considered as a significant justification for the publication.

Secondly, as mentioned in my previous comments, the system is poorly evaluated. The only real measurement results provided are a series of data points from 12 input channels shown in Fig. 8, but the timing accuracy of the data is unknown. Moreover, crucial parameters for measurement electronics, such as input noise, nonlinearity (harmonic and intermodulation distortion), and cross-talk, have not been measured.

In summary, the described measurement system does not represent a significant advancement compared to the state-of-the-art. Given its nature as a defence-related project, its design and source code cannot be disclosed at this moment, which is understandable. However, the impact of the manuscript if published in its current form, is expected to be limited. I recommend the authors wait until the embargo period is over and then publish it as an open-source project.

Comments on the Quality of English Language

n/a

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The authors answered my previous comments. I am still a bit confused by what figure 8 represents, or at least the value it adds to the paper. The output the FPGA send is the amplitude and phase at the input signal frequency. My best guess is that it is just a sine wave of the frequency measured by the FPGA starting at the phase provided by the FPGA with artificial sampling points that are supposed to represent where the sampling occurred. If that is the case, I do not see what value this figure adds to the paper; it feels like a waste of a full page. showing the raw results provided by the FPGA would be more valuable.

That said, if the editor is satisfied with this, I would not oppose publication.

 

Author Response

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Author Response File: Author Response.pdf

Round 3

Reviewer 1 Report

Comments and Suggestions for Authors

n/a

Comments on the Quality of English Language

n/a