This is an early access version, the complete PDF, HTML, and XML versions will be available soon.
Open AccessArticle
Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture
by
Jihwan Lim
Jihwan Lim ,
Jeonghun Son
Jeonghun Son and
Hoyoung Yoo
Hoyoung Yoo *
Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Republic of Korea
*
Author to whom correspondence should be addressed.
Electronics 2024, 13(15), 2971; https://doi.org/10.3390/electronics13152971 (registering DOI)
Submission received: 17 June 2024
/
Revised: 22 July 2024
/
Accepted: 25 July 2024
/
Published: 27 July 2024
Abstract
A lot of research on deep learning and big data has led to efficient methods for processing large volumes of data and research on conserving computing resources. Particularly in domains like the IoT (Internet of Things), where the computing power is constrained, efficiently processing large volumes of data to conserve resources is crucial. The processing-in-memory (PIM) architecture was introduced as a method for efficient large-scale data processing. However, PIM focuses on changes within the memory itself rather than addressing the needs of low-cost solutions such as the IoT. This paper proposes a new approach using the PIM architecture to overcome memory bottlenecks effectively in domains with computing performance constraints. We adopt the RISC-V instruction set architecture for our proposed PIM system’s design, implementation, and comprehensive performance evaluation. Our proposal expects to efficiently utilize low-spec systems like the IoT by minimizing core modifications and introducing PIM instructions at the ISA level to enable solutions that leverage PIM capabilities. We evaluate the performance of our proposed architecture by comparing it with existing structures using convolution operations, the fundamental unit of deep-learning and big data computations. The experimental results show our proposed structure achieves a 34.4% improvement in processing speed and 18% improvement in power consumption compared to conventional von Neumann-based architectures. This substantiates its effectiveness at the application level, extending to fields such as deep learning and big data.
Share and Cite
MDPI and ACS Style
Lim, J.; Son, J.; Yoo, H.
Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture. Electronics 2024, 13, 2971.
https://doi.org/10.3390/electronics13152971
AMA Style
Lim J, Son J, Yoo H.
Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture. Electronics. 2024; 13(15):2971.
https://doi.org/10.3390/electronics13152971
Chicago/Turabian Style
Lim, Jihwan, Jeonghun Son, and Hoyoung Yoo.
2024. "Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture" Electronics 13, no. 15: 2971.
https://doi.org/10.3390/electronics13152971
Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details
here.
Article Metrics
Article metric data becomes available approximately 24 hours after publication online.