Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture
Abstract
:1. Introduction
2. Background
2.1. Convolution
2.2. RISC-V RV32I Architecture
3. Proposed Design
4. Experimental Results
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
References
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PIM Instruction | Instruction Format | Meaning | |
---|---|---|---|
add | rd, rs2, rs1 | R-type | R[rd] = M[rs2]M[rs1] |
mul | rd, rs2, rs1 | R-type | R[rd] = M[rs2]M[rs1] |
slli | rd, rs1, imm | R-type | R[rd] = M[rs1]imm |
addi | rd, rs1, imm | R-type | R[rd] = M[rs1]imm |
Assembly Instruction | Meaning | |
---|---|---|
lw | x14, −32(x8) | Load data from address in memory R[x8]-32 to register x14 |
lw | x14, −56(x8) | Load data from address in memory R[x8]-56 to register x14 |
mul | x15, x14, x15 | Multiply the data in registers x14, x15 and store the result in register x15 |
sw | x15, −40(x9) | Store data in register x15 to address in memory R[x9]-40 |
lw | x14, −88(x9) | Load data from address in memory R[x9]-88 to register x14 |
lw | x15, −40(x9) | Load data from address in memory R[x9]-40 to register x15 |
add | x15, x14, x15 | Add the data in registers x14, x15 and store the result in register x15 |
sw | x15, −40(x9) | Store data in register x15 to address in memory R[x9]-40 |
PIM Instruction | Instruction Format | Meaning | |
---|---|---|---|
add.p | rd, imm(rs1), imm(rs1) | PIM-type | R[rd] = M[rs1+imm[25:20]]M[rs1+imm[31:26]] |
mul.p | rd, imm(rs1), imm(rs1) | PIM-type | R[rd] = M[rs1+imm[25:20]]M[rs1+imm[31:26]] |
slli.p | rd, imm(rs1), imm | PIM-type | R[rd] = M[rs1+imm[25:20]]imm[31:26] |
addi.p | rd, imm(rs1), imm | PIM-type | R[rd] = M[rs1+imm[25:20]]imm[31:26] |
Assembly Instruction | Meaning | |
---|---|---|
mul.p | x15, −32(x8), −56(x8) | Multiply (in PU) the data in memory R[x8]-32, R[x8]-56 and load to register x15 |
sw | x15, −40(x9) | Store data in register x15 to address in memory R[x9]-40 |
add.p | x15, −88(x9), −40(x9) | Add (in PU) the data in memory R[x9]-88, R[x9]-40 and store to register x15 |
sw | x15, −88(x9) | Store data in register x15 to address in memory R[x9]-88 |
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Lim, J.; Son, J.; Yoo, H. Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture. Electronics 2024, 13, 2971. https://doi.org/10.3390/electronics13152971
Lim J, Son J, Yoo H. Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture. Electronics. 2024; 13(15):2971. https://doi.org/10.3390/electronics13152971
Chicago/Turabian StyleLim, Jihwan, Jeonghun Son, and Hoyoung Yoo. 2024. "Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture" Electronics 13, no. 15: 2971. https://doi.org/10.3390/electronics13152971