Design of High-Reliability Low-Dropout Regulator Combined with Silicon Controlled Rectifier-Based Electrostatic Discharge Protection Circuit Using Dynamic Dual Buffer

Abstract

Overshoot and undershoot caused by the current load impact the accuracy of the required output voltage and circuit performance. The transient response issue in existing low-dropout (LDO) regulators is a dynamic specification that must be addressed at the design stage. This transient response is influenced by system parameters such as stability and gain. The LDO regulator suggested in this study is designed to minimize the change in output voltage by considerably enhancing the gain using a dynamic dual buffer structure. A dynamic dual buffer is utilized to effectively control undershoot and overshoot. Under the conditions that the input voltage range is from 3.3 to 4.5 V, the maximum load current is 300 mA, the output voltage is 3 V, and the output of the proposed LDO regulator with the dynamic dual buffer structure has undershoot and overshoot voltages of 41 mV and 31 mV, respectively. That is, the output voltage of the proposed LDO regulator effectively provided and discharged an additional current suited for the undershoot/overshoot conditions to enhance the transient response characteristics. Furthermore, the electrostatic discharge (ESD) robustness characteristics of the proposed LDO regulator improved because of the silicon-controlled rectifier underlying the ESD protection device embedded in the output node and power line.

1. Introduction

At present, advancements in technology and the use of portable electronic devices, such as smartwatches, Bluetooth earphones, and wearable applications, are occurring. Accordingly, users’ demands are also diverse. Among these demands, the biggest issue is an efficient battery supply with excellent sustainability, alongside a limited battery capacity and the convenience of using various applications. As a result, Figure 1 shows the significant ability of PMICs (Power-Management-Integrated Circuits) to improve the battery-driving capability. PMICs play an important part in converting and controlling power according to the system, requiring different powers in portable devices, such as mobile devices and IoT (Internet of Things), to achieve optimized battery performance. Therefore, engineers are striving to provide electronic products with high-level performance and high-efficiency battery-driving technology [1,2,3,4,5]. Among them, Figure 2 shows LDO regulators playing a central role in smartphones, healthcare devices, tablet PCs, and various mobile devices. The power loss in devices that must operate under different voltage and current conditions must be minimized, and the noise of the output voltage must be reduced. Additionally, dozens of LDO regulators must be designed to respond to numerous mobile devices with load conditions that change instantaneously. This design effort is critical to ensure the overall performance and stability of the device. On the other hand, these LDO regulators can shorten battery life. The most important solution to this problem is to develop an LDO regulator with excellent efficiency, such as a low quiescent current and a low peak voltage, for the efficient power management of battery-operated electronic products. Applications of mobile devices are the key components that significantly affect energy efficiency, response speed, and execution time. Power efficiency can be improved by developing an LDO regulator that can control the output voltage and load current while minimizing the impact of rapidly switching loads in various ways [6,7,8,9,10]. In addition, an LDO regulator must not only provide different supply voltages appropriately for each system but also operate stably under ESD (electrostatic discharge) conditions. ESD refers to a phenomenon in which charges rapidly move between two objects due to the potential difference when two objects with different potentials are blended. If a large current is applied for a short period of time, it becomes impossible to supply the appropriate voltage for each system. This damages the entire IC, including the LDO regulator. To prevent these problems, Figure 3 shows that an ESD protection circuit is intended to safely protect the IC when an ESD phenomenon occurs and to secure high reliability and sustainability. The most widely used ESD devices are GGNMOS and diode structures. However, SCRs, which have an excellent current-driving capability in small areas, are suitable for the ESD protection circuit of the IC. It is also important to design an ESD protection circuit by embedding it between the VDD-VSS and VOUT-VSS of the LDO regulator. When an ESD surge is implemented in the VDD node and exceeds the breakdown voltage of the internal components of the LDO regulator, the transistor of the LDO regulator may be damaged and cause a malfunction. Therefore, it is significant to include an ESD protection circuit between the VDD-VSS and VOUT-VSS of the LDO regulator so that the ESD surge can be safely discharged through the ESD clamp. Finally, the ESD protection circuit network is designed and manufactured by embedding the LDO regulator.

2. The Proposed LDO Regulator with ESD Protection Structure

2.1. The Proposed LDO Regulator with Dynamic Dual Buffer

Figure 4 shows the existing LDO regulator. In the case of the existing LDO regulators, large overshoot and undershoot occur when the output voltage changes due to a momentarily changing load current. This is due to the charge and discharge times of the large parasitic capacitance of the pass transistor. The proposed LDO regulator maximizes the gain and adjusts the unity gain bandwidth (UGBW) to minimize the effect of the load current and reduce changes in the output voltage. Overshoot and undershoot due to the influence of the load current generated from the existing LDO regulator is necessary for the gain of the overall system.

Through the proposed buffer structure, we propose an LDO regulator that can reduce the output resistance compared to the existing buffer structure. The proposed buffer structure behaves differently under undershoot and overshoot situations. The input voltage of the high-gain buffer structure due to an undershoot situation is detected as a low voltage, and the output voltage is operated to lower accordingly. Therefore, in this situation, the supply current stage of the high-gain buffer structure is designed not to operate. In an overshoot situation, the input voltage of the high-gain buffer structure is sensed to be higher, and the output voltage is operated to increase accordingly. Therefore, in this situation, the discharge current stage of the high-gain buffer structure is designed not to operate. The proposed buffer structure supplies current in switch mode in overshoot situations. This is because if it is designed to supply current at all times, the problem of a significant increase in quiescent current occurs. Therefore, it is designed to effectively supply and discharge current depending on overshoot and undershoot situations. The buffer serves to lower the output resistance, and in the existing buffer structure, the output resistance is expressed as ${\displaystyle \frac{1}{G_m}}$. To reduce the output resistance in the existing buffer structure, the size of the input MOSFET must be increased. However, this affects the entire LDO regulator system and has limitations in reducing output resistance. Figure 5 shows the dynamic dual buffer structure. Dynamic dual buffer output resistance can be lowered further than existing buffer structures. In the dynamic dual buffer structure, when $∆V_{out}$ occurs due to changes in output voltage, the current is generated through changes in $M_1$. The current change in $M_1$ can be expressed as $r_{o1}$because the drain terminal of $M_1$ and the gate terminal of $M_2$ are connected. Therefore, even if the output voltage changes, only the current path of $r_{o1}$is created. Due to $M_1$current flow, the voltage value in Equation (1) is formed. The $V_{M2gate}$voltage becomes (2). $∆V_{out} \left(1+G_{m1}\ast r_{o1}\right)$ means $V_{M2gate}$voltage, so you can also check the current change in $M_2$. Equation (3) represents the current change in $M_2$caused by the change in output voltage. Depending on the change in output voltage, variation in the current occurring in $M_2$ and the current occurring in $r_{o2}$can be confirmed, and the values are expressed in Equation (4). As a result, the output resistance is formed to be smaller than that of the existing buffer structure, as shown in (5) [11,12,13,14,15].

$$V_{M_1}=G_{m1}\ast ∆V_{out}\ast r_{o1 }$$

(1)

$$V_{M_{2gate}}=∆V_{out}+G_{m1}\ast ∆V_{out}\ast r_{o1 }$$

(2)

$${∆I}_{M_{2}gate}=∆{ V}_{out}\left(1+G_{m1}\ast r_{o1}\right)\ast G_{m2}$$

(3)

$$∆I=∆V_{out} \left(1+G_{m1}\ast r_{o1}\right)\ast G_{m2}+{\displaystyle \frac{∆V_{out}}{r_{o2}}}$$

(4)

$$Rout={\displaystyle \frac{1}{\left(\left(1+G_{m1}\ast r_{o1}\right)\ast G_{m2}+\frac{1}{r_{o2}}\right)}}$$

(5)

The output voltage of the LDO regulator changes rapidly with gain amplification. To respond to these changes, dynamic dual buffers, which effectively transfer the twice-amplified gain to the gate terminal of the pass transistor, are essential. Figure 6 shows the dynamic dual buffers of the proposed LDO regulator operating in an overshoot situation. When a high voltage is applied to the input terminal of dynamic dual buffers, this means that the load current at the output terminal of the LDO regulator increases. As a result, dynamic dual buffers increase the voltage at the output voltage terminal and generate inverter current. The generated inverter current supplies supplementary current to the gate terminal of the pass transistor. Additionally, the gate voltage of $M_3$ forms a path to discharge supplementary current flowing to the output terminal of the proposed LDO regulator. As a result, the proposed LDO regulator can more efficiently regulate rapidly and momentarily changing voltages. Figure 7 shows the dynamic dual buffer of the proposed LDO operating in an undershoot situation. When a low voltage is used for the input terminal of the dynamic dual buffers, this implies that the output voltage of the LDO regulator has decreased due to the load current. By maintaining a low voltage at the input of dynamic dual buffers, the current path of $M_2$ is formed. At the same time, the inverter senses the feedback voltage of the proposed LDO regulator and establishes an additional supply current path due to undershoot. The low voltage generated at the input blocks the inverter current but creates an additional current path. In other words, the proposed LDO regulator efficiently lowers the gate voltage of the pass transistor through the current path of the two MOSFETs and configures a path to supply added current to the output terminal. The proposed LDO regulator amplifies the gain through the feedback voltage of the positive terminal, unlike the amplifier of the existing LDO regulator that uses the negative terminal as the input voltage. As a result, the amplifier in the proposed LDO regulator performs normal feedback operation through the output inversion generated in the subsequent stage. Therefore, it has higher gain and improved output performance compared to the error amplifier of the existing LDO regulator. R1 and R2 in the error amplifier of the proposed LDO regulator are stationary resistors in the output stage. Therefore, in order to reduce the $g_m$ of the input MOSFET, an additional resistor was configured to raise only the Y-axis gain without altering the Bode plot. Figure 8b illustrates the schematic of the circuit, which is designed in three stages to enhance the gain in the proposed LDO regulator. The dynamic capacitor applied to the proposed LDO regulator is connected between the drain terminal and output terminal of the amplifier’s input MOSFET and between the drain terminal of the amplifier’s input MOSFET and the output terminal of the second amplifier to ensure stability by maintaining high loop gain. Two compensation capacitors were formed to form the dominant pole and secondary pole of the LDO system. Because it is an LDO regulator that uses a large external capacitor, the problem of the dominant pole changing to the secondary pole depending on the load current is fatal, making it difficult to achieve stability in the system. Therefore, high gain and stability were secured by fixing the dominant pole through a compensation capacitor. In addition, an additional current path was simultaneously created by configuring a dynamic push-pull structure from the output terminal of the amplifier to the output terminal of the proposed LDO regulator. A decrease in the output voltage of the amplifier means that an undershoot voltage has occurred due to the load current, which corresponds to a change in the output voltage. In the output voltage stage of the proposed LDO regulator, supplementary current is provided to sustain the effective output voltage variation. Conversely, since an increase in the output voltage of the amplifier means that the overshoot voltage generated by the change in load current has occurred, and a supplementary current discharge path can be created for an effective change in the output voltage. Therefore, the proposed LDO regulator not only includes a further current supply function but also a discharge function to keep the output voltage more consistent [16,17,18,19,20].

2.2. SCR-Based ESD Protection Circuit

Figure 9 shows the ESD design window and key parameters. Since the ESD protection circuit should not directly or indirectly affect the normal circuit operation, it is essential to design it appropriately according to the target application voltage. The ESD design window is divided into the Core Damage Region and the Supply Voltage Region, and the ESD design window is determined among the two regions. If the supply voltage range is exceeded, the voltage intended for the internal IC will also be directed to the ESD protection circuit. This will result in the ESD protection circuit not turning off and continuously discharging current. This is called the latch-up phenomenon. Additional current discharge above the normal current level due to the latch-up phenomenon can cause increased power consumption and propagation delay and can cause distortion of the input signal entering the internal circuit. Next, if the Core Damage Region is violated, this will cause a breakdown of the Gate Oxide, provoking Lethal damage to the IC and making it impossible to operate normally. Due to this phenomenon, it can be seen as essential to design within the ESD design window. As a result, the important operations of the ESD protection circuit are as follows. First, the holding voltage (Vh) must be higher than the internal Supply Voltage Region plus about 10% margin. This is to prevent the latch-up issue described above. Second, the trigger voltage (Vt1) must be lower than the internal Core Damage Region. Finally, It2 (second breakdown current) is an index that can confirm the tolerance characteristics among the characteristics of ESD. The proposed ESD protection circuit was designed to be optimized for a 5 V application voltage.

Figure 10 shows the cross-sectional perspective and internal circuit diagram of LVTSCR. The structure of LVTSCR is the conventional SCR structure, in which a ground gate NMOS (GGNMOS) is inserted, and in the conventional structure, when an ESD surge was applied to the anode, an avalanche breakdown occurred at the junction between the N-WELL and the P-WELL. However, in this structure, the N+ bridge region was inserted to cause an avalanche breakdown between the N+ implant region and the P-WELL, thereby lowering the trigger voltage. Figure 11 shows the cross-sectional view and internal circuit diagram of LRSCR. In the case of LRSCR, first, compared to the conventional SCR in terms of structure, a ground gate NMOS (GGNMOS) is inserted, and the avalanche breakdown phenomenon that occurs between the N-WELL and P-WELL when an ESD surge is applied was reduced by causing an avalanche breakdown between the N+ bridge region and the P-WELL. In addition, a P+ implant region was added to the P-WELL on the left side of the N-WELL. Finally, the P+ implant region is connected to the anode terminal, and the parasitic PNP bipolar transistor (QPNP2) is turned on one more compared to the conventional SCR and LVTSCR, thereby improving the holding voltage and on-resistance characteristics. As a result, it has the characteristic of lowering the trigger voltage similar to the LVTSCR and the characteristic of growing the holding voltage by operating the parasitic PNP bipolar transistor (QPNP2). Figure 12 shows the cross-sectional view and internal circuit diagram of the proposed NLRSCR. The proposed structure was designed by modifying the conventional LVTSCR and LRSCR structures. The operating principle of the proposed NLRSCR structure is as follows. First, when an ESD surge is applied to the anode terminals on both sides, the potential of the N-WELL increases. At this time, the potential of the N+ bridge region also increases simultaneously due to the increased potential of the N-WELL. At this time, since the reverse junction between the N+ bridge region and the P-WELL is formed, avalanche breakdown occurs when it reaches a threshold value or higher. Avalanche breakdown generates electron–hole pairs. The created electron current flows out to N+ in the anode region, and the hole current moves out to P+ in the cathode region. This causes the potential of the P-WELL to rise, and a forward junction occurs between the P-WELL and N+ in the cathode region. The parallel-connected parasitic NPN bipolar transistors (QNPN1, QNPN2) are turned on due to the forward junction. Afterward, the current flowing in the turned-on parasitic NPN bipolar transistor operates on the parasitic PNP (QPNP1). As a result, a total of three parasitic bipolar transistors (QNPN1, QNPN2, QPNP1) form an SCR positive feedback structure and discharge a considerable amount of ESD surge. The structural features of the proposed ESD cross-section are as follows: first, the avalanche breakdown occurring between the N-WELL and the P-WELL is lowered by adding the N+ bridge region to lower the trigger voltage, and the N-WELL and N+ region are added to turn on the parasitic bipolar transistor (QNPN2) to improve the on-resistance characteristics. In addition, the P+ floating diffusion region is added to the P-WELL to reduce the current gain of the parasitic bipolar transistor (QNPN2), thereby improving the holding voltage. The structural characteristics are improved to make it optimal for 5 V low-voltage applications [21,22,23,24,25,26,27,28,29,30,31,32,33].

Figure 13 is an LDO block diagram and shows the proposed ESD clamp combined. It was suitable for the 5 V ESD design window, considering the operating voltage of the LDO regulator. An ESD clamp is located between the VDD-VSS and VOUT-VSS of the proposed LDO regulator. It also operates to safely discharge the ESD surge when applied. It is designed to suit the target voltage of the LDO regulator. It is triggered before the junction breakdown and gate-oxide breakdown of the LDO internal circuit occurs and discharges the ESD surge to VSS, allowing the proposed LDO regulator to control.

3. Measurement Result

3.1. Layout of the Proposed LDO Regulator

Figure 14 shows the actual chip photo and layout of the proposed LDO regulator. The size of the proposed LDO regulator is 450 × 372 μ${\mathrm{m}}^2$. Additionally, an ESD protection circuit was placed for the VOUT-VSS and VDD-VSS terminals.

3.2. Load Transient Response

The main function of the LDO regulator is to offer a stable output voltage regardless of the load current. However, in portable applications, the output voltage may be affected by the load step. In addition, the load transient response characteristic refers to the ability to maintain a constant output voltage despite a sudden load change in the output stage. The proposed LDO regulator minimizes the output voltage fluctuation according to the load current by maximizing the gain and controlling the unity gain bandwidth (UGBW). It can be confirmed through measurements that the overshoot and undershoot caused by the load current in the LDO regulator including the dynamic dual buffer structure are proportional to the overall gain of the system. The following is the measurement result of the proposed LDO regulator and the measurement result after the ESD zapping test is presented. The ESD zapping test discharged the positive ESD stress to the proposed LDO regulator in the order of (4 kV, 6 kV, and 8 kV) of HBM three times each according to the combination of each pin in PS modes, and the time between discharges was 1 s. In Figure 15, when the load current is suddenly changed to 200 mA, the characteristics of 18 mV in the undershoot condition and 21 mV in the overshoot condition can be confirmed. In Figure 16, when the load current is suddenly changed to 300 mA, the output voltage change of 41 mV in the undershoot condition and 31 mV in the overshoot condition can be confirmed. In general, the peak voltage value occurs significantly according to the large load current. As a result, it was established that the proposed LDO regulator effectively improves the peak voltage change even at the large load current by using the dynamic dual buffer structure.

3.3. Load Regulation

Figure 17 shows the load regulation measurement results of the proposed LDO regulator. Load regulation refers to the voltage of the output terminal that changes as the load current continuously increases. It was confirmed that the proposed LDO regulator with the ESD protection circuit combined showed an output voltage change of 9.58 mV in the load current range up to 300 mA even after the ESD situation of 8 kV was applied. In contrast, the LDO regulator without the ESD protection circuit combined, normal operation was not guaranteed even after a low ESD situation of 2 kV, and a very large load regulation characteristic was confirmed.

3.4. Line Regulation

Figure 18 shows the line regulation measurement results of the proposed LDO regulator. Line regulation refers to the amount of change in the output voltage when the input voltage changes. In the case of the suggested LDO regulator featuring an ESD protection circuit, it safely discharges the ESD surge even after a high ESD situation of HBM = 8 KV, ensuring normal regulation. As a result, it was demonstrated that the proposed LDO regulator had an output voltage change of 4.38 mV from the input voltage of 3.3 V to 4.5 V. However, it was confirmed that the LDO regulator without the ESD protection circuit could not safely discharge the ESD surge despite the relatively low ESD situation of HBM = 2 kV, thus failing to ensure normal operation.

3.5. Quiescent Current

Quiescent current refers to the minimum input current that the LDO regulator requires to maintain a constant output voltage. A large amount of current continuously consumed in the system can adversely affect the battery life because the battery capacity is limited. Moreover, since the PMIC system is composed of numerous circuits, current consumption is one of the very important characteristics. Figure 19 shows the quiescent current of the proposed LDO regulator. In the case of the proposed LDO regulator without the ESD protection circuit, normal operation is not secured due to damage and destruction of the internal circuit even under a relatively low ESD surge of HBM = 2 kV, and the quiescent current also increases. On the other hand, the proposed LDO regulator with the ESD protection circuit was confirmed to safely discharge a high level of ESD surge of HBM = 8 kV, ensuring the common operation of the internal circuit. Therefore, the quiescent current characteristic of a maximum of 59 µA and a minimum of 52 µA was confirmed over the input voltage range.

3.6. PSRR (Power Supply Rejection Ratio)

Figure 20 shows the simulation results of the PSRR of the proposed LDO regulator. A wide variety of modern semiconductors and electronic components are essential for improving the performance of evolving mobile and other electronic devices. Among these, the semiconductor components provided by LDO regulators operate at low voltages, and certain devices, such as image sensors, are particularly sensitive to the accuracy and stability of the supply voltage. If the precision of LDO regulator voltage regulation is poor, problems may occur in the operation of electronic devices or their electrical characteristics may deteriorate. For top-performing semiconductor devices to operate smoothly, LDO regulators must provide a stable, accurately regulated voltage. The output voltage of an LDO regulator is affected by several factors, one of which is the variation in the input voltage. For example, if the input voltage to the LDO regulator comes from a DC–DC converter, switching noise or other noise from that converter can affect the LDO regulator’s input. Since the LDO regulator generates an output voltage from this input voltage, ripple in the output voltage must be minimized to avoid negatively impacting the load. The LDO regulator’s function to suppress such ripples is called PSRR (Power Supply Rejection Ratio), which is one of the important characteristics of the LDO regulator. The PSRR of the LDO regulator, i.e., its ability to suppress the ripple of the input voltage (Vin), is expressed by Equation (6). As a result of the simulation, the PSRR of the proposed LDO regulator was confirmed to have a maximum value of approximately −34 dB and a minimum value of approximately −100 dB.

$$PSRR=20log{\displaystyle \frac{V_{INRPL}}{V_{OUTRPL}}} [\mathrm{d}\mathrm{B}]$$

(6)

3.7. Pole Split Compensation

The pole split compensation method in Figure 21 can effectively cause pole splitting in the LDO regulator system. In addition, a higher gain can be obtained by using a smaller capacitor than the compensation method using a Miller capacitor, and the split between the dominant pole and the second pole can be made larger than the compensation method using a Miller capacitor. And one of the key advantages of the pole split compensation method is that the feedforward loop is eliminated. In the compensation method using a Miller capacitor, the RHP (Right-Half Plane) zero phenomenon occurs due to the feedforward loop. However, the pole split compensation method can eliminate the phenomenon caused by the feedforward loop. If there is a change in the feedforward loop, the change in the output terminal of the error amp occurs due to the change in the output terminal of the LDO regulator. Additionally, the feedforward loop change will simultaneously form a CG (Common Gate) change at the output stage of the error amp. After the change goes through pass tr, the signal formed by the feedforward loop is removed. Figure 22, Figure 23 and Figure 24 show the result. It is an effective compensation method that can be used by initially eliminating the RHP (Right-Half Plane) zero phenomenon that can occur in compensation methods using Miller capacitors. The effect of the pole split compensation method is meaningful in re-establishing the two poles. As the pole split capacitor grows, the dominant pole moves to the low-frequency range. Additionally, since the second pole moves in a high-frequency band, a pole split effect is created.

3.8. Power Efficiency

Figure 25 shows the power efficiency of the LDO regulator. The efficiency of an LDO is the input power to the output power, and the output voltage is the input voltage minus the dropout voltage. The input current is the sum of the load current and the quiescent current consumed by the LDO controller. To achieve high efficiency, the dropout voltage and quiescent current must be lowered. Quiescent current is closely related to the response speed of the LDO and has a trade-off relationship with efficiency. The equation for power efficiency is as follows. The minimum input voltage of the proposed LDO regulator is 3.3 V, the minimum output voltage is 3 V, the maximum input voltage is 4.5 V, and the maximum output voltage is 4.2 V, so the proposed LDO regulator has a minimum power efficiency of 90.9% and a maximum power efficiency of 93.3%.

$$Efficiency={\displaystyle \frac{V_{OUT}\ast I_L}{V_{IN}\ast I_{IN}}}={\displaystyle \frac{V_{OUT}\ast I_L}{V_{IN}\ast (I_L+I_Q)}}={\displaystyle \frac{(V_{IN}\ast V_{DO})\ast I_L}{V_{IN}\ast (I_L+I_Q)}} [\%]$$

(7)

3.9. ESD Characteristic Evaluation

Figure 26 shows the I-V characteristics measured by applying a Transmission Line Pulse (TLP) to compare the electrical characteristics of the LVTSCR, LRSCR, and the proposed NLRSCR ESD protection circuits. To apply the proposed LDO regulator, the ESD design window should surpass 4.95 V (the maximum operating voltage of the proposed LDO regulator + 10% margin). However, if the holding voltage of the conventional LVTSCR is 3.68 V, it may intrude on the operating area of the internal IC and create issues such as latch-up. The proposed NLRSCR ESD protection circuit has a holding voltage of 6.8 V and a trigger voltage of 9.1 V. Comparing the trigger voltage values, the trigger voltage of the LVTSCR is lower than 10.8 V, and even lower than the trigger voltage of 9.2 V for the LRSCR. Therefore, the proposed NLRSCR ESD protection circuit is suitable for the 5 V class ESD design window and at the same time, it can operate the proposed regulator stably to increase reliability.

Figure 27 and Figure 28 show the thermal robustness of the proposed ESD protection circuit under high-temperature conditions (300–500 K), and the I-V characteristics were evaluated using a TLP system. The high-temperature characteristics are essential because they greatly affect the ESD protection circuit and the It2 (second breakdown current) and the electrical characteristics of the circuit. The base-emitter voltage (VBE) of the parasitic NPN/PNP bipolar transistor decreases, which reduces the holding voltage similar to (7). Furthermore, the holding current decreases due to the decrease in carrier mobility and the increase in the well area and substrate resistance at high temperatures, as in (8). In addition, as the temperature increases, thermal energy loss resulting from the thermal resistance of It2 increases, which reduces It2.

$${\mathrm{V}}_{\mathrm{h}}={\mathrm{V}}_{\mathrm{E}\mathrm{B}\mathrm{Q}1}+{\mathrm{V}}_{\mathrm{B}\mathrm{C}\mathrm{Q}1}+{\mathrm{V}}_{\mathrm{E}\mathrm{B}\mathrm{Q}2}$$

(8)

$${\mathrm{V}}_{\mathrm{h}}={\mathrm{V}}_{\mathrm{B}\mathrm{E}\mathrm{o}\mathrm{n}}+{\mathrm{V}}_{\mathrm{B}\mathrm{C}\mathrm{Q}1}$$

(9)

$${ I}_h={\displaystyle \frac{V_{BEon}}{{\beta }_{NPN }{\beta }_{PNP}-1}} \left[ {\displaystyle \frac{1}{R_n}}\left({\beta }_{PNP}+1\right){ \beta }_{NPN}+\left.{\displaystyle \frac{1}{R_p}}\left({\beta }_{NPN}+1\right){ \beta }_{PNP} \right]\right.$$

(10)

The measurement results show that the holding voltage of the conventional LVTSCR is 3.1 V and the secondary trigger current is 4.74 A at a temperature of 500 K. Conversely, the holding voltage of the LRSCR is 5.25 V and the secondary trigger current is 5.02 A. On the other hand, the holding voltage of the proposed NLRSCR ESD protection circuit is 5.58 V. The secondary trigger current remains high at 7.04 A, which confirms that the proposed ESD protection circuit exhibits superior thermal reliability and performs well at high temperatures compared to the conventional LVTSCR and LRSCR.

Figure 29 and Figure 30 indicate the results of the TLU (Transient Latch-Up) test to ensure the latch-up immunity of the LVTSCR and the proposed ESD protection circuit in 5 V applications. Latch-up triggered by ESD pulses is one of the main causes that can affect the damage and destruction of ICs. In order to apply the ESD pulse to the experimental target, a capacitor charged on the positive side is used, and the power supply is connected to a 5 V DC voltage corresponding to the internal circuit operating voltage of the same node. The voltage waveform is observed using an oscilloscope. In addition, the latch-up immunity characteristics under the overshoot condition of the ESD device can be verified through the TLU test. In Figure 29, the holding voltage of the LVTSCR is low at 3.68 V, which causes a pull-down, resulting in a fixed voltage of 3.5 V. However, in the case of the proposed NLRSCR, the holding voltage is 6 V and the DC supply voltage is more than 5 V. After the ESD protection circuit was activated, the supply voltage was maintained at 5 V, as shown in Figure 30, proving latch-up immunity.

Table 1. I/O Clamp, Power Clamp result for dynamic dual buffer structure LDO regulator.

Structure	Temp	HBM	MM
I/O Clamp	100	>8 kV	>800 V
	200	>8 kV	>800 V
	300	>8 kV	>800 V
	400	>8 kV	>800 V
	500	>8 kV	>800 V
Power Clamp	100	>8 kV	>800 V
	200	>8 kV	>800 V
	300	>8 kV	>800 V
	400	>8 kV	>800 V
	500	>8 kV	>800 V

summarizes the results of the HBM (Human Body Model) and MM (Machine Model) evaluations of the I/O and Power Clamp according to temperature. Looking at the results at high temperature (500 K), the I/O Clamp shows high durability of HBM 8 kV or higher and MM 800 V or higher, and the Power Clamp also has excellent durability of HBM 8 kV or higher and MM 800 V or higher. This confirms that the proposed ESD protection circuit has remarkable thermal reliability and durability.

4. Conclusions

In actual smartphone systems, the actual role of the regulator is to provide a stable and fixed voltage. When a user uses a smartphone, the brightness of the screen sometimes becomes brighter and the load current of the system changes significantly depending on the situation. Even when the load current changes, providing a constant fixed voltage becomes the basis for the load system to operate stably. The purpose of this paper is to review existing problems related to LDO regulators based on high reliability and to verify an LDO regulator with high reliability through improved transient characteristics and a built-in ESD protection circuit. It is essential for an LDO regulator to provide stable output voltage and peak voltage according to load current changes. In order to embed an ESD protection circuit in the LDO regulator, it is important to configure the network by placing the ESD protection circuit between VDD-VSS and VOUT-VSS. When an ESD surge is applied to the VDD node, the breakdown voltage of the internal components of the LDO regulator may be exceeded, damaging the transistors of the LDO regulator and causing malfunction. Additionally, because the output node of the LDO regulator is connected to the system load or another IC system, an ESD surge applied to the output node can exceed the acceptable voltage levels of the IC to which the LDO regulator is connected, damaging or completely destroying the components. Therefore, VDD-VSS and VOUT-VSS have built-in ESD protection circuitry to quickly respond to ESD events and mitigate their effects. The dynamic dual buffer structure of the proposed LDO regulator effectively detects changes in output voltage and forms additional current supply and discharge paths. As a result, the load system is designed to operate stably by providing a constant, fixed voltage even when the load current changes. It was confirmed that by providing additional discharge current at the output terminal of the proposed LDO regulator, the voltage that changes rapidly in an instant can be maintained more consistently. Conversely, even under overshoot conditions that create a dynamic dual buffer current path due to maintaining a high voltage at the input terminal, an additional current discharge path due to the inverter and an additional supply current path are formed at the output terminal of the LDO regulator to keep the gate voltage of the pass transistor constant. It was confirmed that it was maintained. As shown in

Table 2. Performance comparison and summary with proposed LDO regulator.

	This Work	[2]	[5]	[8]	[10]
Technology (m)	0.18	0.065	0.065	0.13	0.18
Supply Voltage(V)	3.3–4.5	1.05–1.2	0.75–1.2	-	1.5
Output Voltage (V)	3.3	0.9	0.55	1.2	1.2
Load Current: IMAX (mA)	300	20	50	20	100
Quiescent Current (µA)	52–59	65	15.9–487	100	2.4–242
Load Transient (ILOAD Rising) (mV)	41	88	51	90	125
Load Transient (ILOAD Falling) (mV)	31	35	52	95	65
Load Regulation (mV)	9.58	-	9	-	0.14
Line Regulation (mV)	6.42	-	4.8	-	12.3
COUT (µF)	2.2	0–0.001	0.01	0.00014	0.00014
T(edge) (ns)	500	5	100	10	100
FoM(1) (V)	4.03 × 10−12	1.46 × 10−11	4.97 × 10−11	5.00 × 10−12	3.15 × 10−11
Year	2024	2020	2014	2020	2015

, the proposed LDO regulator was proven to be a suitable solution for the smooth operation of mobile applications that require sensitive voltage regulation. In addition, since we are directly facing reliability and stability problems due to IC damage and destruction due to ESD, the proposed LDO regulator secured excellent robustness and high reliability over HBM 8 kV and MM 800 V by applying the NLRSCR ESD protection circuit.